SU1425687A1 - Program debugging device - Google Patents

Abstract

The invention relates to automation and computing, and can be used when debugging programs of microprocessor systems. The aim of the invention is to expand the functionality of the device by providing debugging programs in real conditions. The device contains a control unit 1, data registers 2 and 11, data indication units 3 and 8, address 4 register 5, address indication block 5, comparison blocks 6 and 10, respectively, addresses and data, stop address register 12, decoder 13 high-order address bits , elements AND NOT 14-17. The device provides various modes of information exchange between the device blocks and between the device and the microprocessor system being debugged, additional possibilities for storing and displaying addressing information to the debug memory. 1 hp f-ly, 1 nl. (L

Description

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The invention relates to computing and can be used to debug software and hardware and test microprocessor systems (MPS).

The aim of the invention is to expand the functionality of the device by debugging programs in real conditions.

The drawing shows a block diagram of a device for debugging programs. The circuit contains a control unit 1, a first data register 2, a first data indication block 3, an address register 4, an address indication block 5, an address comparison block 6, a data register 7, a second data indication block 8, a debugging parameter block 9, block

10 data comparisons, second register

11data, address address register 12, decoder 13 st1, thirteen address bits, AND-NOT lA-l elements, register of 18 modes, decoder 19 control unit commands, AND elements 20 and 21, OR elements 22 and 23, blocks 24

and 25 delays.

In addition, the drawing shows the inputs-outputs 26-124.

The device works in the following way.

: When writing information to block 9 of debugging memory in data register 2 and address register 4, the data and the address are preliminarily entered, and: at the first input of the register data. 2 Sdanny from the input device arrive Sdanny on the signal arriving at the input of the data register 2 register, and I to the first address input of the register 4 address receives the address from the input device on the signal at the input of the register 4 address from the output of the decoder 19 commands. Controls (the signals are generated by the control unit 1 upon receipt of information from the input device, data and the command sign at the inputs of the command decoder 19. From the output of the data recorder 2, the code is inputted to the information input of the debugging memory unit 9 and recorded on the input signal recordings of debug memory block 9 at the address received at the address input of block 9 from the output of address register 4. Address for writing or reading is made to the 8-bit cell of block 9, if the inputs of the AND-NOT elements are respectively

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14–17 a logic unit level signal is received. In the case of the arrival at one of the outputs of the decoder of the 13 most significant bits of the signal of the logical zero level at the input of one of the elements AND 14, 15, 16 and 17, the signal of the logical unit is output at the output of the corresponding element. The call is made to a 24-bit memory cell. If zero potentials arrive at the inputs of the AND-14-14 elements, when reading from block 9 by a command from the input device, the address is written to the address register 4 in the same way as when writing to the debug memory block 9. Reading from debug memory block 9 is performed by a signal received at the read input from the output of the element OR 23. The signal at the output of the element OR 23 appears when a signal arrives at its input from the output of the decoder 19 commands.

The information from the output of block 9 of the debugging memory arrives at the information input of the data register 2 and: is entered into it by a signal received at its record input from the output of the delay block 2. The delay unit 2 serves to delay the read time from the debug memory block 9, therefore the write signal to the data register 2 arrives at its write input after the data in the debug memory block 9 appears at the output. The information from the output of the register-2 data is fed to the data input of the data indication unit 3. The signal to the control input of this display unit prohibits or enables the display, depending on its level. Each time information is exchanged between blocks of a device for debugging programs from a debugging microprocessor system with an I / O device, the mode register 18 is preloaded with a code that is interpreted by control unit 1 and determines the direction and mode of exchange. The code arrives at the information input of the register 18 of the iMOB from the input-output device by a signal that comes to the input of the record of the register of modes 18 from the input-output device. - The data from debug memory block 9 can be transferred through the L data register to the I / O device and from it, for example, to a computer for analysis and control. The address from the register 4 address output can also be transmitted through the I / O device to an external Wednesday In addition, the address can be displayed in the display unit 5.

Various debugging modes are possible. In the mode of continuous execution of the MPS program, the signal from the MPS to the input of the record of register 4 of address 5 receives the address on its information input, and from its output it goes to the address input of block 9 of debugging memory. The control signal from MPS is fed to the input of the element OR 23, from the output of which the reading signal is fed to the input of block 9 of the debugging memory. After a delay in the read time carried out by the delay unit 25, the data on the signal from the output of the delay unit 25 is entered into data register 2. The delay unit 24 performs a time delay for the data readiness signal to be output at the time data is written to the data register 2. From the output of data register 2, the data is transmitted to the IPM via a control signal received by the IPM from the output of the element OR 22. If this data is a command, then it is executed by the IPN processor. The control signal from the output of the element OR 22 is outputted, taking into account the state of the register of 18 modes. With a positive level of the input signal of the element And 21, the second input of this element also receives a positive level signal from the output of the delay block 24. At the same time, from the output of the AND 21 element, a signal is fed to the input of the OR 22 element. the signal at the output of the element OR 22 is formed when a signal is received from the output of the decoder 19 commands to the input of the element. OR 22. The signal at the output of the decoder 19 commands is formed when the corresponding code arrives at its input from the input / output device present on the input feature Koman

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decoder d 19 commands from an I / O device. Thus, the stepping mode-debug control is performed by the operator using an input device.

During continuous execution of the MPS program, the device analyzes the addresses of the executed commands and information, which is a command or operand, or the contents of the status register. This information is compared in blocks 6 and 10 respectively with the contents of the stop address register 12 and the register 1 1 danh. When coinciding with the outputs of blocks 6 or 10, the inputs of the register 18 of the modes receive signals that put the device in debug mode along the slots. Information in registers 11, 12 is recorded from their information inputs from an input / output device when control signals are written to their inputs.

When executing the MPS program, the intermediate results of the calculations, to check the correctness of the execution of the MPS program, can be entered into the data register 7 from the MPS (according to the recording signal), the contents of which are fed to the display unit 8. Indications can be enabled or disabled by the signal received at the input of block 8.

Claims (2)

Invention Formula 1. A device for debugging programs containing a control unit, a first data register, an address register, an address indication block, an address comparison block, a debug memory block, a stop address register, and a first data indication block, the first information input of the device connected to the first information input the first data register and the information input of the stop address register; the second information input of the device is connected to the second information input of the data register; the information output of the debugging memory block en with the third in-. first entry register entry data, the output of which is connected to the information input of the first display unit, with the first information input of the debugging unit, with the first input of the data comparison unit and is the first information output of the device, the first address input of the device is connected to the first information input of the address register, the second address input of the device is connected to the second information input of the address register, the first input of the device address sign is connected to the input of the address register, the first output of which is connected to information the input of the indication1D1I address block, with the first input of the address comparison block and is the address output of the device, the second information output of the address register is connected to the address the input of the debug memory block, the output of the stop address register is connected to the second input of the address comparison block, characterized by TeMj that in order to expand the functionality of the device by providing debugging of programs in real conditions, the second register of the danns, the second data indication block are entered into the device , data block, buffer register, high-order address decoder, four AND-NOT elements, the outputs of the high-order address register are connected to the high-order decoder inputs, addresses, first, second The third and fourth outputs of which are connected to the first inputs of the first, second, third, and fourth elements of the NAND, respectively, the outputs of which are connected respectively to the first, second, third, and quarter inputs of the block: debug memory, first second, third, fourth, fifth, sixth,; seventh, eighth, nine, tenth, I-eleven, twelve, and trinad-I-th outputs of the control block connect: unnumbered respectively to the first input of the first register data register, to the first input of the register entry address to the record entry block and the debug memory, with the output of the device write attribute, with the input of the write attribute of the second data register, with the input of the write attribute of the stop address register, with the read input of the debugging memory unit, with the second write input of the first data register, with the display enable input of the first display unit data, with an input of permission of indication of the second block about Q five five five data indication, with the resolution enable input of the address indication unit, with the third recording input of the first data register and the second recording output of the device, the output of the access control polling of the control unit is connected to the second inputs of the first, second, third and fourth elements AND-NOT, the first information input of the device with the information input of the control unit and the information input of the second data register, the outputs of the equality of the address and data comparison blocks are connected respectively to the first and second mode inputs of the block control, the device mode feature input is connected to the control unit mode record input, the device access input is connected to the first control unit input, the device data sign input is connected to the buffer register record input, the third device information input is connected to the buffer register information input ,, output which is connected to the information input of the second display unit 5, the second input of the address feature is connected to the second input of the register of the address register and the first input of the control unit, the input of the coma feature The device is connected to the polling input of the instruction decoder, 2. The device according to n.lj, of t. L. - that the control block contains a mode register, the first and second elements are AND, the first and second elements are OR, the first and second delay blocks and the decoder of commands, the first and second modes - Hbje inputs of the control unit are connected to the corresponding installation inputs of the mode register, the input of the mode record flag is connected to the record input of the mode register, the first, second, third, fourth, fifth, sixth, seventh and eighth outputs of the command decoder are connected to the first, second. third, fourth, fifth, and The third output of the block of the grab is with the first inputs of the first and second element of the 1PI, the output of which is the seventh output of the block and through the first element for the core connected to the eighth output of the block and to the input of the second delay element, first, second, third, fourth, fifth and the sixth information outputs register7 14256878 The pa modes are respectively the OR element and the first AND element, the ninth, tenth, eleventh you are the output of the first element And is control unit strokes and connected to the twelfth block output, output with the output of the polling treatment block the second delay element is connected control, with the first inputs corresponding to the second input of the second element And The first and second elective outlet of which is connected to the second cops And, the first and second input of the first element And, the output the control unit is connected to the second one, which is the thirteenth output inputs, respectively, of the second IQ unit stroke.