JPH0652013A - Tracing circuit - Google Patents

Abstract

PURPOSE:To prevent the lack of trace data (history of execution of emulation) at the time of storing executing history generated in the case the minimum instruction cycle of a microcomputer is shorter than the write cycle time of a trace memory used for the tracing circuit. CONSTITUTION:A trace memory is provided with two systems 21, 22 and in these two trace memories 21, 22, trace data TD are stored alternately. In such a manner, even to the microcomputer minimum instruction cycle of the time of about a half of a write cycle of the trace memories 21, 22, data lack of the trace data is eliminated and the trace data can all be stored.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a trace circuit for obtaining trace data which is an emulation execution history in an in-circuit emulator which is a development support tool for one-chip microcomputers.

[0002]

2. Description of the Related Art Conventionally, debugging and the like have been performed using an in-circuit emulator which is a development support tool for a one-chip microcomputer or the like. Emulation means that one microcomputer pseudo-executes the instruction system of another microcomputer by hardware or firmware by a microprogram. A software or hardware device that performs such emulation is called an emulator. The emulator has an advantage of high processing speed because it has an instruction (instruction) interpretation processing function in hardware. Conventionally,
A trace circuit in an in-circuit emulator such as a one-chip microcomputer is equipped with a readable / writable trace memory for storing a history (trace data) of emulation execution of the one-chip microcomputer, and stores a history of a program counter and various registers. is doing. Then, the data stored in the trace memory is executed by a central processing unit (hereinafter, referred to as CPU) to debug the program to be developed.

[0003]

However, in the trace circuit having the above configuration, the upper limit of the operation speed of the trace circuit is determined by the write cycle time (write cycle time) of the trace memory used, and the higher speed than that is required. It could not be used as a trace circuit for a one-chip microcomputer with a minimum instruction cycle. In other words, if the minimum instruction cycle of the one-chip microcomputer becomes shorter than the write cycle time of the trace memory, it is not possible to take a sufficient write time when storing the history of the program counter and various registers. The data stored in the trace memory will be lost. SUMMARY OF THE INVENTION The present invention has a problem that the trace data at the time of storing the execution history generated when the minimum instruction cycle of the microcomputer is shorter than the write cycle time of the trace memory used in the trace circuit. It provides a trace circuit in an in-circuit emulator that solves the problem of missing.

[0004]

In order to solve the above-mentioned problems, the present invention provides a read / write for storing the trace data in a trace circuit which takes trace data as a history of emulation execution in an in-circuit emulator for a microcomputer. There are provided possible first and second trace memories, and write control means for alternately storing the trace data in the first and second trace memories at a predetermined timing.

[0005]

According to the present invention, since the trace circuit in the in-circuit emulator is configured as described above, the write control means can operate even if the minimum instruction cycle of the microcomputer becomes shorter than the write cycle time of the trace memory. , Trace data to be supplied first and second
Are alternately stored in the trace memory at a predetermined timing. As a result, the trace data such as the program counter and various registers can be accurately stored even in the high speed microcomputer having the minimum instruction cycle. Therefore, the above problem can be solved.

[0006]

FIG. 1 is a block diagram of a trace circuit showing an embodiment of the present invention. This trace circuit is, for example, a circuit provided in an in-circuit emulator for a one-chip microcomputer, has a latch circuit 11 that captures and holds trace data TD by a trace latch signal LH, and the latch circuit is provided on the latch output S11 side. 12 and 13 are connected. The latch circuit 12 is a circuit that captures and holds the latch output S11 at the rising edge of the trace pointer TP0, for example. The latch circuit 13 outputs a signal obtained by inverting the rising edge of the trace pointer TP0 by the inverter 32 (that is, the trace pointer T
It is a circuit that captures and holds the latch output S11 at the fall of P0). The first and second trace memories 21 and 22 are connected to the latch outputs S12 and S13 of the latch circuits 12 and 13, respectively, and the first and second trace memories 21 and 22 are respectively connected to the trace pointers TP1 to TP1.
Write control is performed by the TPN, TP1a to TPNa, the trace pointer control unit 31, and the memory write control unit 33.

The first trace memory 21 has a data input terminal DATA for inputting a latch output S12, a write signal input terminal WR / for inputting a write signal WR1 /, and an address input terminal for inputting signals of the trace pointers TP1 to TPN. Has ADDRESS. The first address memory 21 enters the write mode in response to the input of the write signal WR1 /, and the trace pointers TP1 to T
It has a function of storing the latch output S12 in the area designated by PN. The second trace memory 22 has a data input terminal DATA for inputting a latch output S13 and a write signal input terminal WR / for inputting a write signal WR2 /.
And an address input terminal ADDRESS for inputting signals of the trace pointers TP1a to TPNa.
The second trace memory 22 has a write signal WR2 /
Is entered into the write mode, and the latch output S is placed in the area designated by the trace pointers TP1a to TPNa.
It has a function of storing 13.

The trace pointer control unit 31 specifies the trace pointers TP0, TP1 to TPN and TP1a to T for designating the addresses of the first and second trace memories 21 and 22.
It has a function of controlling PNa and holding the output of each of the trace pointers TP0, TP1 to TPN, and TP1a to TPNa while the latch outputs S12 and S13 are output from the latch circuits 12 and 13. Memory write control unit 3
3 are trace pointers TP1 to TP1 based on the basic signal S.
It has a function of alternately outputting the write signals WR1 / and WR2 // when TPN and TP1a to TPNa are odd and even, and supplying them to the first and second trace memories 21 and 22.

The trace circuit of FIG. 1 is also provided with a reading means, but it is not shown because it is not directly related to this embodiment. FIG. 2 shows the trace memory 21 of FIG.
22 is a time chart showing how the trace data TD is stored in 22. The operation of FIG. 1 will be described with reference to this figure.

First, the trace data TD is transferred to the latch circuit 1.
When it is supplied to 1, the trace data TD is latched in the latch circuit 11 when the trace latch signal LH rises. The latch output S11 of the latch circuit 11 is
Latch circuit 12 at the rising edge of trace pointer TP0
And the latch output S12 is sent to the data input terminal DATA of the first trace memory 21. First
In the trace memory 21, the write mode is set by the write signal WR1 / supplied from the memory write control unit 33, and the latch output S12 is stored in the storage area designated by the trace pointers TP1 to TPN. Next, the changed trace data TD is latched in the latch circuit 11 at the rising edge of the trace latch signal LH. The latch output S11 has the signal of the trace pointer TP0 inverted by the inverter 32, and is latched by the latch circuit 13 by the inverted signal (that is, the trailing edge of the trace pointer TP0). The latch output S13 has the latch output S13 of the second trace memory 22.
Sent to. In the second trace memory 22, the write mode is set by the write signal WR2 / from the memory write control unit 33, and the trace pointers TP1a to TPNa.
The latch output S13 is stored in the storage area designated by.

As described above, in this embodiment, when the trace pointers TP1 to TPN and TP1a to TPNa are odd and even, the memory write controller 33 alternately outputs the write signals WR1 / and WR2 /. The input trace data TD is alternately stored in the first and second trace memories 21 and 22 via the latch circuits 11, 12 and 13. Therefore, even with respect to the one-chip microcomputer having the minimum instruction cycle of about half the write cycle of the trace memories 21 and 22, the trace data TD is not lost and all of the trace memory 2 is lost.
1, 22 can be stored. Therefore, the speed of the trace circuit can be increased.

The present invention is not limited to the above embodiment,
For example, the write control means composed of the latch circuits 1, 12, 13 and the trace pointer control unit 31 and the memory write control unit 33 may be changed to another functional block, or the above embodiment may be other than a one-chip microcomputer. Various modifications are possible, such as application to a microcomputer.

[0013]

As described in detail above, according to the present invention, two trace memories for storing trace data are provided, and the trace data are alternately stored in the first and second trace memories. Thus, even for a microcomputer having a minimum instruction cycle that is about half the write cycle of the trace memory, all the trace data can be stored in the first and second trace memories without data loss. . Therefore, speedup of the trace circuit can be expected.

[Brief description of drawings]

FIG. 1 is a configuration block diagram of a trace circuit showing an embodiment of the present invention.

FIG. 2 is a time chart showing the operation of FIG.

[Explanation of symbols]

11, 12, 13 Latch circuits 21, 22 First and second trace memories 31 Trace pointer control unit 33 Memory write control unit

Claims (1)

[Claims] 1. A trace circuit for obtaining trace data, which is a history of emulation execution in an in-circuit emulator for a microcomputer, comprising: a readable and writable first and second trace memories for storing the trace data; A trace circuit, comprising: write control means for alternately storing in the first and second trace memories at a predetermined timing.