JPS6227832A - Address area discriminator for computer program - Google Patents

Abstract

PURPOSE:To designate an address area with the full bit length by providing a storage means containing the memory areas corresponding to each address of a computer program and a write/read means. CONSTITUTION:The data showing the designated address areas 1, 2... are delivered from a terminal 4 and given to a microprocessor 5. The processor 5 analyzes the data and delivers the data DT of different contents for each area, e.g., '1' for the data 1. This data DT is given to the data input DIN of a memory 7. At the same time, the processor 5 delivers the address designating signal AD for designation of memory areas of a memory 7 in response to the addresses 0010-0015 and A000-A017 of the area 1 when '1' is delivered as the data DT. Thus, the signal AD corresponding to the contents of each data DT is delivered and given to the input B of a selector 8. At the same time, the control signal is applied to the control input CS of the selector 8 for selection of the input B.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention provides an apparatus for identifying whether each passing address of an executed computer program belongs to a specified specific address area. Regarding.

[Conventional technology]

When tracing a computer program (ie, recording a passing display), it is common to trace only a designated specific address area, rather than tracing all addresses of the program. Conventional trace devices are equipped with a microcombinator that specifies an arbitrary address area using input from a terminal, and also compares address information of the program being executed with addresses within the address area specified by the microcomputer. A comparison circuit is provided to perform the comparison, and as a result of the comparison,
By targeting only transit addresses identified as belonging to the specified address area as targets for tracing, tracing can be performed only for the specified address area.

[Problem that the invention seeks to solve]

However, in such a system, each time one address area is designated, a comparison circuit must be provided to compare the address in the area with passing address information. That is, it is necessary to provide a number of comparison circuits proportional to the designated number of address areas. Therefore, in order to increase the number of specified address areas, the number of logic circuit configurations increases, and on the other hand, when the number of logic circuit configurations is decreased, only a small number of address areas can be specified. .

Furthermore, when using such a method, the number of logic circuits is reduced, rather than comparing the passing address information with addresses within the designated address area on all address bus lines of the microcomputer. Therefore, it is common practice to compare the two only on address bus lines corresponding to a predetermined number of upper bits. −
For example, in a microcombiator with n address bus lines, the upper 10 bits of the address
Comparison is performed only on the bus lines, and differences in the signal contents of the lower 13 bits of the address bus lines are ignored. Therefore, in this method, it is not possible to specify the address area within the range corresponding to the lower bits that are not compared, so there is a problem that it is impossible to specify the address area with the full bit length. Ta.

This invention was made in order to solve each of the above-mentioned problems.

[Means for solving problems]

The address area identification device according to the present invention includes a storage means having a storage location corresponding to each address of a computer program, and an address area in which a storage location corresponding to an arbitrary address in the storage means indicates the address area to which the address belongs. The present invention is characterized by comprising a writing means for writing designated data, and a reading means for reading out the address area designated data from a storage location in the storage means corresponding to each passing address of the executed program.

[Effect]

The writing means writes address area designation data corresponding to a desired address. The written data is read out in correspondence with the address (passing address) executed by the computer program. Therefore, it is possible to immediately identify which address area the execution address (passing address) belongs to based on the readout output. Furthermore, by changing the content of the address area designation data written in the storage means, any address area can be set.

Data of arbitrary content can be written into the storage location corresponding to the individual address in the storage means, depending on the word length. Therefore, there are multiple numbers of address areas that can be expressed by this data depending on the word length. Therefore,
A relatively small-scale configuration makes it possible to specify a large number of address areas. Furthermore, since the storage location of the storage means corresponds to each address of the program, it is possible to specify the address area using the entire bit length.

Therefore, for example, if this address area identification device is used when tracing a program, a large number of address areas to be traced can be specified with a small amount of logic, and moreover, it can be specified using the total bit length. You will be able to do this.

[Embodiment] Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a block diagram showing an embodiment of an address area identification device according to the present invention. This address area identification device 1
is used to specify an address area to be traced when the tracing device 3 traces a computer program executed in the computer system 2.

In the identification device 1, the terminal 4 is used by the operator to arbitrarily set an address area for tracing. Data indicating the set address area is given from the terminal 4 to the microprocessor 5. microprocessor 5
Based on the data given from the terminal 4, outputs address area designation data DT consisting of a binary coded signal indicating the address area. This data DT output by the microprocessor 5 is applied to the data input DIN of the memory 7 via the buffer 6. The memory 7 stores each computer program to be traced.

It has storage locations that correspond one-to-one to addresses, and has a configuration of 64K x 4 bits, for example.

In response to the output of the address area designation data DT, the microprocessor 5 also sends an address designation signal AD to the two inputs A and B of the selector 8, which indicates each address belonging to the address region designated by this data DT. A signal that is applied to the input B of the selector 8 and controls the selection of the selector 8 is applied to the control human power CS of the selector 8. Which individual address belongs to which address area can be arbitrarily set by the terminal 4.

From the computer system 2, passing address information UAD indicating the passing address of the program being executed is sent to the tracing device 3.
and given to the identification device 1. In the identification device 1, this address information UAD is latched in a flip-flop 9, and the output of the flip-flop 9 is sent to the selector 8.
is given to input A of The output of this selector 8 is given to the address input AD of the memory 7.

The stored data output from the data output DOUT of the memory 7 is latched into the flip-flop 11 via the buffer 10. The output of flip-flop 11 is provided to decoder 12. The decoder 12 decodes the applied data and outputs a designation signal SIG according to its contents. This designation signal SIG is given to the trace device 3.

Furthermore, the computer system 2 also sends transit address information UA.
A clock signal CL synchronized with D is given to the identification device 1, and in the identification device 1, this clock signal CL is applied to the control human power C of the flip-flop 9 and the control system 1.
given to 3. The control system 16 outputs a timing signal T based on this clock signal CL or a signal from the microprocessor 5, and applies the signal T to the control input R/W of the memory 7 and the control input C of the flip-flop 11. The latch timing of the flip-flop 9 is controlled by this clock signal CL, and the latch timing of the flip-flop 9 is controlled by the clock signal CL.
The read/write timing of the flip-flop 11 and the latch timing of the flip-flop 11 are controlled by this timing signal T.

An example of the operation of this identification device 1 will be explained as follows.

Using the terminal 4, the program to be traced has multiple address areas (1), (2) as shown in Figure 2.
), (3), (4), (5), etc. are specified by the operator. At this time, from the terminal 4, each specified address area (1), (2), (3), (4
), (5)... are output and given to the microprocessor 5.

The microprocessor 5 analyzes this data and divides the area (1
) for example ``1'', for example ``2'' for area (2), and so on, outputting data DT with different contents corresponding to each area, and inputting the data DIN of the memory 7.
give to

Furthermore, the microprocessor 5 sets "1" as the data DT.
When outputting, each address 001 belonging to area (1)
Address designation signal AD is output to specify the storage location of memory 7 corresponding to destination 015, A000 to A017, and on the other hand, when outputting "2" as data DT, area (2) is output.
outputting an addressing signal AD specifying a storage location in the memory 7 corresponding to address 0027 of the data DT, outputting an addressing signal AD corresponding to each content of the data DT and applying it to the input B of the selector 8; A control signal for selecting the input B is given to the human control CS of the selector 8.

Thereby, the selector 8 selects this address designation signal AD and applies it to the address input AD of the memory 7.

As a result, in the memory 7, each area (
1, (2), (3), (4), (5)...
- Data DT is written to the corresponding storage location.

When this writing is completed, the microprocessor 5 sends a control signal for selecting the input A to the control input C8 of the selector 8.
give to Also, the memory 7 is set to read mode.

After that, when execution of the program in the computer system 2 is started, the address information UAD and the clock signal CL
is given to the identification device 1. After the address information UAD is latched into the flip-flop 9, the input A of the selector 8
, is selected by the selector 8, and is applied to the address input AD of the memory 7. As a result, address information UAD is sent from memory 7 to address 0 as a passing address.
010, “1” (see Figure 3);
On the other hand, if it indicates address 0020, "0"
(See the figure), the data stored in the storage location corresponding to the transit address indicated by the address information UAD is sequentially read out. The read storage data P is latched by a flip-flop 11 and then applied to a decoder 12.

The decoder 12 decodes the read address area designation data DT and provides the decoded output to the trace device 3 as an address area designation signal SIG.

The trace device 3 records the transit address of the program based on the address information UAD given from the computer system 2, but at this time, the designation given from the identification device 1 corresponding to the address information UAD indicating the same transit address is recorded. Using the signal SIG, it is determined whether or not each passing address belongs to the address area to be traced, and only the passing addresses belonging to the address area are recorded (however this is determined is not clear). (This is a design matter and will not be explained here.) This allows the program to be traced only for the specified address area.

In this way, by using this identification device 1, it is possible to designate a large number of address areas to be traced according to the word length of the memory 7, and moreover, it becomes possible to designate them in terms of total bit length. In addition, the area shown in Figure 2 (1
As shown in the month, it is possible to specify multiple areas within the same address area.

In this practical example, the identification device 1 is used to specify the address area to be traced, but it can also be used in other appropriate fields where it is necessary to identify whether or not a passing address belongs to the specified address area. This identification device 1 may be used in the following.

〔Effect of the invention〕

As described above, according to the address area identification device for a computer program according to the present invention, it is possible to specify a large number of address areas with a small amount of logical objects, and moreover, it is possible to specify an address area with a total bit length. It has excellent effects.

In addition, by using high-speed access memory as a storage means and executing each process by a microprocessor,
It becomes possible to quickly and efficiently identify whether each passing address of a program belongs to a designated address area.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of an address area identification device according to the present invention, FIG. 2 is a diagram showing an example of an address area designated using the terminal in FIG. 1, and FIG. 2 is a diagram showing an example of address area designation data written in the memory of FIG. 1 corresponding to each designated address area in the figure; FIG. DESCRIPTION OF SYMBOLS 1...Address area identification device, 2...Computer system, 3...Trace device, 4...Terminal, 5...Microprocessor, 6,10
...Buffer, 7...Memory, 8...Selector,
9.11...Flip-flop, 12...Decoder, 13...Control system.

Claims (1)

[Scope of Claims] 1. Storage means having a storage location corresponding to each address of a computer program, and address area designation data indicating the address area to which the address belongs to a storage location corresponding to an arbitrary address in the storage means. address area identification for a computer program, comprising: writing means for writing the address area designation data; and reading means for reading out the address area designation data from a storage location in the storage means corresponding to each passing address of the executed program. Device. 2. The data written by the writing means is data for specifying an address area to be traced from among all addresses of a computer program, and the address area identification device is used when tracing a computer program. 2. An address area identification device for a computer program according to claim 1, wherein 3. Claim 1, wherein the storage means, writing means, and reading means are included in a microcomputer.
An address area identification device for a computer program according to item 1 or 2.