JPH0830484A - Trace circuit - Google Patents

Abstract

PURPOSE:To obtain a trace circuit which records the logical state of a specific device each time the device is accessed by providing a trigger signal generating means, an address generating means, and a storage means. CONSTITUTION:The address generating means 22 increases address data ADw as a trigger signal St is inputted and supplies the data to the input-side address terminal group AD of the storage means 23. Therefore, the trigger signal St is supplied to the write terminal WR of the storage means 23 and the address data ADw are supplied to the address terminal group AD of the storage means 23, so that the logical states of an address bus AB and a data bus DB connected to the input-side data terminal group DA of the storage means 23 are written as write data Dw in the storage means 23. Thus, the logical state of the specific device can be recorded each time the device is accessed, which is therefore effective to the specific device at the time of debugging operation wherein trouble occurs very rarely.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a trace circuit for storing a logic state of a device.

[0002]

2. Description of the Related Art In a device equipped with a CPU or the like, when debugging software or hardware, a so-called trace for recording and analyzing the logical state of each device is required. Conventionally, a logic analyzer is used for tracing.

[0003]

Such a logic analyzer records the logical state within a predetermined time in the storage means and analyzes or displays the logical state. However, it is unsuitable for the purpose of recording and analyzing the logical state of a specific device each time an access to the device occurs, because the storage capacity is insufficient and the measurement conditions are limited. The present invention has been made under such circumstances, and an object thereof is to provide a trace circuit for recording the logical state of a specific device each time an access to the device occurs.

[0004]

The trace circuit of the present invention comprises a trigger signal generating means for generating a trigger signal from an access signal given to a device, and an address for changing address data by a unit amount each time the trigger signal is inputted. It is characterized in that it has a generating means and a storage means for storing the logical state of the device in accordance with the address data by using the trigger signal as a write signal. The logical state of the device means the logical state of each terminal of the device, that is, a data terminal, an address terminal, a read terminal,
It includes the logical states of the write terminal and all other control terminals.

[0005]

The trigger signal generating means generates a trigger signal from the access signal given to the device. The address generation means changes the address data by a unit amount each time the trigger signal is input. The storage means stores the logical state of the device according to the address data, using the trigger signal as a write signal. As a result, each time the device to be traced is accessed, its logical state can be stored in the storage means.

[0006]

Next, the present invention will be described with reference to the drawings. 1 is a schematic circuit diagram showing an embodiment of a trace circuit of the present invention, and FIG. 2 is a timing chart corresponding to FIG.

Reference numeral 10 is a circuit under test having a device to be traced. In the present specification, what is to be traced, that is, a device, a circuit, an element, and the like are referred to as a device. The circuit under test 10 is the CPU 1
1, a decoder 12, a memory element 13, an I / O controller 14 and the like. AB is an address bus and DB is a data bus. Further, RD is a read signal that controls reading from each element, and WR is a write signal that controls writing from each element.

The decoder 12 decodes the address data on the address bus AB to select signals CS1, CS2.
, CSn are generated and given to the memory element 13 and the I / O controller 14 under the control of the CPU 11. The memory device 13 and the I / O controller 14 use the address bus A
It is a device to be traced, which exchanges data with the CPU 11 via B and the data bus DB.

Reference numeral 20 is a trace circuit, which is a trigger signal generating means 21, an address generating means 22, and a storage means 2.
Three. The trigger signal generation means 21 generates a trigger signal St from an access signal supplied to the memory element 13 which is a device, that is, a selection signal CS1, a read signal RD, and a write signal WR. The trigger signal generating means 21 is, as illustrated in FIG. 1, a read signal RD.
And a negative logic OR gate 21 for inputting the write signal WR
A and an AND gate 21B of negative logic for inputting the output thereof and the selection signal CS1. Therefore, the trigger signal St is generated when the selection signal CS1 of the memory element 13 that is the device is valid and the read signal RD or the write signal WR is valid.

The address generating means 22 is composed of, for example, a binary counter element, and has a clear terminal CLR.
Is reset when is enabled and the trigger signal St
Output Q is incremented each time is input to the address terminal AD of the storage means 23 as address data ADw.

The storage means 23 is constructed by connecting one or more dual port memories in parallel. On the input side of the storage means 23, there are provided an address terminal group AD for inputting the address data ADw from the address generation means 22, a write terminal WR for inputting the trigger signal St, and a selection signal CSw for activating the operation on the input side. A selection terminal CS for inputting is provided. On the other hand, on the output side of the storage means 23, an address terminal group AD for inputting an address ADr at the time of reading, a data terminal group RD for read data RDr, and a selection signal CSr for activating the operation on the output side. A selection terminal CS for inputting is provided.

In the data terminal group DA on the input side of the storage means 23, the above-mentioned address bus AB and data bus D are provided.
B, the read signal RD, and the write signal WR are connected to write data indicating their logical states (hereinafter, may be collectively referred to as write data Dw), and the written data is , Read data Dr is read from the data terminal group DA on the output side.

The trace circuit 20 is connected to an analyzing means 30 which will be described in detail later, and an address generating means 22.
The clear signal CLR for clearing, the selection signals CSw and CSr to the storage means 23, and the read signal RDr are supplied from the analysis means 30 to the trace circuit 20, and the data read from the storage means 23 is also the above. The data is output to the analysis means 30.

Next, the operation for tracing the logic state of the memory element 13 of FIG. 1 will be described with reference to FIG. As shown in FIG. 2, if the selection signal CS1 for selecting the memory element 13 is in the valid state at the time point t1, and then the write signal WR is in the valid state for the period from the time point t2 to the time point t3, the trigger signal generating means 21. Generates a trigger signal St from the selection signal CS1 and the write signal WR, and supplies the trigger signal St to the address generation means 22 and the storage means 23.

The address generating means 22 has a trigger signal St.
The address data ADw is incremented in accordance with the input of and is given to the input side address terminal group AD of the storage means 23. Therefore, the trigger signal St is stored in the write terminal WR of the storage means 23, and the address data ADw is stored in the storage means 2
By being respectively input to the address terminal group AD of No. 3, the logical state in the address bus AB and the data bus DB connected to the input side data terminal group DA of the storage means 23 is written in the storage means 23 as the write data Dw. Be done.

That is, the memory element 13 which is a device
The logical state (the state of the address bus and the data bus) at the time of access to is written in the storage means 23. Each time an access occurs, the logical state is written in the storage means 23 in the order of the addresses generated by the address generation means 22, as described above. Thus, only the logical state at the time when the device is accessed is sequentially stored in the storage means 23. In other words, since no data is written in the storage means 23 unless it is accessed, many logical states can be stored.

After the trace operation for the required period is completed,
Various control signals are given from the analyzing means 30 and necessary data are read out to the analyzing means 30. That is,
The selection signal CSr in the valid state is given to the selection terminal CS on the output side of the storage means 23, the read signal RDr in the valid state is given to the read terminal RD, and the address data ADr to be given to the address terminal AD is to be read. Is incremented in accordance with the above, the logical state of the device is read from the data terminal DA on the output side to the analysis means 30 and analyzed.

In FIG. 2, the write signal W given to the device is
Although only R is shown, it goes without saying that the trace operation is similarly performed with the read signal RD.

When the I / O controller 14 is a device to be traced, the trigger signal generating circuit 21 of the trace circuit 20 outputs the corresponding selection signal CS2.
You can connect it to Further, the device is not limited to the memory element and the I / O controller shown in the present embodiment, and any device that can be accessed by the CPU 11 may be used. In that case, the selection signal of the device is a trigger signal. It may be given to the generation circuit 21.

A personal computer or the like can be used as the analysis means 30 connected to the trace circuit 20. If the trace circuit 20 is constructed so that it can be connected and stored in the expansion slot of the personal computer, it is easy to exchange control signals and data between the analyzing means 30 and the trace circuit 20. As a result, the analysis unit 30 can read the logic state of the device recorded in the storage unit 23 of the trace circuit 20, create a list in which the terminals and logic states of the device are arranged in time series, and analyze the list. Is. That is, the analysis unit 30 and the trace circuit 20
The trace device can be configured by.

Although a readable / writable memory such as a RAM can be used as the storage means 23, unlike the dual port memory, since there is only one set of data bus and address bus, bus arbitration is performed. A circuit or the like is required and the circuit configuration becomes complicated.

The connection between the trace circuit 20 and the device is
A clip terminal (probe) similar to that used in a logic analyzer or the like may be used.

Further, the trigger signal generating means 21 can be realized by those skilled in the art by an arbitrary logic circuit, and is not limited to this embodiment.

As described above, in the trace circuit 20 of this embodiment, the logical state of the specific device is written in the storage means 23 only when the specific device is accessed, and the logical states of the other devices are Since it is not written, relatively many logical states can be stored for the required device. Therefore, it is particularly effective for debugging work in the case where a failure occurs in a specific device in a very rare case.

In this embodiment, the logical states written in the storage means 23 are the data bus DB, the address bus AB,
Although the read signal RD and the write signal WR are used, the trace circuit of the present invention is not limited to this.
The logic states written in the storage means include various control signals and the like in addition to the above.

[0026]

As described above in detail, according to the trace circuit of the present invention, the logical state of a specific device can be recorded each time an access to the device occurs, so that the trace state of the specific device can be very small. This is especially useful for debugging when a problem occurs in rare cases.

[Brief description of drawings]

FIG. 1 is a schematic circuit diagram showing an embodiment of a trace circuit of the present invention.

FIG. 2 is a time chart of the same embodiment.

[Explanation of symbols]

 13 memory device (device) 14 I / O controller (device) 21 trigger signal generation means 22 address generation means 23 storage means 30 analysis means 30 ADw address data St trigger signal

Claims (1)

[Claims] 1. A trigger signal generating means for generating a trigger signal from an access signal given to a device, an address generating means for changing address data by a unit amount each time the trigger signal is input, and a write signal for the trigger signal. And a storage unit that stores the logical state of the device according to the address data.