JPH0218647A - Cache memory test method - Google Patents

Abstract

PURPOSE:To test plural cache memories in parallel with each other by reading and writing the data of all '1' and all '0' into and out of the cache memories and referring to the outputs of a cache memory comparator, an AND circuit and an OR circuit respectively. CONSTITUTION:In the 1st stop of a test, a cache memory comparator 12 checks the data having all bits set at '1' on a cache tag part 8. An AND circuit 14 checks the data having all bits set at '0' on a cache data part 10. In the 2nd step of the test, a comparator 12 checks the data having all bits set at '0' on the part 8. While an OR circuit 16 checks the data having all bits set at '0' on the part 10. Thus it is possible to check whether a cache memory is normal or not just by reference to both circuits 14 and 16 as well as the comparator 12. In such a way, plural cache memories can be tested in parallel with each other.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a method for testing character cache memory used in a computer system.

Cache memory used in conventional technical computer systems is intended to improve system performance by storing frequently used data in a small amount of high-speed memory. A cache address register 102 that stores the address data shown in FIG. 3, a cache data section 108 and a cache tag section 110 that are composed of a random access memory that receives the mote signal and accesses the first part 104 of the cache address register as an input. and,
In a conventional test of a cache memory comprising a comparator 112 that compares data from the second portion 106 of the cache address register and the cache tag portion 110, an external testing device, e.g. Write data to all words in the cache tag section, then sequentially give addresses corresponding to all words in the cache memory, read out all bits of the word from the cache data section and the cache tag section, and write data to all words in the cache memory. Checks word memory cells. Here, 114 is a signal line indicating a comparison result between the second portion 106 of the cache address register and the data from the cache tag section 110;
6 is a data line from the cache tag section, and 118 is a data line from the cache data section.

Problems to be Solved by the Invention In testing a cache memory in the prior art, an external testing device, such as a tester, reads out all bits of a word to the outside and performs a check. For this reason, there is a problem that the tester can only test a limited number of cache memories at one time since there are many bits to be checked per word.

The present invention aims to test multiple cache memories in parallel by adding a small amount of hardware to the cache memories.

Means for Solving the Problems The present invention provides a mode signal indicating a write mode and a read mode, a cache address register storing address data, and a cache address register that receives the mode signal and is accessed using a first portion of the cache address register as an input. a cache data section and a cache tag section consisting of a random access memory; a cache comparator for comparing data from the second portion of the cache address register and the cache tag section; AND for the bits of
A circuit and an OR circuit that performs an OR operation on all bits of data from the cache data section are provided, and as a first step, addresses corresponding to all words of the cache memory are stored in the first part of the cache address register in write mode. The second part of the cache address register is always given data of 1 for all bits, the cache data section is always given data of 1 for all bits, and the cache data Always 1 in the last word of the section and cache tag section
Then, in the read mode, the first part of the cache address register is given the addresses corresponding to all the words of the cache memory consecutively, and the second part of the cache address register is given the addresses corresponding to all the bits of the cache address register. Data of 1 is always given and data of all words are read from the cache data and the cache tag section, and the cache comparator compares the data from the cache tag section with the second part of the cache address register, and the AND circuit Now test the data from the cache data section and do this for every word of the cache memory, and as a second step test the data from the cache address register in write mode.
section is given consecutive addresses corresponding to all words of the cache memory, the second section of the cache address register is always given O data for all bits, and the cache data section is given consecutive addresses for all words of the cache memory. always write data of 1 to all words of the cache data section and the cache tag section, and then write data of 1 to all words of the cache memory in the first part of the cache address register in read mode. The addresses are continuously given, data of O is always given to all bits in the second part of the cache address register, data is read from the cache data section and the cache tag section, and the cache comparator reads the data from the cache data section and the cache tag section. A cache memory characterized in that data from the cache tag section is compared with a second portion of the cache address register, and the OR circuit tests the data from the cache data section for all words of the cache memory. The test method is that the cache comparator is the second of the cache address registers.
Compare the data from the cache tag part and the AND
The circuit ANDs all bits of data from the cache data portion, and the OR circuit ORs all bits of data from the cache data portion.

As the first stage of the test, the cache comparator checks for data in which all bits in the cache tag section are 1, and the AND circuit checks for data in which all bits in the cache data section are 1. In the second stage, the cache comparator checks the data in which all the bits in the cache tag part are O, and the OR circuit checks the data in which all the bits in the cache data part are O. vessel,
It is possible to determine whether the cache memory is normal simply by referring to the results of the AND circuit and the OR circuit.

Therefore, the external test device can test a plurality of cache memories.

The cache comparator is the second cache address register.
A cache data comparator compares data from the cache data section and data from the cache data register. In the first step of the test, an arbitrary pattern is applied to the cache memory, and in the second step, an inverse pattern of the previously applied arbitrary pattern is applied to the cache memory, and the comparison results of the cache comparator and cache data comparator are You can determine whether the cache memory is normal just by referencing it. Therefore, the external test device can test a plurality of cache memories.

Embodiment FIG. 1 is a diagram illustrating a method for testing a cache memory provided in a cache memory chip in a first embodiment of the present invention. In the first step of the cache memory test method of the present invention, a pattern of all 1s is written into the cache memory tag section 8 and the cache memory data section 10, and a test is performed to see if it can be read normally.

First, mode signal 2 is set to write mode.

Then, all 1 data is given to the second part 6 of the cache address register, all 1 data is given to the cache memory data section 10 through the data line 18, and O is given to the first part 4 of the cache address register. Data of all 1s is written to the cache memory tag section 8 and the cache memory data section 10 of the Oth word of the cache memory. Further, the first part 4 of the cache address register is changed continuously to write data of all 1's to the cache memory tag part 8 and the cache memory data part 10 of all words. next,
Set test mode signal 2 to read mode. All 1 data is given to the second part 6 of the cache address register, O is given to the first part 4 of the cache address register, and the cache memory tag part 8 and the cache memory data part 1 of the Oth word of the cache memory are given.
Data of 0 is read onto the data line 18. At this time, cache memory tag section 8 and cache memory data section 1
If memory cell 0 is normal, cache comparator 12
The data in the second portion 6 of the cache address register and the data read from the cache memory tag section 8 are compared, and a match is detected on the cache memory bit line 20. Further, the AND circuit 14 tests the data read from the cache memory data section 10, and its output 22 becomes 1. Therefore, cache memory bit line 20 from cache comparator 12 and AND circuit 1
Just by looking at the output from 4, it can be determined that all 1 data can be read and written to the cache memory.

In the second stage of the cache memory testing method of the present invention,
A pattern of all O's is written to the cache memory tag 8 and the cache memory data section 10, and a test is performed to see if it can be read normally. First, mode signal 2 is set to write mode. Then, all O data is given to the second part 6 of the cache address register, all O data is given to the cache memory data section 10 through the data line 18, and 0 is given to the first part 4 of the cache address register. All 0 data is written in the cache memory tag section 8 and the cache memory data section 10 of the 0th word of the cache memory. Furthermore, the first cache address register
The portion 4 is changed continuously to write all 0 data in the cache memory tag section 8 and the cache memory data section 10 of all words. Next, mode signal 2 is set to read mode. Second cache address register
Data of all O's is given to the part 6, O is given to the first part 4 of the cache address register, and the data of the cache memory tag part 8 and the cache memory data part 10 of the Oth word of the cache memory is read out. At this time, if the memory cells of the cache memory tag section 8 and the cache memory data section 10 are normal, the cache comparator 12 selects the second section 6 of the cache address register.
The data read from the cache memory tag unit 8 are compared, and a match is detected on the cache memory bit line 20.

Further, in the OR circuit 16, the cache memory data section 1
The data read from 0 is tested and its output 24
becomes 0. Therefore, by simply looking at the cache memory bit line from the cache comparator 12 and the output from the OR circuit 16, it can be determined that all 0 data can be read and written to the cache memory. That is, through the first and second stages shown above, the cache memory bit line 20. Output 2 of AND circuit 14
2 and the output 24 of the OR circuit 16 to test the cache memory.

For example, if the cache memory data section 10 is 32 bits, in the conventional cache memory testing method, the external test equipment must check the cache memory bit lines from the cache comparator and 32 data lines from the cache memory data section. It won't happen. However, in the cache memory test method according to the present invention, in the read test, the cache memory bit line 20. Output 22 of AND circuit 14 and O
You only need to look at the three outputs 24 of the R circuit 16, so if you use the same external test equipment, you will need 10 (3X10=30
) can be tested in parallel.

FIG. 2 shows a diagram illustrating a method for testing the cache memory 32 provided in the processor 30 in the second embodiment of the present invention. The second embodiment of the present invention has a cache memory 32 including a cache address register 34, a cache tag section 36, a cache data section 38, and a cache comparator 40 for comparing tag data, and further includes a cache data section and an external data section. A cache data comparator 42 is provided within the processor to compare data input from the bus. Below, the operation of the processor in its normal state and during testing will be explained.

In a normal state, the address generation unit 44 generates an address for accessing external memory.

The address 110 unit 46 and cache address register 34 receive this address. Cache memory 32
Now, the cache tag section 36 and the cache data section 38 are accessed using the first part 48 of the cache address register among the received addresses. Then, the second portion 50 of the cache address among the addresses received by the cache comparator 40 is compared with the data from the cache tag unit 36 . Finally, the control execution unit 52 receives the comparison result from the cache memory bit line 54.

If the comparison results in a match, the control execution unit 52 receives the data from the cache data unit 38 and processes it. If the comparison does not match, the external memory 56 is accessed and loaded into the data 2110 section 58. And in the cache memory 32, a first portion 48 of the cache address register
The cache tag part 36 of the word being accessed is rewritten with the data of the second part of the cache register, and the cache data part 38 of the same word is rewritten with the data 2110 part 5 of the same word.
Rewrite with the data of 8. At the same time, the control execution unit 52
Data 2110 receives data from section 58 and processes it.

There are two test states, and each stage has two steps: write mode and read mode.

In the first stage, the write mode is first input from the mode signal 60 which is an external terminal. Then, from the address bus 62 outside the processor 30, O is sent to the first part 48 of the cache address register, and "'1010..." is sent to the second part of the cache address register.
. . .10" checker plug pattern is given. Furthermore, the data bus 64 outside the processor 30 is provided with a checker plug pattern of "101".
Give a "checker plug" pattern of "1010...10" to the 0th word of the cache tag section 36 and cache data section 38.
Write the checker plug pattern. Further, the address bus 62 continuously changes the value of the second portion 50 of the cache address register to write a checker-plug pattern for every word of the cache memory 32. , input the read mode.Then, from the address bus external to the processor 30, O is input to the first part 48 of the cache address register, and "1010...10 is input to the second part of the cache address register.
Gives a checker plug pattern. Furthermore, on the data bus 64 outside the processor 30, "1010...
...Give a 10゛ checker plug pattern. Then, the read data in the cache tag section 36 is compared with the second section 50 of the cache address register by the cache comparator 40, and the read data in the cache data section 38 is compared with the cache data section 38 by the cache comparator 40. The comparator 42 compares the data input from the outside via the data 2110 section 58. Finally, cache comparator 4
The result of 0 is outputted to the outside of the processor 30 using the cache memory bit line 54, and the result of the cache data comparator 42 is outputted to the outside of the processor 30 using the cache memory valid line 66. Therefore, by simply looking at the outputs of the two external terminals, it can be determined that the above-mentioned pattern in the cache memory 30 can be read and written.

In the second stage of the test, a test is performed by giving the cache memory 30 an inverted pattern of the pattern given in the first stage. Therefore, by performing the first stage and the second stage, for the memory cells of the cache memory 30,
This means that 1 and O have been read and written. Therefore, the cache memory 30 can be tested by simply looking at the outputs of the two external terminals.

For example, if the cache memory data portion 38 is 32 bits, in the conventional cache memory testing method, the external test equipment checks the cache memory bit lines from the cache comparator and 32 data lines from the cache memory data portion. There must be. However, in the cache memory test method according to the present invention, in the read test, it is only necessary to look at the cache memory bit line 54 from the cache comparator 40 and the cache memory valid line 66 from the cache data comparator 42. Therefore, if the same external test equipment is used, 16 (2
x16=32) parallel testing becomes possible.

Effects of the Invention The cache memory is provided with a mode signal, an AND circuit and an OR circuit for the cache data section, and data of all 1 and all 0 is read and written to the cache memory, and the output of the comparator of the cache memory, the output of the AND circuit, and The cache memory can be tested by looking at the three outputs of the OR circuit. Therefore, if the same test equipment is used, ten or more tests can be performed in parallel at the same time.

In addition, the cache memory is provided with a mode signal and a comparator for the cache data section, and a two-step test pattern and its inverted pattern are provided, and the output of the comparator of the cache memory and the output of the comparator for the cache data section are You can test the cache data by looking at the two videos. Therefore, if the same test device is used, it is possible to test six or more devices at the same time.

[Brief explanation of the drawing]

FIG. 1 shows the first cache memory test method of the present invention.
FIG. 2 is a circuit block diagram for explaining the second embodiment of the cache memory test method of the present invention; FIG. 3 is a circuit block diagram for explaining the conventional cache memory test method. FIG. 2...Mode signal, 4...First part of cache address register, 6...Second part of cache address register, 8...Cache tag part , 1o...Cache data section, 1
2...Cache comparator, 14...A
ND circuit, 16...OR circuit, 18...
・Data line, 20... Cache data bit line, 22... AND circuit output, 24...
...OR circuit output.

Claims (2)

[Claims] (1) Cache data consisting of a mode signal indicating write mode and read mode, a cache address register that stores address data, and a random access memory that receives the mode signal and is accessed using the first part of the cache address register as input. a second portion of the cache address register and a cache tag portion; a cache comparator that compares data from the second portion of the cache address register and the cache tag portion; and an AND circuit that performs an AND operation on all bits of the data from the cache data portion. Then, an OR circuit is provided that performs OR on all bits of data from the cache data section, and as a first step, addresses corresponding to all words of the cache memory are consecutively stored in the first part of the cache address register in write mode. data of 1 is always given to all bits in the second part of the cache address register, data of 1 is always given to all bits in the cache data section, and data of 1 is always given to all bits in the cache data section; and always write data of 1 to all words of the cache tag section, and then continuously give addresses corresponding to all words of the cache memory to the first part of the cache address register in read mode, and In the second part, data of 1 is always given to all bits, and data of all words is read from the cache data section and the cache tag section, and the cache comparator reads the data from the cache tag section and the cache tag section. The second part of the address register is compared, and the AND circuit tests the data from the cache data part and does this for every word of the cache memory, and in a second step the first part of the cache address register is tested in write mode. is given consecutive addresses corresponding to all words of the cache memory, the second part of the cache address register is given data of 0 for all bits, and the cache data part is given data of 0 for all bits. Always give 0 data, always write 0 data to all words of the cache data section and the cache tag section, and then write the addresses corresponding to all the words of the cache memory to the first part of the cache address register in read mode. are continuously given, data of 0 is always given to all bits in the second part of the cache address register, data is read from the cache data section and the cache tag section, and the cache comparator reads the data from the cache data section and the cache tag section. A cache memory characterized in that data from the cache tag section is compared with a second portion of the cache address register, and the OR circuit tests the data from the cache data section for all words of the cache memory. Test method. (2) Cache data consisting of a mode signal indicating write mode and read mode, a cache address register that stores address data, and a random access memory that receives the mode signal and is accessed using the first part of the cache address register as input. a second portion of the cache address register, a cache tag portion, a cache tag portion, a cache data register that stores data to be written to the cache data portion, a second portion of the cache address register, a cache that stores data from the cache tag portion and data to be written to the cache data portion. A cache data comparator is provided for comparing the data registers, and as a first step, addresses corresponding to all words of the cache memory are successively applied to the first part of the cache address register in write mode, and the second part of the cache address register is provided with a cache data comparator for comparing the data registers.
a first pattern of data that is different for each word is given to the cache data section, a second pattern that is different for each word is given to the cache data section from the cache data register,
writing a different pattern for each word in all the words of the cache data section and the cache tag section, and then sequentially giving addresses corresponding to all the words of the cache memory to the first part of the cache address register in a read mode; The second part of the cache address register is given the first pattern, the cache data register is given the second pattern, all words of data are read from the cache data section and the cache tag section, and the cache data register is given the second pattern. The cache comparator compares the data from the cache tag section with the second portion of the cache address register, and the cache data comparator compares the data from the cache data section and the data from the cache data register and caches the data. This is done for all the words of the cache memory, and as a second step, in the write mode, the addresses corresponding to all the words of the cache memory are successively given to the first part of the cache address register, and the addresses corresponding to all the words of the cache memory are given to the second part of the cache address register in write mode. an inverted pattern of a first pattern is applied to the cache data section, an inverted pattern of a second pattern is applied from the cache data register to the cache data section, and a first stage inversion is applied to all words of the cache data section and the cache tag section. write a pattern, and then in a read mode, a first part of the cache address register is given addresses corresponding to all words of the cache memory successively, and a second part of the cache address register is given an inverted pattern of the first pattern. the cache data section and the cache tag section; the cache comparator compares the data from the cache tag section with a second portion of the cache address register; the cache data comparator reads the data from the cache data section and the cache tag section; A cache memory test method is characterized in that data from a cache data register is compared with data from a cache data register and this is performed for all words of the cache memory.