JPH0341374A - Pattern generator - Google Patents

Abstract

PURPOSE:To generate pattern data without increasing capacity by a circuit receiving a plurality of bits in parallel to perform logical operation at every corresponding control bit and a circuit receiving the output thereof in parallel to store the same as pattern data. CONSTITUTION:A bit reversal control circuit 12 and a pattern data memory circuit 11 storing the output data thereof are provided. The data of the circuit 11 is applied to the circuit 12 as a control bit to allow the pattern data generated one before to act as a reversal condition and the data accessed presently is reversed to generate the next pattern data. By this method, the pattern data is determined by the combination of the data in the previous address and the data in the present address and different pattern data are generated even when the same address is accessed and, even when the kinds of memory data of a memory are scarce, pattern data varying by a number possible in the combination of data can be formed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a pattern generator, and more particularly, to a pattern generator for an IC tester that generates pattern data by accessing a pattern memory according to address information generated from a sequence generator. The present invention relates to a pattern generation device for an IC tester that can generate a wide variety of pattern data even if the memory capacity of a pattern memory for storing data for pattern generation is increased.

[Prior Art] In conventional IC testers, separate pattern generators are provided for each test device, such as a pattern generator for memory testing and a pattern generator for logic testing. The pattern generator has a circuit that generates an address for accessing a pattern memory called a sequence pattern generator (SQPG) or sequence generator as hardware that controls the flow (sequence) of a pattern program. There is.

In addition, in recent test systems for very large scale integrated circuits (VLSI), since both memory and logic are tested at the same time, the test pattern generator has a pattern memory 1 for memory and a pattern memory 2 for logic, as shown in FIG. are provided, and these pattern memories 1
.

[Problem to be solved] In this way, in a pattern generator that generates pattern data by accessing a pattern memory using 5QPG, pattern generation data must be stored for each pattern to be output in order to generate a wide variety of patterns. Generated pattern data is written in advance into a pattern memory from an external storage device, which is necessary especially in the case of pattern generation on the logic side.

A pattern generator that generates patterns using this method has a drawback that test efficiency is reduced by the time it takes to write the generated pattern data into the pattern memory from the beginning.

In order to avoid this, it is possible to increase the storage capacity of the pattern memory, but as the number of items to be tested increases and the functionality of the IC to be tested increases, the required capacity increases. Is this the one you want to be together with? In the future, memory capacity will have to increase proportionately. Moreover, there is a limit to the capacity of the pattern memory that can be increased, and the limit is exceeded.

The present invention solves the problems of the prior art, and aims to provide a pattern generator that can generate a wide variety of pattern data without increasing the capacity of the pattern memory. do.

[Means for Solving the Problems] The configuration of the pattern generation device of the present invention to achieve such an object includes a memory for storing data for pattern generation, and address information for accessing this memory that is sequentially generated. and a sequence generator that accesses this memory by
A logic operation circuit that receives multiple bits of data output from the memory in parallel and performs a logical operation on each received bit according to a control bit corresponding to each bit, and from this logic operation circuit. output 6 - a pattern data storage circuit that receives each output bit in parallel and stores it as pattern data;
Each bit of the pattern data stored in the pattern data storage circuit is sent to the logical operation circuit as a control bit corresponding to each bit, and each bit of the pattern data stored in the pattern data storage circuit is sent to each address of the memory. Correspondingly, the original data before being subjected to logical operations by the logical operation circuit is stored, the memory is accessed by the sequence generator, and the pattern data stored in the pattern data storage circuit is outputted to the outside.

[Function] In this way, the bit inversion control circuit and the pattern data storage circuit that stores the output data of the bit inversion control circuit as output pattern data are provided, and the data in the pattern data storage circuit is bit inverted as the control bit. By adding it to the control circuit, it is possible to use the previously generated pattern data as an inversion condition to invert the currently accessed data and generate the next pattern data.

Therefore, pattern data can be determined by a combination of data at the previous address and data at the current address, and different pattern data can be generated even if the same address is accessed. Even if the number of types is small, it is possible to generate a wide variety of pattern data to the extent that they can be combined.

As a result, even if the memory capacity for pattern data is small, it is possible to generate a wider variety of pattern data than before. In this case, instead of inverting the relationship between the previously generated pattern data and the data generated by accessing the memory, the pattern data is calculated by logical operation using AND logic, OR logic, or other logic. A similar effect can be obtained by generating .

[Embodiment] Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 1 shows an IC to which the pattern generator of the present invention is applied.
It is a block diagram of the pattern generation part of the tester, and the second
Figures (a) and (b) are explanatory diagrams of data stored in each memory of the pattern generator of the embodiment and the conventional pattern generator.

Reference numeral 10 is a 5QPG, which is mainly composed of an instruction memory and has a built-in selector, program counter, etc., as in the past. This sets the address for accessing the pattern memory in the program counter according to the data contents of the instruction memory, accesses the pattern memory, reads data from the pattern memory, and controls the sequence of pattern data generated. The instruction memory includes an address data area for accessing the data memory and a device under test (DUT) area.
A control data area for reading/writing, etc., and an instruction control information area for controlling the next instruction memory address, etc. are provided. Control data of a bit inversion command that causes the bit inversion control unit 12 to perform bit inversion processing is stored.

`` is a data memory that is accessed by the 5QPG 10, generates original data that becomes the basis of pattern data from the accessed address, and sends it to the bit inversion control unit 12. In order to generate pattern data corresponding to the pins of OUT (device under test), a pin-corresponding memory section "a" is provided corresponding to the pins.

``b,...,''n, and each bit serving as the original data of the pattern data output from the respective pin-corresponding memory sections ``a, flb,...''n is controlled by a bit inversion control unit. Output to 12.

Ru.

The bit inversion control unit 12 controls pin-corresponding memory units “a” and “b”.
+..., bit inversion control circuits 13a, 13b+... provided corresponding to "n".

0- 13n, pin-corresponding memory sections "a" and "b".

. . , "n". The bit inversion control circuits 13a, 13b, *a*+ 13n are EXO
R (exclusive OR), receives the signal (1 bit) output from the memory section corresponding to each pin into one input,
When the signal applied to the other input is "1", that signal (1-bit signal of one input) is inverted and output. Furthermore, when the signal applied to the other input is "0", the 1-bit signal of one input is output as is.

Each bit inversion control circuit 13 al 13 b+ ・
....

The outputs of 13n are output from flip-flops (F/F) 14a, 14b, .
14n, and the flip-flops 14a, i4
b, "'"+14 The data stored in rx is sent to the pin electronics circuit 16 in correspondence with the pins as pattern data.

data) 15a, 15b of the bit inversion control unit 12;

..., 15n are flip-flops 14a, 15n, respectively.
14b, *@@, and 14n are received on one side, and the gate control signal (HI GH level (hereinafter referred to as “H
”) or “1”/LOW level (or “L”) or “
bit inversion control circuits 13a, 13b, .
..., 13n to the other input of EXOR. The gate control signal applied to each data) 15a, 15b, . . . , 15n is supplied from the 5Q PGIO via the control line 10a.
”, the outputs of the flip-flops 14a, 14b, @”5 14n are added to the other input of each EXOR.As a result, the output of the flip-flop 14a, 14b, @”5 14n is added to the other input of each EXOR. , flb, ...
, "n is inverted and output from each EXOR, which is then outputted from each flip-flop 14a, 14b, *
It is stored in the corresponding storage location of e, 14n. vice versa,
For the bit where the signal of the other input of EXOR is 0'', the pin pair t, memory section ``A, 1 l b+
..."The corresponding bit of "n" is output as is without being inverted, and similarly, each flip-flop 14a.

The data are stored in corresponding storage locations 14b, . . . , 14n.

Each of these flip-flops 14a, 14b.

The data stored in the bit inversion control circuits 13a, 13b, .・、
13n as a control bit to its corresponding circuit, and then used as data to perform inversion control on data generated when the data memory is accessed.

By the way, when the bit inversion control unit 12 receives a signal from the 5QPG 10 in which the gate control signal is in the "L" degree state, the gates 15a, 15b, . . .

15n closes. As a result, its output side is maintained at "L" (that is, "0"), and the flip-flop 14a+
14b, ``@@, 14n pin-corresponding memory section ``a, flb, .
....

14n and stored. Therefore, by setting the gate control signal to "H" or "°L", the data memory
It is possible to perform inversion control on the data to generate pattern data, or to use the data as it is as pattern data.

Here, when the gate control signal is "H", the pattern data applied from the flip-flops 14 al 14 b, . . . , 14 n to the pin electronics circuit 16 is not the data itself obtained from the data memory, but one The data is inverted and controlled by the previously generated pattern data. In the case of this inversion control, the data stored in the data memory is not the pattern data itself, but is inverted controlled by the previous generated pattern data determined by the data at the address previously accessed in the data memory. The previous data, the original data before the inversion control, is stored there.This is different from the data stored in the conventional pattern memory.This data difference 44 will be explained with reference to FIG.

What is shown in FIG. 2(b) is the data stored in the pattern memory shown in FIG.
Pitsu) Data of (0, 1, 2) for 8 addresses (@~
■Only the address (address) is shown. Also, (a) in the same figure
What is shown in FIG. 1 is the above-mentioned data stored in the data memory shown in FIG.

In conventional pattern data generation, 5Q in Figure 3 is usually used.
The PGIO sequentially accesses one address at a time from address 0 to address 7, as shown in (b) of the figure, to generate pattern data. In this case, the stored data at each address corresponds to the pattern data itself. On the other hand, the data at each address shown in (a) of Figure 2 is
It is not the pattern data itself, but the data before being inverted by the previous pattern data, and as shown in the figure, it is possible to obtain the conventional pattern data for 8 locations with 4 locations.

In this case, the data memory generated by 5QPGIO”
As shown in the figure, the addresses are 0, 1, 2, 1, 3, and 1.

'2nd address, then 1st address.

In other words, access address 0 and read °“00” as before.
0” and then access address 1, “OO”0
” and EXO corresponding to each bit position (digit position) of “001”
R is taken between these, resulting in (b
) is the same data as address 1.

°“001” is generated. Next, the 2nd address is accessed and “0” is read out, and EXOR is performed between this and the previous pattern data “001”, and the 2nd address in (b) of the same figure is read out. Same data.

"010" can be obtained. In the same way, next address 1 is accessed and "001" is obtained from the "data memory", and "01" is the pattern data that occurred one time before.
By performing an EXOR with "0", it is possible to obtain "0"', the same data as at address 3 in (b) of the same figure.
Similarly, if the above-mentioned addresses, 3rd address, 1st address, 2nd address, and 1st address are accessed in this order, the same data as from addresses 4 onwards in FIG. 4(b) can be obtained.

Note that the following is a control in which the 5QPG 10 applies a gate control signal "H" to each gate 15a, 15b, ..., 15n to keep the gates open, but the data memory "
If you want to use the data as it is as pattern data, 5
The QPG 10 may set the gate control signal to "L" to stop its inversion control.

As explained above, in the embodiment, the gates 15a, 1
5b, . . . , 15n are provided, but the outputs of the flip-flops may be directly input to EXOR and constantly inverted to generate pattern data without providing these gate circuits. Further, in the embodiment, each gate circuit is commonly controlled, but a gate control signal may be sent to each individual gate circuit to control each gate circuit. Furthermore, a plurality of gate circuits may be grouped and each gate circuit may be controlled as a group.

In the embodiment, Example 17 is given where only inversion control is performed by EXOR, but this is not applicable to other logical operations, such as OR.
The next pattern data may be generated by performing a logical operation on the data in the data memory and the previously generated pattern data using a logical operation such as logic or AND logic.

Although the inversion control signal in the embodiment is controlled to be inverted at "1", it is of course possible to perform inversion control at "0".

[Effects of the Invention] As can be understood from the following description, the present invention includes a bit inversion control circuit and a pattern data storage circuit that stores output data of the bit inversion control circuit as output pattern data. Then, by adding the data of this pattern data storage circuit as a control bit to the bit inversion control circuit, the pattern data generated one time ago acts as an inversion condition, inverting the currently accessed data and inverting the next data. Pattern data can be generated.

As a result, even if the memory capacity for pattern data is small, it is possible to generate a wider variety of pattern data than before. In this case, instead of inverting the relationship between the previously generated pattern data and the data generated by accessing the memory, the pattern data is calculated by logical operation using AND logic, OR logic, or other logic. A similar effect can be obtained by generating .

[Brief explanation of drawings]

FIG. 1 shows an IC to which the pattern generator of the present invention is applied.
Block diagram of the pattern generation part of the tester, Figure 2 (a)
) and (b) are explanatory diagrams of stored data in each memory of the above embodiment and the conventional pattern generator, and FIG.
FIG. 2 is a block diagram of a pattern generation portion of a conventional IC tester. 1...Pattern memory for memory, 2...Pattern memory for logic, 10...5Q
PG"1...Data memory,"a, flb, 1ln-
Bin corresponding memory unit, 12... Bit inversion control unit, 12a, 12b, 12n... Bit inversion control circuit, 9-13 a + 13 b + 13 n... Bit inversion control circuit, 14a, 14b, 14n -Flip-flop, 15 al 15 b+ 15 n...
Gate.

Claims (2)

[Claims] (1) In a pattern generation device having a memory that stores data for pattern generation and a sequence generator that sequentially generates address information to access this memory and accesses this memory, the data output from the memory is A logic operation circuit that receives multiple bits in parallel and performs a logical operation on each received bit according to the control bit corresponding to each bit, and a logic operation circuit that processes each bit output from this logic operation circuit in parallel. and a pattern data storage circuit for receiving the data and storing it as pattern data, each bit of the pattern data stored in the pattern data storage circuit being sent to the logic operation circuit as a control bit corresponding to each bit, At each address of the memory, original data before being logically operated by the logic operation circuit is stored corresponding to each bit of the pattern data stored in the pattern data storage circuit, and the memory is accessed by the sequence generator. A pattern generating device characterized in that the pattern data stored in the pattern data storage circuit is outputted to the outside. (2) In a pattern generation device having a memory that stores data for pattern generation and a sequence generator that sequentially generates and accesses address information for accessing this memory, a plurality of data output from the memory bits in parallel, and each received bit is set to “0” in the control bit corresponding to each bit.
and “1”, the corresponding bit is inverted, and the control bit “0” and “1” are inverted.
a bit inversion control circuit that outputs the corresponding bit as is according to the other of the bits, and a pattern data storage circuit that receives each bit output from the bit inversion control circuit in parallel and stores it as pattern data. each bit of the pattern data stored in the pattern data storage circuit is sent to the bit inversion control circuit as a control bit corresponding to each bit; Original data that is selectively inverted according to "0" or "1" of each bit of the stored pattern data is stored, and the memory is accessed by the sequence generator and stored in the pattern data storage circuit. A pattern generation device characterized in that the generated pattern data is outputted to the outside.