JPS5937787B2 - Integrated circuit testing equipment - Google Patents

Description

[Detailed description of the invention] This invention relates to integrated circuit testing equipment.

As shown in FIG. 1, the current integrated circuit testing equipment stores test patterns written from an external storage device 11 that stores the test patterns of the integrated circuit under test 10 on each pin number of the integrated circuit under test. The transferred test pattern is transferred to the high-speed buffer memory 12 that operates at a test frequency corresponding to 1:1, and is sent to the conversion system device 13 consisting of a driver and a comparator as an input pattern of the driver 131.
Also, as a comparison pattern for the comparator 132, it is outputted from the S buffer memory operating at the test frequency.

Since the buffer memory has a finite capacity, if this capacity is insufficient, the test pattern will be divided and transferred several times from an external storage device. The first one like this
The test equipment has a large capacity external storage device in order to store extremely long and random test patterns of test objects such as microcomputer LSIs, and further increases the number of transfers from the external storage device to the buffer memory. It is desired to increase the time taken up for transfer in the total test time to improve both economic efficiency and test equipment throughput.

The present invention has been made in response to such needs, namely, an external storage device for storing test patterns of subjects;
A buffer memory that transfers the pattern or part of the information of the external storage device directly or in a converted state to the subject as an input pattern and sends a reference pattern corresponding to this input pattern to the comparison circuit; An information modification instruction system device that instructs modification of information based on an instruction, an information modification control memory that transfers information transferred from an external storage device to a computing system device according to instructions from the information modification instruction system device, and an information modification control memory that instructs information modification control memory. An integrated circuit testing device characterized in that it is equipped with the arithmetic device that calculates information in an external storage device based on the transferred information and transfers the calculation result to a buffer memory, and is used for testing a test object. .

FIG. 2 shows a system block diagram of an embodiment of the integrated circuit testing apparatus of the present invention.

In FIG. 2, external storage device 21 and buffer memory 22 are connected via a switch 24. In FIG. In these devices, a magnetic disk, a magnetic drum, or a storage section of a computer is used as an external storage device to store the test pattern of the subject.
Normally, this external storage device operates at a slower speed than a buffer memory. Buffer memory is a high-speed memory that normally operates at the test frequency, and has a finite memory capacity for each channel of the terminal under test. Then, the pattern or partial information of the external storage device is transferred directly or in a converted state to the subject 20 as the input pattern, and the reference pattern corresponding to this input pattern is transferred to the comparison circuit.
The switch switches the writing pattern to the buffer memory to either a pattern from an external storage system device or a pattern subjected to an arithmetic operation by the arithmetic system device 25. The switching instruction is given by control from the external storage device or by the write control device 28. The information modification control memory 26 is a memory that stores sequence information that instructs what kind of arithmetic operation is to be performed on the content of any address in the buffer memory and to which address in the buffer memory to write, and the information modification control memory 26 stores the information content transferred from the external storage device. is sent to the calculation system device according to the instruction from the information modification instruction system device 27. The information modification instruction system device further transfers instruction information to the write control system device 28, the calculation system device, and the switch according to the instruction from the external storage system device. According to the information transferred from the pattern modification control memory, the arithmetic system equipment performs arithmetic operations, including 1:1 operations, on the information from the external storage system equipment or the content of any address in the buffer memory, and transfers the information to the buffer memory via the switch or through the buffer memory. Transfer immediately. The write control system device transfers a write command to a buffer memory or a temporary storage register (not shown) included in the calculation system device according to the contents of the pattern modification control memory.
Further, this write control system device is configured to be able to determine the address of the buffer memory when inputting the output pattern of the buffer memory to the calculation system device. The conversion system device 23 uses a driver 231 to convert the input pattern to the signal voltage level of the test object as a test pattern, and a comparator 232 to convert the response output voltage of the test object to a logic level to output the buffer memory, that is, a reference output pattern. Compare the test results with the test results to detect matches or discrepancies between the two and determine whether the test subject is good or bad. In the example of FIG. 2, a switch is disposed to disable the use of the example of FIG. 1, but this can be removed if it is not necessary.

The function of the write control system equipment may be included in the information modification/instruction system equipment, and the independent arrangement may be omitted. As already mentioned, the external storage device stores test patterns and information to be transferred to the information modification control memory.

Further, the external storage system device transfers modification information to the information modification control memory via a path 2126, sends a modification start command to the information modification instruction system device through a path 2127, and the information modification control memory is indicated by a path 2726. The address is determined by a command from the information modification instruction system device, and the modification information corresponding to that address is sent to the writing control device and the calculation system device. The contents of the information modification control memory are sent to the calculation system equipment through the path 2625, where a calculation operation corresponding to the contents of the information modification control memory is performed on the pattern transferred through the path 2125.
The modified test pattern can be transferred to the switch via path 2524 and to the buffer memory via path 2422. An instruction as to which address in the buffer memory is to be written is sent to the address switching device 30 through a path 2830, and a write command is issued from the write control system device through a path 2822. The address switching device provides a write or read address to the buffer memory on path 3022. When testing the subject 20, the address in the buffer memory of the pattern given to the driver 231 and comparator 232 from the buffer memory is sent from the test address generating device 29 via the path 2930 to the address switching device 30 and then to the buffer memory via the path 3022. given to. The test address generation device is a device that generates test addresses for buffer memory, and
The frequency and the route of the start and stop commands 2129 are given from the external storage device 21. The address switching device changes the test address from the test address generating device 29 to the address via the path 2829 from the write control device 28 in response to a command from the test address generating device through path 2930 or a command through path 2830 from the write control system device 28. Switch. Control information to the write control system device is given from the information modification memory through a path 2628.

A write command from the write control system device is sent to the calculation system device via path 2825, and the calculation system device that instructs writing to one or more temporary storage registers included in the calculation system device is sent to the path 2125. The arithmetic operation can be performed on the pattern sent from the external storage device sent by the path 2225, the buffer memory pattern shown by the path 2225, or the temporary storage register included in the arithmetic device according to the calculation contents shown by the path 2625. can. Arithmetic operations can be performed on the patterns sent via path 2225 either while testing a subject or not. When testing, the output of the buffer memory is given to the test object by a driver, and the output of the test object is converted to a logic level by a comparator and compared with the reference pattern of the buffer memory to determine whether the test object is good or bad. , the write control system device determines the address of the buffer memory through the path 2830, connects the output pattern at that address to the calculation system device through the path 2225, performs the calculation operation here, and then sends the write control system through the path 2830. The device determines the write address of the buffer memory 22 and writes path 2.
A modified pattern can be written by a write command of 822. The address in the buffer memory of the pattern sent to the computing system equipment via path 2225 and the address at which the modified pattern is written do not necessarily need to be the same, and can be determined by the write control system equipment.
If no test is being performed, the contents of the buffer memory can be modified in the same manner as in the above case, except that the driver and comparator are not operating. When testing, the information modification control system device can also start operating in response to a modification start command via path 2927 from the test address generating device. In short, in the integrated circuit testing device of the present invention, information modification instruction system equipment, information modification control memory, and calculation system equipment are added to the buffer memory, so that part of the information content of the buffer memory is modified at the test frequency while the buffer memory is operating. Since it is possible to write data into the buffer memory, some of the contents of the buffer memory can be changed with a certain regularity, and the buffer memory can be scanned multiple times for comparison between the subject's input test pattern and the subject's output response pattern. It may be possible to transfer the reference pattern.

Therefore, when a part of the test pattern is changed with a certain regularity and repeated multiple times, the memory capacity of the external storage device can be reduced, the number of transfers can be reduced, and the processing capacity can be improved. For example, in FIG. 3, it is assumed that a pattern at one or more addresses is modified based on a certain regularity while looping from one address to another address in the buffer memory. P, Q, R, S, etc. in the diagram A are buffer memory I,
The pattern of pins from one pin number to another at addresses j, k, and l is expressed as a numerical value. While rouzoting from address i to l several times, P at address i increases by 2, Q at address j increases by 1, R at address k increases by 2, and S at address l increases by 1. In the case of incrementing by increments, in the first loop, the pattern at address i is sent as an input to the driver and as a reference pattern to the comparator, and then the value P is modified and written as the value P+2 by the arithmetic device. Similarly, at address j, Q is modified and written to the value Q+2. In this way, when the pattern at address i is sent to the driver and comparator for the second time, it is possible to send a modified pattern like a diagram. When the number of repetitions of the loop in the above example increases, according to the present invention, only the buffer memory at address i-1 is required, so the effect of reducing the buffer memory capacity becomes greater. Furthermore, in the present invention, arithmetic operations with a certain regularity are performed between the information transferred from the external storage device and the information already stored in the buffer memory or information modification control memory, and the arithmetic results are reproduced. Can be written to buffer memory. Therefore, operations such as modifying part of the information transferred from the external storage device to create a test pattern, or assigning each bit simultaneously sent from the external storage device to a predetermined channel or channels of the buffer memory, etc. It can be done.

[Brief explanation of the drawing]

FIG. 1 is a diagram of a conventional integrated circuit testing apparatus, FIG. 2 is a block diagram of an integrated circuit testing apparatus according to the present invention, and FIG. In Figure 2, 20... Subject, 21... External storage device, 22... Buffer memory, 27
... Information modification instruction system equipment, 25 ... Arithmetic system equipment, 26 ... Information modification control memory.

Claims (1)

[Claims] 1. An external storage device that stores the test pattern of the test subject, and a standard that transfers the pattern or part of the information of this external storage device directly or in a converted state to the test subject as an input pattern, and that corresponds to this input pattern. A buffer memory that sends patterns to a comparison circuit, an information modification instruction device that instructs modification of information according to instructions from an external storage device, and a calculation system that sends information transferred from the external storage device to a calculation system according to instructions from the information modification instruction device. information modification control memory to be transferred to the device;
An integrated circuit that is equipped with a calculation system device that calculates information in an external storage device based on information transferred from the information modification control memory and transfers the calculation result to a buffer memory, and is used for testing a subject. Circuit testing equipment.