JPH01205799A - Memory circuit testing machine - Google Patents

Abstract

PURPOSE:To shorten testing time by preparing writing data according to writing address information and preparing expected data by comparing reading address information and the expected data. CONSTITUTION:When the data are written to a memory circuit 6, first, a test execution control part 1 sets the address information to an address register 2 and sends a writing control signal through a writing and reading control line 9 to a buffer 5 and the circuit 6. Thereafter, the address information set to the register 2 is sent to an arithmetic part 3 and the circuit 6, and the writing data, for which an operation is executed, are written through the buffer 5 to the circuit 6. On the other hand, when the data are read, the control part 1 sets the address information to the register 2, and the arithmetic part 3 divides the address information and sends the information to be obtained to a data comparing part 4 as the expected data. Thereafter, the data read from the circuit 6 are compared with the expected data at the comparing part 4, and the quality of the read data is decided by the compared result obtained by comparing the read data with the expected data. Thus, the testing time can be shortened.

Description

TECHNICAL FIELD The present invention relates to a memory circuit tester, and more particularly to a memory circuit tester for verifying the normality of write and read operations of a memory circuit.

BACKGROUND ART Conventionally, this type of memory circuit testing machine has a test execution control section, and is configured to create write data and expected data in this test execution control section.

The conventional memory circuit tester will be explained using FIG. 3.

FIG. 3 is a system diagram showing the configuration of a conventional memory circuit tester. In the figure, the conventional memory circuit tester includes a test execution control section 18, an address register 2, a data register 20, a data comparison section 4, and a buffer 5. This is what we do.

When writing data to the memory circuit 6, the test execution control unit 18 first creates write data and writes it to the data register 20.
Set to . The set write data is sent to the memory circuit 6 via the buffer 5 and data line 8. At the same time, the test execution control section 18 sets address information in the address register 2, and the address information is sent to the memory circuit 6 via the address line 7. Furthermore, the test execution control section 1
8 sends a write control signal to the memory circuit 6 via a write/read control line 9, and write data is written into the memory circuit 6.

On the other hand, when reading and comparing data from memory circuit #I6, the test execution control unit 18 creates expected data and sets it in the data register 20. The set expected data is sent to one of the inputs of the data comparison section 4. and,
The test execution control unit 18 sends the address information of the address register 2 to the memory circuit 6 via the address line 7, and the data stored in the memory circuit 6 is read out by a read control signal sent via the write/read control line 9. . The read storage data is sent to the other input of the data comparator 4 via the data line 8 and buffer 5, and compared with expected data.

However, in the conventional memory circuit tester described above, the test execution control unit 18 creates write data and expected data, and sets the data in the data register 20, so random pattern data is transferred to the memory circuit 6. When attempting to write data to and test, the test execution control unit 18 has to create write data and expected data and set them in the data register 20 each time the address is updated, and the test execution control unit 18 has to perform a lot of processing. This has the disadvantage that the test time becomes longer.

OBJECTS OF THE INVENTION An object of the present invention is to provide a memory circuit tester that can shorten test time.

The memory circuit tester of the present invention includes a writing means for writing write data to a predetermined address of a memory circuit according to write address information, and a writing means for writing stored data to a predetermined address of a memory circuit according to read address information. A memory circuit testing machine having a reading means for reading data and a comparison means for comparing the stored data with expected data, wherein the write data is created according to the write address information, and the write data is created according to the read address information. and data creation means for creating the expected data.

Example Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a system diagram showing the configuration of an embodiment of a memory circuit testing machine according to the present invention, and parts equivalent to those in FIG. 3 are indicated by the same reference numerals. In the figure, a memory circuit tester according to an embodiment of the present invention includes a test execution control section 1, an address register 2, an arithmetic section 3, a data comparison section 4, and a buffer 5. This test is for testing the memory circuit 6.

The test execution control unit 1 sets address information, sends a write or read control signal, reads data comparison results, and controls test execution procedures.

The address register 2 holds address information sent from the test execution control section 1 and sends it to the memory circuit 6 and the calculation section 3 via the address line 7.

The arithmetic unit 3 takes in address information from the address line 7, divides the information into several byte information, calculates the byte information together to create one byte of information, and sends it to the data line 1o. be.

The buffer 5 takes in information on the data line 10 during a memory write operation and sends it to the memory circuit 6 via the data line 8.
Information on the data line 8 is taken in during a memory read operation and sent to the data comparator 4 via the data line 11.

The data comparator 4 connects the data line 10 to the data line 10 during the memory read operation.
and 11, compares the two, and sends the results to the test execution control section 1.

In this configuration, when writing data to the memory circuit 6, the test execution control section 1 first sets address information in the address register 2, and sends a write control signal to the write/read control line 9.
The data is sent to the buffer 5 and memory circuit 6 via the buffer 5 and the memory circuit 6. and,
The address information set in the address register 2 is sent to the arithmetic unit 3 and the memory circuit 6, respectively. The calculation unit 3 divides the address information and sends the information obtained by calculation to the buffer 5 via the data line 10 as write data.

Buffer 5 sends write data to memory circuit 6 upon receiving the write control signal. The memory circuit 6 receives the write control signal and writes data.

On the other hand, when reading and comparing data from the memory circuit 6, the test execution control section 1 sets address information in the address register 2, and sends a read control signal to the buffer 5 and the memory circuit 6. The address information set in the address register 2 is sent to the arithmetic unit 3 and the memory circuit 6. Arithmetic unit 3
divides the address information and sends the information obtained by calculation to one of the inputs of the data comparator 4 as expected data. Then, the stored data is read from the memory circuit 6 and sent to the buffer 5 in response to the read control signal.

When the buffer 5 receives the read control signal, it sends the data to the other input of the data comparator 4.

The data comparison section 4 compares the data read and sent from the memory circuit 6 with expected data and sends the result to the test execution control section 1. The test execution control section 1 determines the quality of the read data based on the comparison result from the data comparison section 4.

Next, the calculation section 3 will be explained using FIG. 2.

In Figure 0, which is a system diagram showing the configuration of the calculation unit 3,
The arithmetic unit 3 includes two arithmetic circuits 12 and 13. Address lines 14, 15 and 16 are obtained by dividing address line 7 in FIG. 1 into three. Arithmetic circuit 12
is an adder circuit that takes in information on address lines 14 and 15, calculates both, and sends the result to data line 17. Further, the arithmetic unit 13 includes a data line 17 and an address line 16.
takes in the information, calculates both, and sends the result to data line 1.
This is an adder circuit that sends out 0.

That is, in the present invention, since the write data and expected data to be written to the memory circuit 6 are created from address information, the processing of the test execution control section 1 is reduced, and the test time can be shortened.

As explained above, the present invention provides an arithmetic unit that creates write data and expected data from the address information of the address line. This has the effect that setting processing can be omitted and test time can be shortened.

[Brief explanation of the drawing]

FIG. 1 is a system diagram showing the configuration of a memory circuit tester according to an embodiment of the present invention, FIG. 2 is a system diagram showing the configuration of the calculation section 3, and FIG. 3 is a system diagram showing the configuration of a conventional memory circuit tester. It is a system diagram. Explanation of symbols of main parts 1... Test execution control section 3... Arithmetic section 4... Data comparison section 6... Memory circuit

Claims (1)

[Claims] (1) A writing means for writing write data to a predetermined address of a memory circuit according to write address information, a reading means for reading stored data according to read address information, and an expectation of the stored data. A memory circuit testing machine having a comparison means for comparing data, the memory circuit testing machine creating the write data according to the write address information,
A memory circuit tester comprising: data creation means for creating the expected data in accordance with the read address information.