JPH03176710A - Initialization control system for information processor - Google Patents

Abstract

PURPOSE:To reduce a load due to reset at the time of restarting and to attain high speed operation by providing a local processor with a means for informing the sort of reset. CONSTITUTION:When a power supply is turned on, a reset signal is inputted to the local processor 6 by a reset control mechanism 2 and the processor 6 is restarted to read out the value of a reset state holding means 11. Since the values of MRST and H/WRST are set up to '1', the write/read check of an optical value is executed and then a value saved in a register is written. Thus, the preceding value can be held in the case of reset other than the connection of the power supply.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an information processing device equipped with a memory and a processor that operates according to a program on the memory.
The present invention relates to an initialization control method for an information processing device that can perform appropriate initialization as needed.

[Conventional technology]

Conventionally, information processing apparatuses receive a reset signal when the power is turned on or when a program runs out of control, thereby restarting the program. In this case, t
It is not possible to distinguish between a reset at the time of #1 input and a reset at the time of program runaway, and a method has been adopted in which all initial settings are made and the program is operated every time a reset signal is input. Therefore, the data that had been accumulated before the program ran out of control would be lost when the program was reset due to the runaway. As an example of solving this problem, JP-A-61
There is one disclosed in JP-202233.

In this method, judgment data stored in the ROMIζ of the information processing device is loaded into the RAM of the information processing device during initial settings, and when a reset signal is input to the information processing device, the initial settings are preceded. Then, the judgment data in the ROM and the judgment data in the RAM are compared, and if they match, the program is executed without performing new initial settings, and if they do not match, the judgment data is written and Run the program after performing initial settings.

On the other hand, recently, as the performance and functionality of information processing equipment has progressed, information processing equipment has become more and more advanced.
In addition to a sub-processor (hereinafter referred to as a local processor), it has come to consist of a plurality of control units operated by a sub-processor (hereinafter referred to as a local processor). An example thereof is shown in FIG. The information processing device 17 is an MPUI,! J upper set control mechanism 2.
It is composed of a main storage device 3 (hereinafter referred to as main memory), a plurality of control units 4 (hereinafter referred to as I10 adapters), and a system bus 5 that connects these to each other. one I1
The adapter 4 includes an interface circuit 8 that interfaces the local processor 6, local memory 71, system bus, and adapter 4, and a local bus 9 that connects them to each other. In such an information processing device 17, there are three types of resets for the adapter 4 as shown below.

(1) iJt source investment large input set (hereinafter referred to as FOR)
A reset signal supplied from the reset control mechanism 2 to the entire information processing device 17 when the power is turned on.

(2) Resetting the entire system using MPUI (hereinafter referred to as
(referred to as MR8T) When the MPU 1 determines that it is necessary to reset the entire information processing device 17, the reset signal that the MPU 1 supplies to the reset control mechanism 2 distinguishes between this signal and FOR, thereby allowing a free run at the time of reset. (for example, dynamic memory refresh circuits).

(3) Resetting each I10 adapter (hereinafter referred to as H/W
RIT) When the MPUI attempts to reset an individual I10 adapter 4 (for example, when an error occurs only in the I10 adapter 4), a reset command is issued to the I10 adapter 4, and the interface circuit 8 in the I10 adapter 4 Now, the reset pulse generation circuit 10 analyzes the command,
Generate the necessary reset signals.

These three types of reset signals (POR13, MR8'r1
4. H/WRS T15 ) are combined by a NOR gate 12 in the interface circuit 8, and this signal is output to the R8Ti child of the local processor 6. The output of the NOR gate 12 is normally at the "H" level, and when any one of the three types of resets (13, 14, 15) is input, it outputs the "'L" level.

When the “L” level is input to the R8Ti child, the local processor 6 initializes its internal state and stores ρ in the local memory 7.
Restart from address.

In this way, a reset is generated as needed, and only the necessary control section or circuit is reset.

[Problem to be solved by the invention]

The above-described prior art does not take into account the 4j system in which parts other than the judgment data of R and AM are destroyed when the program runs out of control. In other words, even though the program itself in RAM was destroyed due to a runaway program, the RAM
If the above judgment data is not destroyed, the program is restarted without performing initial settings, which causes the problem that the program runs out of control again.

In addition, when multiple resets are generated, from the perspective of the information processing device 17 as a whole, they can be seen as different resets with different meanings, but from the perspective of the local processor 6 of one device 10 adapter 4. It can only be seen as a reset signal input to the R8Ti child of the local processor 6. Therefore, for any of the reset signals (13, 14, 15), the local processor 6 has no choice but to initialize the local memory 7, so there is a problem in that the information before the reset cannot be left behind.

The purpose of the present invention is to ensure that 11
An object of the present invention is to provide an initialization control method for an information processing device that can be set up and reset as necessary.

[Means to solve the problem]

In order to achieve the above object, the present invention, as shown in FIG. IJ upper set control mechanism 2゜Main memory 3. I10 adapter 4, a system bus 5 that connects these to each other, and an interface circuit 8 that constitutes I10 adapter 4. An information processing device initialization control method in an information processing device 17 that includes a local processor 6, a local memory 7, and a local bus 9 that connects these to each other, the interface circuit 8 having a reset state holding means that indicates the type of reset. 11 is provided so that the content of the reset state holding means 11 can be read by the local processor 6.

The reset state holding means 11 can be configured by allocating and holding the supplied reset signal as is in bit units.

The reset state holding means 11 maintains M after supplying the reset signal.
It can be configured by holding the contents given by commands from the PUI.

[Effect]

Next, the operation of the present invention will be explained with reference to FIG.

When the reset state holding means 11 holds reset signals, each reset signal is held directly by hardware. This is assigned to different bits of an arbitrary address seen from the local processor 6 so that the local processor 6 can read it. Further, an address is assigned to this held state so that it can be cleared by write access by the local processor. As a result, the previous reset state remains and there is no possibility of malfunction.

Further, when the reset state holding means 11 holds a command given from the MPUI, the MPU 1 instructs the type of reset according to the contents of the command, and the local processor 6 reads this contents and processes the corresponding reset. Do this. When the command is issued from the MPUI, a flag in the reset state notification means 11 is turned on. The local processor 6 issues the command,
This can be determined by flag-on detection. Therefore,
There is no possibility of malfunctions caused by reading the stored contents before issuing a command.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is an overall configuration diagram of an embodiment of the present invention.

This figure is a diagram in which the reset state holding means 11 of FIG. 6, which is a feature of the present invention, is applied to FIG. 7.

That is, in this embodiment, three types of resets are used: POR43 and MFLST14°H/WR8T15. As a result, the reset state holding means 11 is composed of respective reset holding sections (18, 19, 20).

First, the operation of the reset state holding means 11 will be explained using FIG. FIG. 2 is a circuit diagram of the reset state holding means 11 used in this embodiment. The respective reset states are maintained by edge-triggered flip-flops (hereinafter abbreviated as FFs: 18, 19, 20). F
F goes high from the Q terminal when the S terminal goes to the ``H'' level.
Outputs the level, and the T terminal changes from 1lLl level @ HI
When the level changes to T, the input value of the D terminal is output to the IJ terminal.Here, all the D terminals are grounded, so the input of the T terminal changes from "L" level to "H" level. When this happens, the output of the Q terminal becomes "L" level.

First, the reset signal (poben13.MR8T14°H/
When WR8T15) is input, FF (18,
19, 20), the Q output of the corresponding F'F (34,
35 or 36) becomes an "H" output.

Next, reading of F F (18, 19, 20') in one shift will be explained. The local bus 9 includes an address signal (ADR) 22 and a data signal (Data) 24.
It consists of a write signal (WR) 21 and a read signal (D) 23. W R21,! :RD 23 is enabled at the ``H'' level during writing and reading, respectively.

Therefore, when the local processor 6 reads the address assigned to the reset state holding circuit 11, the address signal is decoded by the address decoder section 14, and the output 32 becomes an "H" level. As a result, the output of the A N D gate 26 becomes ``H'' level, and the tristate output gates (27, 28, 29) are enabled. Therefore, F F (18, 19.

The output signals (34, 35, 36) of the tri-state output gates (27, 28, 29)
38, 39).

The data signal is outputted to the data signal line 24 of the local bus 9 via the data signal line 24 of the local bus 9.

Finally, clearing of the values held in F F (18, 19, 20) will be explained. Here, when the local processor 6 writes to another address assigned to the reset state holding circuit 11, the address signal is decoded by the address decoder section 14 and the output 30 becomes 1H'' level.Next, the write signal 21 becomes H At the same time, the output 31 of the AND gate 25 changes from the "IIL" level to the "H" level and is input to the T terminals of the FFs (18, 19, 20), and each Q terminal becomes a 1L" level output.

In this way, the reset state is maintained and cleared.

The control procedure using the above reset state holding means 11 will be explained using the flowchart of FIG. 3.

First, when the power is turned on, reset the controller from $2 to P
OR13 is supplied and a reset signal is input to local processor 6 via gate 12 and signal line 16.

As a result, the local processor 6 restarts from address ρ (step 40).

Next, the value of the reset state holding means 11 is read out (step 41). Here, as explained earlier, the value of POR is 1
8 is '1''. Therefore, this is determined in step 42, and the process proceeds to normal reset processing (clearing all memories, generating parity). Step 43. Checking write/read of all memories: step 44).After that,
Perform the necessary initial settings (step 46), clear the value of the reset state holding means according to the previously explained procedure (step 47), and proceed to the original control processing (step 48).
). Next, consider the MR' that occurred while I10 adapter 4 was operating.
The processing of IT 14 or H/WR8T15 will be explained.

In the same way as described above, the value of the reset state holding means 11 is read from the initial address (step 40) (step 41). Here, MRS T or H/WR8
Since the value of T is 1'', the process moves from step 42 to step 45. In step 45, the memory value is read and saved in the register, and a write/read check of an arbitrary value is performed on that address. After that, write the value saved earlier into the register.Do this for all memories.

Then, steps 46 to 48 are executed in the same manner as described above. In this way, the previous values (programs and parameters) can be retained when the power is turned on other than when the power is turned on.

Next, a second embodiment of the present invention will be described. FIG. 4 is an overall configuration diagram of an embodiment of the present invention, and shows the reset state holding means 11 of FIG. 6 in detail. The reset state holding means 11 has a command register mark in which the MPUI writes a code indicating the type of reset, and a flag 49 indicating that the MPUI has written a value to the command register mark.
It consists of

The flag 49 is set to ``1'' when the MPUI accesses the command register 50, and is reset to ``O'' when a reset signal is input.The processing procedure using this reset state holding means 11 is shown in FIG. The flowchart in FIG. 5 partially corresponds to the flowchart in FIG. 3 (steps 40, 43 to 46-48).

First, when a power-on reset is supplied, the local processor 6 restarts from address ρ (step 40), as described above. Next, the flag 49 is read, the value is determined, and if it is "0", a loop is executed (step 51). M
PU1 writes a code indicating FOR in the command register 52.

As a result, the flag 49 becomes '1''. Therefore, the process moves from step 51 to step 52, and the code of the command register is read. Then, the code is judged (step 53), step 43 (clearing all memory),
After performing step 44 (write/read check of all memories), perform necessary initialization (step 46),
The process moves to actual control processing (step 48). next,
The processing of a reset that occurs while the I10 adapter 4 is in operation will be explained. The local processor 6 starts from the address ρ as described above (step 40). Here, the flag 49 is cleared to 6ρ'' by the reset.

Therefore, the local processor 6 waits in step 51 until the command register 50 is saved from the MPUI. MPU1- writes a reset code other than when the power is turned on to the command register 50. Therefore, the local processor 6 reads the value of the command register in step 52, determines the code in step 53, and proceeds to step 45. In step 45, a save type write/read check of all memories is performed as described above, and in step 46. Proceed to step. In this way, as in the previous embodiment, in the case of a reset other than when the power is turned on, the value before the reset can be saved.

In the above two embodiments, the save type write/read check of the entire memory in step 45 may be performed on some areas, and the other areas may be cleared. Further, all or some of the other initial settings in step 46 may not be performed at the time of reset other than when the power is turned on. Further, although the reset state holding means 11 is provided in the interface circuit 8, it may be built in the local processor 8.

〔Effect of the invention〕

According to the present invention, since the type of reset can be distinguished, data such as programs and operating parameters, and statistical information such as trace information and logging information are retained without being cleared when a reset is performed other than when the power is turned on. can. This eliminates the need to reset the initialized program more than necessary, reducing the load upon restart due to reset and increasing speed. Also, statistical information can be stored accurately.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a block diagram of an embodiment of the present invention.
1, FIG. 3 is a flowchart of the process shown in FIG. 1, FIG. 4 is a block diagram of the second embodiment of the present invention, and FIG. FIG. 6 is a block diagram showing the configuration of the present invention, and FIG. 7 is a block diagram of a conventional information processing apparatus. l...MPU 2...Reset control mechanism 3...Main memory 4...I10 adapter 6...Local processor 7...Local memory 8...Interface circuit 11...Reset state holding means 13 ...Reset signal at power-on (FOR) 14...
・System reset signal (MR8T) 15...I10
Adapter unit reset signal (H/WR8T) 17... Information processing device 18, 19, 20... POR, MR8T', H/
WR, ST holding circuit 49...Command register written flag 50...
・Command register

Claims (1)

[Scope of Claims] 1. A central processing unit that is in charge of overall control, a main memory that holds programs and data of the central processing unit, and a reset control mechanism that is in charge of resetting the device, and is connected to a common bus and dedicated to the system. An initialization control method for an information processing device including a local processor that performs processing and a local memory that stores programs and data of the local processor, further comprising means for notifying the local processor of the type of reset. An initialization control method for information processing equipment. 2. A local processor that is connected to a common bus with a central processing unit that controls the entire system and that performs dedicated processing, and is characterized in that the local processor is provided with means for notifying the type of reset. 3. An LSI connected to a common bus with a central processing unit that controls the entire system, and equipped with a local processor that performs dedicated processing and means for notifying the type of reset. 4. An information processing device that performs the initialization control method according to claim 1. 5. The method for initializing an information processing apparatus according to claim 1, wherein the reset type notification means holds each reset signal. 6. The reset type notification means, after the reset,
2. The initialization method for an information processing device according to claim 1, wherein the initialization method is provided by a central processing unit in the form of a code. 7. The initialization control method for an information processing apparatus according to claim 1, wherein any initial setting is not performed based on the notification of the type of reset.