JPH05257725A - Error transmitter for cpu unit - Google Patents

Abstract

PURPOSE:To efficiently operate respective units by shortening system recovery time discriminating the cause of system error at the other unit and by continuing the operations without resetting when there is no influence upon the processing of its own unit, when the system error is generated. CONSTITUTION:Processing contents are selected corresponding to the states of a system reset signal 12 to be inputted/outputted between a CPU unit 2 for calculating/executing the contents of a program and the other unit (such as an output unit 3, special function unit 4 and data link unit 5) controlled by the CPU unit 2, and a CPU error signal 13 to directly transmit error inside the CPU unit 2 to the other unit.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CPU unit error detection device and a CPU unit error transmission device for executing various controls based on the error detection.

[0002]

2. Description of the Related Art FIG. 4 is an explanatory diagram showing a configuration of a conventional programmable controller. In the figure, 1
Is a power supply unit for supplying power to the system, 2 is for executing arithmetic processing for controlling other units, CPU unit is the center of the system, and 3 is externally turned on / off based on a command input from the CPU unit 2. The output unit 4 for outputting the OFF information is a special function unit which is connected to an external device (computer, monitor device) and exchanges information with the CPU unit 2.

Reference numeral 5 is a data link unit for performing data communication between systems through a dedicated line, and 6 is a unit connecting a power supply unit 1, a CPU unit 2, an output unit 3, a special function unit 4 and a data link unit 5. The base unit 7 is provided in the CPU unit 2, and an error signal (power supply reset signal: hereinafter referred to as ΣREL signal) 10 from the power supply system to notify that the power supply is down 10
And a reset circuit that integrates an error (calculation error etc.) signal (hereinafter referred to as CPUERR signal) 11 generated inside the CPU and outputs a system reset signal (hereinafter referred to as ΣMRE signal) 12, 8 is connected to the special function unit 4 An external device (computer, monitor device, etc.) that exchanges information by executing the data link unit 5 via a dedicated line.
It is a system (slave station system) connected with. Also, 1
5 is an MPU (microprocessor) provided in the CPU unit 2, 16 is a latch circuit provided in the output unit 3, and 17 is an M provided in the special function unit 4.
PU (microprocessor), 18 is a communication interface also provided in the special function unit 4, 19 is an MPU (microprocessor) provided in the data link unit 5, and 20 is also provided in the data link unit 5. Output port.

Next, the operation will be described. In the system, if the power supply unit 1 goes down or the CPU unit 2 becomes unexecutable due to an operation error or the like during the execution of the program, the ΣREL signal 10 and the CPUERR will be issued as power down notices, respectively.
Signal 11 is generated. These signals are sent to the CPU unit 2
It is input to the reset circuit 7 therein, and the logical sum is obtained in the circuit and output as a ΣMRE signal 12 to each unit.

Next, each unit that has detected the ΣMRE signal executes its reset processing. In the output unit 3, the external output latch circuit 16 is cleared and all the outputs are turned off. In the special function unit 4, the ΣMRE signal is connected to the RESET terminal of the internal MPU 17 so that the internal device is reset and the external device 8
Interrupt communication with. In the data link unit 5, like the special function unit 4, the MPU 19 is reset, but the transmission system is not reset, so other slave station systems can detect that the system is down, and this system Is disconnected from the link line to continue the data link.

In addition, "Reset / Retry Circuit" disclosed in Japanese Patent Application Laid-Open No. 2-234241 and Japanese Patent Application Laid-Open No. 3-172924 as reference technical documents related to the present invention.
There is a "printer control system" disclosed in the publication.

[0007]

In the conventional system, the ΣMRE signal is output even if one of the CPUERR signal generated in the CPU unit 2 and the ΣREL signal from the power supply unit has an error. Therefore, in other units, the system goes down in a state where it cannot be determined which factor caused the reset,
As a result, there is a problem that it takes time to determine the cause of the reset and it takes time to restore the system.

When a system down occurs,
There is also a problem that other units are inefficient in operation of the system because they automatically reset and stop operation even if they do not affect their own units.

The present invention has been made to solve the above problems, and when a system error occurs, another unit determines the cause of the system error, shortens the system recovery time, and reduces the system recovery time. It is an object of the present invention to obtain an error transmission device of a CPU unit that can continue the operation without resetting and efficiently operate each unit when there is no influence on the processing.

[0010]

An error transmitting device for a CPU unit according to the present invention calculates the contents of a program,
A system reset signal input / output between the CPU unit to be executed and another unit (output unit, special function unit, data link unit, etc.) controlled by the CPU unit, and an error inside the CPU unit, The processing content is selected based on the state of the CPU error signal transmitted to the unit.

[0011]

The system reset signal (ΣM
RE) and the CPU error signal (CPUERRL) are factors (power system error / C) when a system error occurs.
Error in the PU) is transmitted from the CPU unit to other units as information.

[0012]

【Example】

[Embodiment 1] An embodiment of the present invention will be described below with reference to the drawings. In FIG. 1, 1 is a power supply unit and 2 is a CPU
Unit, 3 is an output unit, 4 is a special function unit,
Reference numeral 5 is a data link unit, 6 is a base unit, 7 is a ΣREL signal 10 from the power supply unit 1 and a CPUERR signal 11 inside the CPU unit 2 are integrated to obtain a ΣMRE.
A reset circuit that outputs a signal 12 and an external device (computer, monitor device) 8 connected by communication with the special function unit 4.

Reference numeral 9 is a system (slave station system) connected to the data link unit 5 by a dedicated line. CPU
In the unit 2, there are two signals that are connected to the reset circuit 7 as a CPUERR signal 11 inside the CPU and a CPUERRL signal 13 that is directly connected from the base unit 6 to other units. In the output unit 3, CP
Output form when the UERRL signal 13 is input (all points O
The output mode selection switch 14 for selecting FF or holding the output state) is built in. Further, 15 is an MPU (microprocessor) provided in the CPU unit 2, 16 is a latch circuit provided in the output unit 3, and 17 is an MPU provided in the special function unit 4.
(Microprocessor), 18 is a communication interface also provided in the special function unit 4, 19 is an MPU (microprocessor) provided in the data link unit 5, and 20 is also provided in the data link unit 5. Output port.

Next, the operation will be described. In FIG. 1, when the CPU unit 2 and the system are operating normally, the ΣMRE signal 12 and the CPUERRL signal 13 are in the non-active state. Here, when the ΣREL signal 10 becomes active as a power-down notice due to a failure in the power supply system, the ΣMRE signal 12 is activated as in the conventional system.
Becomes active, each unit (output unit 3, special function unit 4, data link unit 5) enters a reset state, and the output unit 3 turns off the output.

In the special function unit 4, before the power is turned off, the CPUERRL is passed through the communication interface 18.
Since the signal 13 is non-active, it can be transmitted to the external device 8 that the system is down due to an error in the power supply system, and the external device 8 can provide a more specific response (for example, an alarm due to an abnormality in the power supply system). It will be possible.
In the data link unit 5, similarly to the special function unit 4, the data link unit 5 can notify the other slave station 9 that the system is down due to an error in the power supply system, and notify the slave station of the cause of the system down of the own station. it can.

Next, when an error occurs inside the CPU unit 2, the processing in the CPU unit 2 can distinguish between an error that requires a system down and an error that does not require a system down.
In the case of an error that causes the system to go down, the CPUERR signal 11 and the CPUERRL signal 13 are activated.
As a result, the ΣMRE signal 12 and the CPUERRL signal 1
3 becomes active, and each unit (output unit 3,
The special function unit 4 and the data link unit 5) are in a reset state, and the output unit 3 outputs its output OF.
F

In the special function unit 4, since the CPUERRL signal 13 is active via the communication interface before the reset processing, it is possible to inform the external device 8 that the system is down due to an error in the CPU unit 2. As the external device 8, it becomes possible to take more specific measures (messages for CPU inspection, etc.) than before. In the data link unit 5, the CPU unit 2 is connected to another slave station 9 through the dedicated line in the same manner as the special function unit 4.
Communicate that the system is down due to an internal error,
It is possible to notify the slave station of the cause of the system down of its own station.

Finally, among the errors inside the CPU unit 2, if the error does not require system down, the CPUERR signal 11 is inactive and the CPUE
Only the RRL signal 13 is activated. by this,
ΣMRE signal 12 is non-active and only CPUERRL signal 13 is active, and each unit (output unit 3, special function unit 4, data link unit 5)
In the output unit 3, the mode setting switch 14 can be used to select whether to turn off all the outputs or maintain the output state when an error that does not require a system down occurs. Can work. In addition, the special function unit 4 and the data link unit 5 operate normally (external device 8 and slave station 9
It is possible to transmit the fact that an error has occurred in the CPU unit 2 of the local station to the external device 8 or another slave station 9 as one piece of information while continuing the data communication).

[Second Embodiment] Next, a second embodiment according to the present invention will be described. 2 and 3 show a second embodiment of the present invention.
2 is an explanatory diagram for explaining the embodiment of FIG. 2, and the description of the portions having the same contents as those of the embodiment 1 shown in FIG. 1 will be omitted.

In FIG. 2, a system gate array 30 is provided with an error check circuit 30a for executing various error checks in the apparatus and a CPU error I / O port 30b. The error check circuit 30a detects a WDT error or the like by hardware. Further, the CPU error I / O port 30b selectively outputs various errors of severe, moderate and mild. Here, the severe error includes a runaway of the CPU, a WDT error when the hardware of the CPU does not operate normally, and the moderate error includes a calculation check error.
Further, the minor error includes a battery error and the like.
Further, 31 is a setting switch which allows the user to selectively set whether to treat the medium error as a minor error or a serious error, and 32 is an MPU 15, an error check circuit 30a, and a CPU error I / O port. A CPU bus for transmitting signals between the two.

In the above configuration, how the CPUERRL signal 13 and the .SIGMA.MRE signal 12 are used to distinguish between errors will be described below. First, the CPU
When the ERRL signal 13 is at the “L” level, the ΣMRE signal 12
Is at the "H" level, it is judged to be a minor CPU error. Secondly, the CPUERRL signal 13 is "H".
When the ΣMRE signal 12 is at the “L” level, it is determined to be a medium error such as a power supply error. Third
When the CPUERRL signal 13 is at the “L” level,
When the E signal 12 is at "L" level, it is determined that the CPU has a serious error. Fourth, CPUERRL signal 1
When 3 is at "H" level and the ΣMRE signal 12 is at "H" level, it is determined to be normal.

FIG. 3 is an explanatory diagram showing the configurations of the output card unit 3a, the intelligent special function unit 4a, and the data link unit 5a in the second embodiment. In addition to the latch circuit 16, the output unit 3a includes ,
A setting switch 14a is provided which allows the user to select whether to hold or reset the output in the case of a CPU error, particularly a medium error or a light error.

The intelligent special function unit 4a is provided with an I / O port 33 in addition to the MPU 17 and the communication interface 18 for communicating with the external device 8. Then, when an error occurs, the MPU 17 checks the error content of the I / O port 33 by the NMI operation and sends the content to the communication interface 18, whereby the external device 8 side can determine the error in the system, The recovery time can be shortened.

The data link unit 5a includes an MPU 1
9, an I / O port 34 and a link interface 35 are provided. This data link unit 5a
Similarly to the intelligent special function unit 4a, can transmit an error of its own station to another slave station system when an error occurs.

[0025]

As described above, according to the present invention, CP
The UERRL signal and the ΣMRE signal are wired on the bus, and on the other hand, each unit (output unit 3, special function unit 4, which can determine the error content by the content of the two signals)
By configuring with the data link unit 5), the error of its own station can be transmitted to other systems (external device, slave station) connected by the dedicated line, and when a system error occurs, the system of other units When the cause of the error is determined, the system recovery time is shortened, and when the processing in the own unit is not affected, the operation can be continued without resetting and efficient operation of each unit can be achieved.

[Brief description of drawings]

FIG. 1 is an explanatory diagram showing a schematic configuration (Embodiment 1) of a programmable controller according to the present invention.

FIG. 2 is an explanatory diagram showing a schematic configuration (second embodiment) of a programmable controller according to the present invention.

FIG. 3 is an explanatory diagram showing a schematic configuration (second embodiment) of a programmable controller according to the present invention.

FIG. 4 is an explanatory diagram showing a schematic configuration of a conventional programmable controller.

[Explanation of symbols]

 1 Power Supply Unit 2 CPU Unit 3 Output Unit 3a Output Card Unit 4 Special Function Unit 4a Intelligent Special Function Unit 5 Data Link Unit 5a Data Link Unit 6 Base Unit 7 Reset Circuit 8 External Device 9 Slave Station System 10 Error Signal (ΣREL) 11 Error signal (CPUERR) 12 System reset signal (ΣMRE) 13 Error signal (CPUERRL) 14 Output mode selection switch 30 System gate array 30a Error check circuit 30b CPU error I / O port 31 Setting switch

Claims (1)

[Claims] 1. A CPU for calculating / executing program contents
A system reset signal input / output between a unit and another unit controlled by the CPU unit (output unit, special function unit, data link unit, etc.) and an error inside the CPU unit are directly transmitted to the other unit. An error transmission device for a CPU unit, characterized in that processing contents are selected based on a state of a transmitted CPU error signal.