JPH07129424A - One-bit error detection informing device for ecc function circuit - Google Patents

Abstract

PURPOSE:To prevent a system from being stopped due to the trouble of two-bit error by informing the detecting of one-bit error in data outputted from a memory circuit corresponding to the switching of a mode to a CPU as memory abnormality. CONSTITUTION:When the error of one bit is detected, a one-bit error detect signal ER1 is outputted as '1' by an ECC function circuit 5 and when the error over two bits is detected, an over two-bit error detect signal ER2 is outputted as '1'. When reporting one-bit error to a CPU 1, a memory access control part 3 applies a test mode signal TM as valid '1' to an AND gate G1 inside a mode switching part 4. When the mode switching part 4 for switching the detection mode of bit error is turned to a one-bit error detection valid mode, the one-bit error detect signal ER1 of '1' outputted from the ECC function circuit 5 is informed to the memory access control part 3 as abnormal MER and reported to the CPU 1 as interrupt INTM.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an EC as a circuit for detecting an error in output data of a memory circuit and generating a correction code.
The present invention relates to a device in which a C function circuit notifies the CPU of detection information output when a 1-bit error is detected as a memory abnormality.
In the drawings, the same reference numerals denote the same or corresponding parts.

[0002]

2. Description of the Related Art FIG. 2 shows an example of the configuration of a main part of an information processing apparatus having an ECC function circuit of this type. In the figure, 1 is a CPU, 6 is a memory circuit, and 5 is an ECC function circuit that detects an error in the output data 6a of the memory circuit 6 and generates a correction code for a 1-bit error. In addition, this ECC
The functional circuit 5 outputs a 1-bit error detection signal ER1 when detecting a 1-bit error, and outputs a 2-bit or more error detection signal ER2 when detecting an error of 2 bits or more. Two
Is an access control unit that controls the output of data 6a from the memory circuit 6 in response to a memory access request from the CPU 1 and inputs error detection signals ER1 and ER2 from the ECC function circuit 5 to detect an error of 2 bits or more. The signal ER2 is notified to the CPU 1 as a memory abnormality interrupt INTM. 7 is a data bus.

As described above, in general, the information processing apparatus includes a circuit for detecting an error in the output data 6a of the memory circuit 6 and a circuit for detecting an error.
ECC comprising a circuit for generating a bit error correction code
A functional circuit 5 is added. Even if there is a frequent 1-bit error in the data from the memory circuit 6 due to a failure of the memory circuit 6 or a disconnection of the data line, the 1-bit error is automatically corrected by the ECC function circuit 5. 1-bit error detection signal ER1
Is not notified and is left as it is.

[0004]

As described above, in the conventional information processing apparatus, when a 1-bit error of data is detected in the normal operation, the data is automatically corrected, so that the failure of the memory frequently occurs. Even if a 1-bit error occurs in the data, the memory failure or the like cannot be detected, and another 1-bit error may occur by accident, causing the system to go down.

Therefore, it is an object of the present invention to provide a 1-bit error detection / notification device of an ECC function circuit which can notify a CPU of a 1-bit error according to a mode setting and prevent a system down.

[0006]

In order to solve the above-mentioned problems, in the 1-bit error detection notification device of the present invention, a circuit (5 or the like) having an ECC function outputs data from a memory circuit (6 or the like) ( 6a, etc.) detection information for detecting and outputting a 1-bit error (1-bit error detection signal ER1, etc.)
CP when setting a predetermined mode (test mode, etc.)
It is assumed that a unit (mode switching unit 4, memory access control unit 3, etc.) for notifying U (1 etc.) (as a memory abnormality interrupt INTM, etc.) is provided.

[0007]

In the access control unit 2, the 1-bit error detection signal ER1 from the ECC function circuit 5 is set in accordance with the mode setting.
A circuit for notifying the CPU 1 as an interrupt signal INTM indicating a memory abnormality is provided.

[0008]

1 is a block diagram of the essential parts of an information processing apparatus as an embodiment of the present invention and corresponds to FIG. In FIG. 1, a memory access control unit 3 and an AND
A mode switching unit 4 including a gate G1 and an OR gate G2 is provided. Next, the operation of FIG. 1 will be described. CPU
1 reads data from the memory circuit 6, the CPU 1
Makes a memory access request to the access control unit 2. The requested memory access control unit 3 in the access control unit 2 controls the data output from the memory circuit 6. For the data 6a output from the memory circuit 6, the ECC function circuit 5 detects a data bit error. When the ECC function circuit 5 detects a 1-bit error as described above, the ECC function circuit 5 outputs the 1-bit error detection signal E.
When R1 is output as "1" and an error of 2 bits or more is detected, the error detection signal ER2 of 2 bits or more is "1".
Output as. The memory access control unit 3 includes the CPU 1
When a 1-bit error is to be notified to the CPU 1 based on a command such as the above, the test mode signal TM is given as valid "1" and given to the AND gate G1 in the mode switching unit 4.

Therefore, when the mode switching unit 4 for switching the bit error detection mode is in the 1-bit error detection valid mode (that is, the test mode signal TM is "1"), the ECC function circuit 5 outputs "1". 1-bit error detection signal ER1 of "AND gate G1, OR gate G2
The memory access control unit 3 is notified as a memory abnormality MER via. The memory access control unit 3 that has received the memory abnormality MER notifies the CPU 1 as an interrupt INTM.

[0010]

According to the present invention, the detection of a 1-bit error in the data 6a output from the memory circuit in response to the mode switching is notified to the CPU as a memory abnormality INTM. Since a 1-bit error can be detected, system stoppage due to a 2-bit error can be prevented in advance. For example, if a regular memory diagnostic program or the like is executed in the 1-bit error detection valid mode (test mode), it is possible to detect a 1-bit error abnormality of the memory online, and therefore the system reliability can be improved. it can.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a main part of an information processing apparatus as an embodiment of the present invention.

FIG. 2 is a conventional configuration diagram corresponding to FIG.

[Explanation of symbols]

 1 CPU 2 access control unit 3 memory access control unit 4 mode switching unit 5 ECC function circuit 6 memory circuit 6a output data of memory circuit 6 7 data bus G1 AND gate G2 OR gate ER1 1 bit error detection signal ER2 2 bits or more error detection Signal TM Test mode signal MER Memory error INTM Memory error Interrupt

Claims (1)

[Claims] 1. An ECC, comprising: a circuit having an ECC function, which detects a 1-bit error in output data from a memory circuit and outputs detection information to a CPU when setting a predetermined mode. 1-bit error detection notification device for functional circuit.