JPH0219932A - Back-up device for development of microprocessor - Google Patents

Abstract

PURPOSE:To eliminate the synchronizing error between a microprocessor kept in a break state and a target system by always designate the ready signal inputted to the microprocessor via the target system. CONSTITUTION:A controller 2 outputs a high level while a microprocessor 1 is kept in a break state and the address set by a switch 10 is outputted to a target system via a fixed address buffer 7. The target system outputs a ready signal READY18 and the target data 12 based on a read signal 22. Then the signal READY18 is inputted to the controller 2 and the microprocessor 1. Thus the microprocessor 1 uses the signal READY18 of the target system to give an access to a break memory 3. As a result, the synchronizing error is avoided between the microprocessor 1 and the target system.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a microprocessor development support device, and in particular, the present invention relates to a microprocessor development support device, and in particular, the microprocessor itself reads a clear memory and performs processing on a target system without outputting control signals such as signals. Microprocessor development during the period from when emulation is stopped until the next execution of emulation (referred to as break) by creating control signals using the bus cycle start signal, READY signal, CLK signal, etc. output by the microprocessor. The present invention relates to a microprocessor development support device that allows the support device to perform trouble-free debugging without having any particular influence on a user's system under development (referred to as a target system).

[Conventional technology]

Conventionally, this type of microprocessor development support equipment usually outputs the address output by the microprocessor to the target system as is. ), even during a break, the output signal to the target system was simply the output signal of the microprocessor through a buffer and was output as is. However, it was necessary to control whether or not input signals on the target system during break are input to the microprocessor. especially,
Since the READY signal is not always input from the target system when the microprocessor is in break mode, it is necessary to forcefully use the READY signal created within the microprocessor development support equipment to continue operation. It had become.

There was no problem with this method for ordinary microprocessors, but in recent high-speed microprocessors, the microprocessor itself does not output a clear memory read signal, etc., but instead uses a bus cycle start signal output by the microprocessor on the target system. The configuration is such that the control signal is created using the READY signal, CLK signal, and the like. For this reason, when this microprocessor executes a debug program, the READ button in the microprocessor development support device
Using the Y signal, the target system creates R
There was a possibility that synchronization with the EADY signal could not be achieved.

In other words, the relationship between control signals such as memory read signals created by the target system itself and signals output by the microprocessor development support device to the debugging target system becomes confused, causing the target system to fall into an abnormal state. was there.

This example will be explained using FIGS. 3 and 4.

FIG. 3 is a block diagram of a conventional microprocessor development support device, in which the left side of the broken line shows the inside of the microprocessor development support device, and the right side shows the target system.
FIG. 4 is an example of a bus cycle timing chart of a microprocessor used in the microprocessor development support device shown in FIG.

Based on the timing shown in FIG. 4, the microprocessor 1 selects the address 8. Bus cycle start signal (hereinafter referred to as
(referred to as BCY signal)15. A memory read/write signal (hereinafter referred to as R/W signal) 16 is output, and READ
A bus cycle is executed by inputting the Y signal 17 and inputting/outputting data 11. The BREAK/RUN controller 2 uses a BREAK/RUN control signal (hereinafter referred to as B) to control whether the microprocessor 1 executes a program on the target system or a debug program written in the break memory 3.
/R signal) 14 is output. The break memory 3 stores a debugging program, and the microprocessor 1 executes this program during a break.
Continue debugging the target system. Break memory 3 has address 8. Data 11 is connected, and data 11 is read according to the specified address 8 by one control signal generated by the controller (control signal generator for break memory) 4.

Write. Break memory 3 is B/R signal 14
Activates only when is at high level.

The controller 4 receives the BCY signal 15. R/W signal 16, R
Using the EADY signal 17, a memory read signal for the Targetera I system (hereinafter referred to as ME
One control signal similar to MR is created. Address buffer 6 outputs address 8 to the target system as target address 9. READY selector 2
1 is READY from the target side (hereinafter TREAD
It has a function to select either READY (hereinafter referred to as MREADY) 20 inside the microprocessor development support device, and the selection is made by the B/R signal 14.
It is determined by the inverted signal, and when it is high level, TR
Select EADYl 8, and when it is low level, MREAD
Select Y20. The data buffer 5 transfers data 11 to target data 12 or target data 1.
2 inputs and outputs data to and from the data 11 according to the R/W signal 16. The data buffer 5 is enabled when the signal obtained by inverting the B/R signal 14 is at a high level, and disabled when it is at a low level. The control signal generator 13 generates a BCY signal 15, an R/W signal 16, and a TREADY signal.
The signal 17 is used to generate a MEMR signal 22, etc., shown in broken lines in FIG.

The MEMR signal 22 is connected to BCY as indicated by the dashed line in FIG.
It becomes active at the rising edge of signal 15, and T2CLK
This signal becomes inactive by detecting the rising edge after the signal and the fact that TREADY18 is active.

The microprocessor configured as described above operates as shown below.

During emulation, the controller 12 outputs a low level to the B/R signal 14, and the break memory 3
is disabled, data buffer 5 is enabled, R
The EADY selector 21 selects TREADY18. The target system receives the BCY signal 15 and R/W signal 1 from the memory specified by the output target address 9.
MEMR signal 22, which becomes active at 6, is used to output data to target data 12. At this time, TREADYl8 is also activated at the same time. The control signal generator 13 terminates the MEMR signal 22 at this TREADY18. Microprocessor 1 outputs address 8,
After outputting the BCY signal 15 and R/W signal 16, the RE
When ADY signal 17 becomes active, data 11
is taken to terminate this bus cycle. As described above, when the microprocessor 1 is executing the program on the target system, the program is executed normally.

When the microprocessor 1 stops execution of the program on the target system (there are many methods for stopping, but they will not be explained here) and transitions to execution of the break memory 3, the controller 2 outputs the B/R signal. Set 14 to high level. Naturally, the data buffer 5 is disabled, and the R, EADY selector 21 is set to MREADY2.
Select 0.

Inside the microprocessor development support device, the microprocessor 1 outputs the address 8 to the break memory 3, and outputs the BCY signal 15° R/W signal 16 to the controller 4. The controller 4 receives the BCY signal 15. R/W signal 1
6 activates control signal 19 and MREAD
Make it inactive by Y20. MREADY2
0 becomes active or inactive at the appropriate timing for the microprocessor 1 to access the break memory 3. When the control signal 19 is a memory read signal, the break memory 3 outputs the data 11 in accordance with the control signal 19.

The microprocessor 1 uses T2CLK as shown in FIG.
Data 11 is read by detecting the rising edge of the signal and the fact that READY 17 is active. In other words, the microprocessor development support device ignores TREADYl8 of the target system during a break, so it operates completely unrelated to the target system. The operation during break from the target system side is first the BCY signal 15. The R/W signal 16 causes the control signal generator 13 to activate the MEMR signal 22. Control signal generator 13 does not deactivate MEMR signal 22 until TREADYl8 becomes active. Therefore, MREADY20 and TREADYl
If the timing of 8 is different, the BCY signal 15 from the microprocessor development support device may become active again even though the bus cycle of the target system has not finished, resulting in the disadvantage that normal operation cannot be maintained. was there.

Furthermore, the method for masking the output of the BCY signal 15 to the target system side during break is the microprocessor 1
If the microprocessor itself operates at high speed, the active timing of the BCY signal 15 will be delayed when accessing the target system during a break, so if the execution speed of the microprocessor is high, there is a risk that the access timing will not be satisfied, so this cannot be adopted.

[Problem to be solved by the invention]

As is clear from the above explanation, the microprocessor itself does not output a clear memory read signal, etc., but uses the bus cycle start signal, READY signal, CLK signal, etc. output by the microprocessor on the target system to read memory data. A microprocessor development support device using a microprocessor configured to generate control signals such as read signals has a problem in that the operations of the microprocessor development support device and the target system become out of synchronization during a break.

Therefore, the present invention aims to provide a microprocessor development support device that solves the above-mentioned problems.

In contrast to the conventional microprocessor development support device described above, the present invention always reads the address to be output to the target system during a break from the target system.
It has an original content in that the response of the Y signal can be specified to a specific fixed address or a specific range address, and the READY signal of the target system is always input to the microprocessor.

[Means to solve the problem]

A microprocessor development support device according to the present invention includes a microprocessor that generates a control signal by applying a signal to a control signal generator of a target system, and a break memory that stores a debugging program and receives address signals from the microprocessor. , a break/run controller that specifies whether the microprocessor executes an emulation program on the target system or a break program that executes the debugging program; and a break/run controller that specifies that at least a part of the address signal is fixed. an address consisting of an address buffer and, when the break/run controller specifies emulation, a fixed address specified by the fixed address buffer and a portion of an address signal from the microprocessor, or an address specified by the fixed address buffer; an address buffer that outputs only a fixed address from the microprocessor to the target system when the break/run controller specifies a break; a data buffer for inputting/outputting data input/output to the processor and the break memory to the target system; and a READY from the Targetera I system.
The break memory control signal generator is configured to input a signal together with the control signal generator and the microprocessor, and further receives a signal from the microprocessor and outputs a control signal to the break memory.

[Effect]

In the microprocessor development support device configured as described above, the address output to the target system during break is performed by the user from the target system to the READY button.
A signal response can be assigned to any configurable specific fixed address or specific range address, and the READY input of the microprocessor is always provided with a means to be assigned to the target system. During a break, a specific fixed address or a specific range of addresses set by the user is output to the target system, so R
The EADY signal always originates from the target system.

Since the microprocessor development support device detects only the READY signal of the target system as the READY signal, the control signals such as memory read signals generated by the target system can be synchronized with the control signals of the microprocessor development support device.

〔Example〕

DESCRIPTION OF THE PREFERRED EMBODIMENTS A debugging microprocessor according to a first embodiment of the present invention will be described below with reference to the accompanying drawings.

FIG. 1 is a block diagram of a first embodiment of a microprocessor development support device according to the present invention.

The basic configuration and operation are the same as the conventional microprocessor development support device shown in FIG.

In the microprocessor development support device shown in FIG. 1, address 8 of microprocessor 1 is address buffer 6
and the break memory 3, and the target address 9 output from the address buffer 6 is wire-ORed for each signal corresponding to the output of the fixed address buffer 7 and output to the target system. The fixed address buffer 7 can specify high or low input signals for each bit of all addresses using a switch 10. This designation of high and low may be performed by a configuration in which the designated address can be latched by software instead of using a switch.

On the other hand, the B/R signal 14 output from the controller 2 is not only connected to the data buffer 5 via the break memory 3 and the inverter, but also connected to the fixed address buffer 7.
It is also connected to the address buffer 6 via an inverter. Address buffer 6 and fixed address buffer 7 are both active when the B/R signal 14 is at high level, so address buffer 6 is active during emulation, and fixed address buffer 7 is active during break.
becomes active. Controller 4 is always TREAD
Attach only Yl8 to MREADY20 as shown in Figure 3.
and READY selector 21 that selects TREADYl 8.
is no longer needed.

That is, the main difference between the microprocessor development support device shown in FIG. 1 and the microprocessor development support device shown in FIG. address will now be output to the target system.
Another point is that the MREADY 20 created by the microprocessor development support device itself shown in FIG. 3 is deleted, and the microprocessor 1 of the microprocessor development support device is operated only with the TREADY1 8 created on the target system.

The microprocessor development support device configured as described above operates as follows.

While the microprocessor 1 is emulating, the controller 2 is outputting at a low level.

Therefore, the target system has microprocessor 1.
address 8, BCY signal 15 and R/W signal 16 are outputted via respective buffers. The target system reads the MEMR signal 22 (reads,
There are various operations such as writing, but here, it will be explained as a memory read signal MEMR. ) etc., and TR
The target data 12 along with EADYl8 is output to the microprocessor development support device. The microprocessor 1 uses this TREADYl8 as REA via a buffer.
DY17 and target data 12 are received and data 11 is received via the buffer, this bus cycle is completed, and the next bus cycle is performed.

During emulation, there are no problems as with the conventional example.

While microprocessor 1 is at break, controller 2
is outputting a high level. Therefore, the value of the switch 10 set by the user is output to the target system via the fixed address buffer 7. B.C.
The Y signal 15 and R/W signal 16 are also output via their respective buffers. As already explained, the target system is MEMR22 created based on these signals.
Accordingly, TREADYl 8 and target data 12 are output. Since the target address 9 output to the target system is always set to the address at which TREADYl8 is outputted to the microprocessor development support device, TREADYl8 is always inputted to the controller 4 and microprocessor 1 via the buffer. Ru.

That is, when microprocessor 1 accesses break memory 3, TREADYl of the target system is
8 is used, so that the microprocessor 1 and the target system will not be out of synchronization. Of course, the break memory 3 needs to be a memory that can be accessed even when the weight is 0. Furthermore, since the address input by TREADY18 to the microprocessor development support device is always output to the target system during a break, the operation of the microprocessor 1 does not stop.

FIG. 2 is a block diagram of a second embodiment of the microprocessor development support device according to the present invention.

The basic configuration and operation are the same as the microprocessor development support device shown in FIG.

The address 8 of the microprocessor 1 shown in FIG.
The address output from address buffer 6' to the target is output to the target system (the number of upper and lower bits can be determined according to the functions of the microprocessor), and is output to the target system as is, at target address 9'. becomes. The address output from address buffer 6'' to the target is wire-ORed with the address output from fixed address buffer 7, resulting in target address 9''. Address buffer 6' is always active, address buffer 6'' is active during emulation, and fixed address buffer 7 is active during break. This is the set address, and the user sets the upper end of the address range using the switch 10 so that TREADYl8 is always generated from the target system.

During emulation, the address buffer 6'' is active, so the address 8 of the microprocessor 1 is directly output to the target system via the address buffer 6' and the address buffer 6''. If you use this configuration during a break, the target system will be
Only the target address 9' is output as the address of the microprocessor 1, but the value set by the switch 10 is output on the target address 9''.In other words, even during a break, the microprocessor is 1 address 8 can be output to the target system. This indicates that if the microprocessor 1 has a refresh function and the function described in the present invention, it can provide a refresh function to the target system even during a break. ing.

The microprocessor development support device configured as described above can output the microprocessor address directly below the address output to the target system during a break, so it can be used as a microprocessor development support device for microprocessors with a refresh function. can also be easily realized.

〔Effect of the invention〕

As explained above, the address to be output to the target system during a break in the microprocessor development support device can be specified as a specific fixed address or a specific range of addresses that always receive a READY signal response from the target system, and RE to be input
By always specifying the ADY signal to the target system, it is possible to solve the problem of the microprocessor and the target system being out of synchronization during a break.

Furthermore, since the READY signal is fixed only from the target system, there is also the effect that the READY selection signal is unnecessary.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a first embodiment of the present invention, FIG. 2 is a block diagram of a second embodiment of the present invention, and FIG.
The figure is a block diagram of a conventional microprocessor development support device, and FIG. 4 is a timing diagram showing the microprocessor shown in FIG. 3 and control signals generated outside the microprocessor.

Claims (1)

[Claims] a microprocessor that supplies a signal to a control signal generator of the target system to generate a control signal; a break memory that stores a debugging program and receives address signals from the microprocessor; a break/run controller that specifies whether an emulation executes a program or a break that executes the debugging program; a fixed address buffer that specifies at least a part of the address signal to be fixed; and the break/run controller. When emulation is specified, an address consisting of a fixed address specified by the fixed address buffer and a part of the address signal from the microprocessor, or only a fixed address specified by the fixed address buffer is sent to the break/run controller. an address buffer that outputs only the address signal from the microprocessor to the target system when the controller specifies a break; and an address buffer that outputs and inputs only the address signal from the microprocessor to the target system when the break/run controller specifies emulation. A data buffer for inputting and outputting data to and from the target system, and an RE from the target system.
A break memory control signal generator that inputs an ADY signal together with the control signal generator and the microprocessor, and further receives a signal from the microprocessor and outputs a control signal to the break memory. Processor development support equipment.