JPH0543142B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an input/output circuit, and particularly to an input/output circuit used in an I/O port of a microcomputer or the like.

[Conventional technology]

Conventionally, the input/output circuit of a peripheral control I/O port included in a microcomputer or the like has usually had the configuration shown in FIG.

In FIG. 2, 20 is an output data latch;
0 is a register that specifies whether the signal input/output terminal 40 is in an input state (high impedance) or an output state.

In the input/output circuit shown in FIG. 2, the signal applied to the signal input/output terminal 40 is transmitted into the device via this input/output circuit only when the signal input/output terminal 40 is in the input state. Ta.

In recent years, the fields in which microcomputers are applied are rapidly expanding. This is largely due to the development environment for systems using microcomputers, as well as the lower prices of LSIs for microcomputers.

What is important in the development of microcomputer application systems is how efficiently the system can be debugged when software and hardware are intricately intertwined. In particular, if the status of the I/O port of a microcomputer, which is the contact point between hardware and software, can be determined by software, it would be very useful in system debugging.

[Problem that the invention seeks to solve]

The conventional input/output circuit described above can transmit the state of the signal input/output terminal to the microcomputer only when the state of the signal input/output terminal is set to the input state. In other words, when the signal input/output terminal is in the output state, there is a problem in that it is not possible to inform the microcomputer whether the signal input/output terminal is in the expected state.

SUMMARY OF THE INVENTION An object of the present invention is to provide an input/output circuit that allows an electronic device to detect that a logic state that an internal electronic device attempts to output is normally applied to a signal input/output terminal.

[Means for solving problems]

The input/output circuit of the present invention includes an output data latch that is located in an electronic device and temporarily holds a signal from inside the electronic device, and a signal input/output terminal that is in an input state or an output signal of the output data latch. a first selection circuit that specifies whether to set the output state;
a three-state buffer provided between the output data latch and the signal input/output terminal and controlled by the output signal of the first selection circuit; and a second selection circuit that selects an output signal independently of the first selection circuit and inputs the selected output signal into the electronic device.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a logic circuit diagram showing one embodiment of the present invention. Note that the input/output circuit of this embodiment is connected to a microcomputer as an electronic device (not shown) via a data bus and a control signal line.

In FIG. 1, 10 is a mode register that indicates whether this input/output circuit is in an output state or an input state, 20 is an output data latch that temporarily holds data to be output, 30 is a 3-state output buffer, and 40 is a This is a signal input/output terminal.

The operation of the embodiment shown in FIG. 1 will be explained below.

First, in data output control for the signal input/output terminal 40, the register address signal ADR ₁ assigned to the mode register 10 and the write control signal WR are used.
AND circuit 11 performs the logical product with AND circuit 1.
By inputting the output signal from 1 to the mode register 10 as a write clock, the output or input state of the mode register 10 is specified.

This is similar to the procedure for I/O operation commands or memory operation commands that general microcomputers have. In other words, when a microcomputer, a data bus, an address bus, and a read/write signal are connected, the address data of the target data is output on the address bus during the read cycle, and the read signal is turned on within that period. At this time, target data is output onto the data bus, so the data is read out at the timing of the rise of the read signal (in the case of active low). Also, in a write cycle, when the target address data is output on the address bus, the write signal is turned on within that period, and the data that is being output on the data bus at this time is read on the rise of the read signal (active low). Write at the timing of (case). Therefore, in the cycle in which the address bus is decoded to obtain the register address signal ADR ₁ , the data to be written to the mode register 10 already exists on the data bus, so this data is used to write the 3-state buffer 30. Specify the logical value "1" or "0".
In this embodiment, when the mode register 10 has a logical value of "1", the 3-state output buffer 30 becomes high impedance (that is, the signal input/output terminal 40 is in the input state), and when the logical value is "0", the 3-state output buffer 30 is held in the output data latch 20. The data being displayed is output to the signal input/output terminal 40.

Writing data to the output data latch 20 is similar to writing data to the mode register 10.
Address signal assigned to output data latch 20
The AND circuit 21 calculates the logical product of ADR ₂ and the write control signal WR, and writes the data on the data bus to the output data latch 20 using the output from the AND circuit 21 as a write clock.

In this manner, the mode register 10 can determine whether the state of the signal input/output terminal 40 is an output state or an input state.

Next, the data input operation will be explained.

In order to input the data held in the output data latch 20 again to the microcomputer via the data bus, the address signal ADR ₂ and the read control signal RD assigned to the output data latch 20 are input using an input command possessed by the microcomputer. to occur. At this time, the OR circuit 52 and the AND circuit 5
1 controls the 3-state input buffer 50, which outputs data to be input onto the data bus, to the output state. At the same time, the selection gate 53 selects the output of the output data buffer 20 as the data input to the 3-state input buffer 50.

In order to input the data on the signal input/output terminal 40 to the microcomputer, the address signal ADR ₃ assigned to the signal input/output terminal 40 and the read control signal RD are used.
This is executed by generating . At this time, the selection gate 53 selects the data on the signal input/output terminal 40 as the data to be applied to the 3-state input buffer 50.

As explained above, the input and output states of the signal input/output terminal 40 are determined by the mode register 10, and which data is input into the microcomputer at the time of input is determined using the respective address signals ADR ₂ and ADR ₃ . , can be independently selected by the second selection circuit.

〔Effect of the invention〕

As explained above, the input/output circuit of the present invention includes a first selection circuit that specifies whether the state of the signal input/output terminal is to be an input state or an output state, and a first selection circuit that specifies whether the state of the signal input/output terminal is to be an input state or an output state; By providing a second selection circuit that selects and inputs output data, it becomes possible to input both the data to be output and the data actually appearing at the signal input/output terminal into the electronic device. Therefore, there is an effect that the electronic device itself can determine whether the state of the signal input/output terminal is normal or not.

[Brief explanation of the drawing]

Figure 1 is a logic circuit diagram of one embodiment of the present invention, Figure 2 is a logic circuit diagram of an embodiment of the present invention.
The figure is a logic circuit diagram of an example of a conventional input/output circuit. 10...Mode register, 11...AND circuit,
20...Output data latch, 21...AND circuit,
30...3-state output buffer, 40...signal input/output terminal, 50...3-state input buffer,
51...AND circuit, 52...OR circuit, 53...
selection gate.

Claims (1)

[Claims] 1 Specify whether the output data latch in the electronic device temporarily holds the signal from inside the electronic device and the signal input/output terminal should be in the input state or the output state of the output signal of the output data latch. a first selection circuit, a three-state buffer provided between the output data latch and the signal input/output terminal and controlled by the output signal of the first selection circuit; signal or the output signal of the output data latch.
An input/output circuit comprising: a second selection circuit that selects and supplies the selected signal to the electronic device independently of the selection circuit.