JPS62235670A - Inputting and outputting circuit - Google Patents

Abstract

PURPOSE:To decide a state of a signal input/output terminal by an electronic device itself, by inputting a data to be outputted and a data which appears actually in the signal input/output terminal, into the electronic device through the first and the second selecting circuit, respectively. CONSTITUTION:In case of a data output control to a signal input/output terminal 40, AND of a register address number ADR1 which is allocated to a mode register 10, and a write control signal WR is taken by an AND circuit 11, and an output signal of the AND circuit 11 is inputted as a write clock to the mode register 10. Whether a state of the signal input/output terminal 40 is an output state or an input state can be determined by the mode register 10. At the time of input, which data is to be inputted into a microcomputer is selected by a selecting gate 53 by using the respective address numbers ADR2 and ADR3.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an input/output circuit, and particularly to an input/output circuit used in an I10 port of a microcomputer or the like.

[Conventional technology]

Conventionally, the input/output circuit of a peripheral control I10 port included in a micro combinator or the like has usually had the configuration shown in FIG.

In Fig. 2, 20 is the output data latch, and 10 is the input state of the signal input/output terminal 40 (high impedance).
This is a register that specifies whether to set the output state or output state.

In the input/output circuit shown in FIG. 2, the signal applied to the signal input/output terminal 40 is transmitted into the device via this input/output circuit only when the signal input/output terminal 40 is in the input state. Ta.

In recent years, the fields in which microcomputers are applied are rapidly expanding. This is LS for microcomputer.
In addition to lowering the price of I, much depends on the development environment for systems using microcomputers.

What is important in the development of a micro combinatorial application system is how efficiently the system can be depacked in a state where software and hardware are intricately intertwined. Special K: If the status of the microcomputer's 10 ports, which are the interface between hardware and software, can be determined by software, it will be very useful in system depacking.

[Problem that the invention seeks to solve]

The conventional input/output circuit described above can transmit the state of the signal input/output terminal to the microcomputer only when the state of the signal input/output terminal is set to the input state.

In other words, when the signal input/output terminal is in the output state, there is a problem in that it is not possible to transmit to the micro combinator whether the signal input/output terminal is in the expected state.

SUMMARY OF THE INVENTION An object of the present invention is to provide an input/output circuit that allows an electronic device to detect that the logic state that the internal electronic device attempts to output is normally applied to a signal input/output terminal.

[Failure to solve the problem]

The input/output circuit of the present invention includes an output data latch that is located in an electronic device and temporarily holds a signal from inside the electronic device, and a state of a signal input/output terminal as an input state or an output of the output data latch. a first selection circuit that specifies whether to output the signal; and a first selection circuit that selects either the signal on the signal input/output terminal or the output signal of the output data latch independently of the first selection circuit; and a second selection circuit for input into the electronic device.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a logic circuit diagram showing one embodiment of the present invention. The input/output circuit of this embodiment is connected to a microcomputer as an electronic device (not shown) via a data bus and a control signal line.

In FIG. 1, 10 is a mode register that indicates whether this input/output circuit is in an output state or an input state;
is an output data latch that temporarily holds the data to be output,
30 is a 3-state output buffer, and 40 is a signal input/output terminal.

The operation of the embodiment shown in FIG. 1 will be explained below.

First, in data output control for the signal input/output terminal 40, the logical product of the register address signal ADH1 assigned to the mode register IOK and the write control signal WR is ANDed.
When the output signal from the AND circuit 11 is input to the mode register 10 as a write clock, the mode register IOK output or input state is designated by K.

This is similar to the procedure of the I10 operation instruction or memory operation instruction that general micro combinators have. In this embodiment, when the mode register 10 has a logical value of "1", the 3-state output buffer (9) has a high impedance (
That is, the signal input/output terminal 40 is in an input state), and the data held in the output data latch 20 is output to the signal input/output terminal 40 when the logic value rOJ is reached.

Writing data to the output data latch 20 is similar to writing data to the mode register IO.

Address signal ADH assigned to output data latch 20,
AND the write control signal WR and the AND circuit 21, and the data on the data bus is written into the output data latch 20 using the output from the AND circuit 21 as a write clock.

In this manner, the mode register 10 can determine whether the state of the signal input/output terminal 40 is an output state or an input state.

Next, the data input operation will be explained.

In order to input the data held in the output data latch 20 to the microcomputer via the data bus again, address signals ADH and ADH assigned to the output data latch 20 are used using an input command possessed by the microcomputer. A read control signal RD is generated. At this time, OR circuit 5
2 and the AND circuit 51 to control the 3-state input buffer 50, which outputs the data to be input onto the data bus, to the output state. At the same time, the output of the output data buffer 20 is selected as the data to be input to the 3-stage buffer 50 using the selector 53.

Inputting data on the signal input/output terminal 40 to the microcomputer is executed by generating address signals ADH and read control signal RD assigned to the signal input/output terminal 40. At this time, the selection gate 53 selects the data on the signal input/output terminal 40 as the data to be applied to the 3-state input cover 7a 50.

As explained above, the input and output states of the signal input/output terminal 40 are determined by the mode register IOK, and which data is input into the microcombiator at the time of input is determined using the respective address signals ADR and ADRs. Well, second
can be selected independently by the selection circuit.

〔Effect of the invention〕

As explained above, the input/output circuit of the present invention includes a first selection circuit that specifies whether the state of the No. 18 input/output terminal is to be a manual state or an output state, and a first selection circuit that specifies whether the state of the input/output terminal No. By providing a second selection circuit that selects and inputs the output data of the data latch, both the data to be output and the data actually appearing at the signal input/output terminal can be input into the electronic device. This has the effect that the electronic device itself can determine whether the state of the signal input/output terminal is normal or not.

[Brief explanation of drawings]

tJfJ1 is a logic circuit diagram of an embodiment of the present invention, and FIG. 2 is a logic circuit diagram of an example of a conventional input/output circuit. 10...Mode register, 11...A
ND circuit, 20... Output data latch, 21.
...AND circuit, 30...3-state output buffer, 40...signal input/output terminal, 50...
...3rd stage Kabuffa, 51...
AND circuit, 52...OR circuit, 53...
...Selection gate. Agent Patent Attorney Susumu Uchihara
・

Claims (1)

[Claims] An output data latch that is located in an electronic device and temporarily holds a signal from inside the electronic device, and a signal input/output terminal that determines whether the state is an input state or an output state of an output signal of the output data latch. a first selection circuit to specify, and a second selection circuit to select either a signal on the signal input/output terminal or an output signal of the output data latch independently of the first selection circuit and input it into the electronic device. An input/output circuit comprising: a selection circuit;