JPH06195474A - Program counter and program counter value change controller - Google Patents

Abstract

PURPOSE:To make it possible to effectively change the flow of the instruction execution of a CPU from the outside of the CPU. CONSTITUTION:The PC register 12 of a program counter 10 holds an address value used for the address designation when a program instruction is read. A PC output buffer 18 outputs the address value of the PC register 12 to an address bus BA when 'without change' is inputted from a PC value change signal SPC. When 'with change' is inputted, the output to the address bus BA becomes a high impedance state. An adder 22 performs an increment not for the address value that the PC register 12 outputs and but for the address value to be inputted from the address BA in the case of 'with change' and writes this result in the PC register 12.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a central processing unit (CPU) which outputs and addresses an address value to a predetermined address bus in order to sequentially read program instructions stored in a memory into a predetermined data bus. )
Related to a program counter used for
In order to further increase the degree of freedom in designing a system using U, the flow of instruction execution of the CPU can be changed more effectively from outside the CPU, and the program counter is set to the program counter. The present invention relates to a program counter value changing controller that changes the program counter value.

[0002]

2. Description of the Related Art Integrating an electronic device into an integrated circuit has many advantages such as miniaturization of the entire device, improvement of reliability and reduction of power consumption. In addition, there are various designing methods for forming an integrated circuit. For example, various design methods are known for reducing the design man-hours and design costs associated with the design of integrated circuits. For example, there is a technique in which at least a part of the design process or the manufacturing process is shared and prepared in advance, and the other processes are customized.

An integrated circuit based on such a technique is called a semi-custom type integrated circuit, and includes a standard cell type integrated circuit, a gate array type integrated circuit, and the like.
The standard cell type integrated circuit is an integrated circuit based on a design method in which registered cells (functional blocks) are arranged and interconnected according to a circuit to be incorporated in the integrated circuit. The gate array type integrated circuit is an integrated circuit of a type in which a group of cells arranged in a matrix which is processed before the wiring process is made common and the subsequent wiring process is performed according to a circuit incorporated in the integrated circuit. . According to such a semi-custom type integrated circuit, it is possible to reduce the TAT (turn around time) and the cost at the time of design and production, and it is possible to provide an integrated circuit designed according to the customer. it can.

In recent years, in such a semi-custom type integrated circuit, a CPU, a RAM (random access memory) accessed by the CPU, and a ROM (re
memory such as ad only memory) and I / O (input / outp
ut) and other peripheral circuit macro libraries are provided. According to the semi-custom type integrated circuit in which such a macro library is prepared, it is possible to provide an integrated circuit in which a microcomputer system having a customized configuration including a CPU is incorporated in one.

A general CPU has an AL as a main configuration.
U (arithmetic logical unit) and various registers,
Also, a control circuit for controlling the overall timing is provided. The register includes, for example, a program counter as well as an accumulator and a general-purpose register used for the arithmetic operation in the ALU.

The widely used computer architecture today is the so-called Neumann computer. The Neumann type computer sequentially executes program instructions stored in advance in a memory.
The program instructions are usually stored in the main memory together with the data handled by them. Further, a series of programs including the program instructions is generally called a stored program (hereinafter, simply referred to as a program).

The general Neumann computer is
To efficiently execute the program sequentially,
It has a register called a program counter. The program counter outputs the address value stored in the program counter to a predetermined address bus in order to sequentially read the program instructions stored in the memory in advance to a predetermined data bus. Also, the characteristic of the program counter is 1
When one program instruction is read and executed, it has a function of incrementing the address value stored in the program counter (increasing the value by "1").

Further, when the CPU having the program counter executes, for example, a jump instruction or the like, the program counter writes the address value stored in the program counter to an address of a jump destination according to the jump instruction. It can be replaced.
In the interrupt control function of the computer, when an interrupt occurs, first, the address value stored in the program counter is saved in, for example, a stack area on the main storage device. Thereafter, an address value indicating the address where the interrupt processing program is stored is written in the program counter.

Further, a general computer is usually a CP
A predetermined system bus is used when the U accesses various peripheral devices such as a main storage device and an input / output device. According to such a system bus, it is possible to share the program command and data transmission paths in the computer, and to unify the interfaces of the peripheral devices in the computer. Furthermore, with such a system bus, the scale of the interface unit occupying the entire computer hardware can be reduced.

Various techniques have heretofore been disclosed in order to further enhance the degree of freedom in designing a system using a CPU.

For example, in Japanese Patent Laid-Open No. 62-10735, C
A technique is disclosed in which an access unit independent of the internal control storage of the PU is added to the external storage device. According to the Japanese Patent Laid-Open No. 62-10735, the operating speed of the CPU can be improved.

Further, in Japanese Patent Laid-Open No. 64-66900, a memory provided inside a CPU or the like connected to a corresponding internal bus in a normal operation mode is used as a test bus in a predetermined test mode. The technique of connecting to is disclosed. In recent years, the number of memories such as registers incorporated in a CPU tends to increase. JP-A-64-6
According to the 6900, it is possible to efficiently test the functions and performances of a large number of memories in the CPU, for example.

Further, Japanese Patent Laid-Open No. 2-90323 discloses a technique relating to an indirect register access system for indirectly specifying and reading the contents of internal registers of a computer system. This technique reads data from a corresponding indirect register inside a processor through a first multiplexer,
An indirect access register for storing an address is provided.
Also, the read data is sent to the internal bus via the second multiplexer, and the MI for storing the address etc.
An R register is provided. An external bus control unit for storing the address, which sends the data sent to the internal bus to the external bus via the third multiplexer, is provided. Predetermined address information is set in the indirect access register, the MIR register, and the external bus control unit, and the contents of an arbitrary indirect register inside the processor are sent to the internal bus or external bus of the processor. According to the Japanese Patent Laid-Open No. 2-90323, one indirect access register can also be used as the indirect access register so that the contents of an arbitrary register in the computer system can be read in or out of the computer system. The amount of wear can be reduced.

[0014]

However, as described above, in spite of the disclosure of various techniques relating to the architecture of a system using a CPU, C
No effective system is disclosed for a system using a CPU, which can change the flow of instruction execution of a PU more effectively from outside the CPU.

For example, there is a method in which the CPU executes a jump instruction or the like to change the flow of instruction execution.
That is, the flow of instruction execution is changed to the branch destination address designated by the jump instruction. However, such a method of changing the instruction execution flow of the CPU by software requires a large number of so-called machine cycles until the instruction execution flow of the CPU is actually changed.

Further, the flow of instruction execution can be changed by using the interrupt control function of the CPU as described above. However, even in this case, a plurality of machine cycles are required before the flow of instruction execution is changed. Further, for example, the number of hardware interrupt inputs is limited, and in this respect, there is a limit in system construction using a CPU. That is, the function of the CPU is limited.

The present invention has been made to solve the above-mentioned conventional problems, and in order to increase the degree of freedom in designing a system using a CPU, the flow of instruction execution of the CPU is A program counter used for CPU, which can be changed more effectively from the outside.
Another object of the present invention is to provide a program counter value changing controller for changing the address value stored in the program counter.

[0018]

A program counter according to the first invention of the present application outputs an address value to a predetermined address bus to sequentially read program instructions stored in a memory in advance to a predetermined data bus. In the designated program counter, when “no change” is input from the program counter register holding the address value and the PC value change signal input from the outside of the program counter, the value is held in the program counter register. A program counter output buffer that outputs the address value that is present to the address bus, and when "changed" is input from the PC value change signal, the output to the address bus is in a high impedance state. , When the address is specified, output to the address bus By adding the value "1" to the address value being read and adding the value "1" to the address value, and writing the result of the addition to the program counter register by the next address designation, The above object has been achieved.

In the program counter value changing controller of the second invention of the present application, the central processing unit having the program counter whose program counter value is to be changed monitors signals input to and output from the system bus.
Detects the timing to start changing the program counter value,
A PC value change signal generation circuit for transmitting "changed" to the program counter with a predetermined PC value change signal;
An address value output timing detection circuit for detecting an unused state of an address bus of the system bus;
“Changing” is transmitted by the C value change signal, and an address value output circuit that outputs an address value related to the program counter value change to the address bus when the unused state is detected is provided. Thus, the above-mentioned problems are achieved.

[0020]

According to the present invention, in order to increase the degree of freedom in designing a system using a CPU, first, the flow of instruction execution of the CPU can be changed more effectively from outside the CPU. This was made paying attention to one of the important points.

Therefore, the first aspect of the present invention relates to the configuration of the program counter used in the CPU. That is, by changing the address value stored in the program counter, the flow of instruction execution of the CPU can be externally changed, which is a more effective configuration.

On the other hand, the second invention relates to a configuration of a program counter value changing controller for changing the address value of the program counter of the first invention.

FIG. 1 is a block diagram showing the gist of the first invention.

FIG. 1 shows the structure of the program counter 10 relating to the first aspect of the present invention, which can be used in various CPUs. The program counter 10 outputs an address value to a predetermined address bus BA and addresses it in order to sequentially read out program instructions stored in a memory accessed by the CPU to a predetermined data bus. . The program counter 10 mainly includes a program counter register (hereinafter, simply referred to as a PC register) 12,
It is composed of a program counter output buffer (hereinafter simply referred to as a PC output buffer) 18 and an adder 22.

The PC register 12 holds an address value as described above, which is used for addressing when a desired program instruction is accessed via a predetermined data bus. When the address value to be held has a bit width of, for example, n bits, the PC register 12 can store the address value. For example, it is composed of a total of n so-called D-type flip-flops.

The PC output buffer 18 is a tristate output buffer. The PC output buffer 18
Is valid / invalid of its output according to the PC value change signal SPC.
An invalid selection is made. That is, the PC value change signal SP
When “No change” is input from C, the PC
The address value held in the register 12 is output to the address bus BA. On the other hand, in the PC output buffer 18, when "changed" is input from the PC value change signal SPC, the output to the address bus is in a high impedance state.

When the address value held in the PC register 12 has a bit width of n bits, the PC counter output buffer 18 can be composed of, for example, a total of n tri-state output logic gates.
For example, it can be composed of n tri-state output buffers.

The PC output buffer 1 shown in FIG.
In the logic circuit diagram 8, the input of the PC value change signal SPC is a negative logic input for selecting valid / invalid of its output. However, the present invention is not limited to this. That is, it suffices that the output to the address bus BA becomes a high impedance state when “changed” is input from the PC value change signal SPC. That is, the valid / invalid P
The logic of the input of the C counter output buffer 18 is the PC
It depends on whether the value change signal SPC is a positive logic signal or a negative logic signal. For example, when the PC value change signal SPC is “no change”, “1 (H
State) ”, the PC counter output buffer 1 for selecting the valid / invalid of the PC output buffer 18
Input 8 is a positive logic input.

The adder 22 is used to realize the function of incrementing the address value of the program counter. That is, when the predetermined program instruction is addressed by the program counter and the program instruction is executed by the predetermined CPU, the PC register 1
It is for incrementing the address value held in 2. The adder 22 reads the address value output to the address bus BA at the time of addressing, increments the address value, and then outputs this result to the PC by the next addressing.
The data is written in the register 12.

As a feature of the present invention, the adder 22 is
The address value to be incremented is read from the address bus BA. That is, the P
The data is read from the output side of the C output buffer 18.

Therefore, when "no change" is input from the PC value change signal SPC, the address value output from the PC register 12 via the PC output buffer 18 is read into the adder 22. Be done.

On the other hand, when "changed" is input from the PC value change signal SPC, something different from the address value held in the PC register 12 is output to the address bus BA. Is read into the adder 22. When "changed" is input, the output of the PC output buffer 18 is in a high impedance state, and the address value held by the PC register 12 is not output. When the "changed" is input, for example, the address value output to the address bus BA by the program counter value change controller according to the second invention described later in detail with reference to FIG. 22 is read.

As described above, according to the program counter of the first aspect of the present invention, while "changed" is input from the outside of the program counter by the PC value change signal SPC, the program value is changed through the address bus BA or , It is possible to write a desired address value to the PC register 12 via the adder 22. By writing a desired address value to the PC register 12, the flow of instruction execution of the CPU using the program counter can be changed from outside the CPU. Therefore,
According to the present invention, it is possible to further increase the degree of freedom in designing a system using a CPU.

FIG. 2 is a block diagram showing the gist of the program counter value changing controller of the second invention.

The program counter value changing controller (hereinafter, simply referred to as PC value changing controller) shown in FIG. 2 uses the address value held in the PC register 12 in the program counter of the first invention. To change. That is, the PC value change controller monitors the signals of the predetermined data bus, the predetermined address bus BA, and the system bus 3 including various control signal lines, and the PC value change signal SPC referred to with reference to FIG. Is output while changing the address value of the program counter, the desired address value to be written to the PC register 12 is output.

As shown in FIG. 2, the PC value change controller mainly comprises a PC value change signal generation circuit 6
2, an address value output timing detection circuit 64, and an address value output circuit 66.

The PC value change signal generating circuit 62 is input and output by a program counter whose program counter value is to be changed, that is, a CPU having a program counter to which the first invention is applied. Monitor the signal on bus 3. With such monitoring,
The change start timing of the program counter value is detected according to the operating state of the CPU. Further, when such a change start timing is detected, the PC value change signal generation circuit 62 transmits "changed" to the program counter by a predetermined PC value change signal SPC.

The PC value change signal SPC is the same as that described with reference to FIG. Also, the PC value change signal S
The PC may be configured as one signal in the system bus 3. Alternatively, the PC value change signal SPC may be a signal directly input from the PC value change controller to the program counter to which the first invention is applied.

The present invention does not limit the specific detection method of the PC value change signal generating circuit 62 for detecting the change start timing of the program counter value as described above. The method of detecting the change start timing is determined according to the content of the signal of the system bus 3 which is different for each computer system.

For example, the PC value change signal generation circuit 62.
May detect the start of the output of the address value from the program counter to detect the change start timing. For example, when the program counter outputs its program value in synchronization with the system clock in the system bus 3, the output start timing of the address value of the program counter is in the system bus 3. It can be detected by the system clock signal.

Alternatively, an address value output signal from the program counter to the system bus 3 is output by an address output enable signal output from the program counter or a CPU including the program counter included in the system bus 3. May be detected to detect the change start timing.

Address value output timing detection circuit 6
Reference numeral 4 is for detecting an unused state of the address bus included in the system bus 3. The PC value change controller including the address value output timing detection circuit 64 outputs the normal address value to the program counter to which the program counter to which the first aspect of the invention is applied transmits the address value to be rewritten. Use the address bus used for. Therefore, the signal of the address value that the program counter outputs to the address bus and the signal of the address value for rewriting that the PC value change controller outputs to the same address bus are:
There must be no collision on the address bus. The address value output timing detection circuit 64 prevents such a signal collision on the address bus.

When a request for changing the PC value is made for some reason, the PC value change signal generating circuit 62 indicates "changed" in the PC change signal SPC as described above. Communicate to the program counter. Also, by inputting "changed" to the program counter,
The output of the PC output buffer 18 is set to a high impedance state, and the address bus is set to an unused state.
The address value output timing detection circuit 64 detects such an unused state of the address bus.

The address value output circuit 66 uses the PC
From the value change signal generation circuit 62 to the PC value change signal SPC
Is transmitted, and when the address value output timing detection circuit 64 detects the unused state, the address value related to the program counter value change is output to the address bus. The address value output by the address value output circuit 66 is written to the PC register 12 via the system bus 3 and the adder 22 of the program counter of the first invention. By changing the address value held in the PC register 12, the flow of instruction execution of the CPU having the program counter can be changed.

As described above, according to the PC value changing controller of the present invention, the address value held by the PC register 12 in the program counter of the first invention can be changed. Also, as a result, the first
The flow of instruction execution of the CPU provided with the program counter of the invention can be changed.

The present invention is not specifically limited to the use form of the PC value change controller of the present invention.
For example, the present invention does not specifically limit in what form the PC value change request is made, what kind of address value is changed, and where to obtain the change destination address value. Absent.

For example, the PC value changing controller of the present invention can also be used to configure an automatic reset circuit when power is turned on. In this case, a PC value change request is first issued to the PC value change signal generation circuit 62 when power is turned on. Further, as the change destination address value output from the address value output circuit 66, a value according to the head address of the program for performing the reset process is output.

Further, for example, the PC value changing controller of the present invention can configure or expand the interrupt control function of the CPU. In this case, when any interrupt request is made, this is used as the above-mentioned PC value change request to the PC value change signal generating circuit 62. Further, when realizing the interrupt control function in this way, the address value of the change destination output from the address value output circuit 66 is a value according to the start address of the interrupt processing program corresponding to the input interrupt request. Become.

[0049]

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 3 is a block diagram showing the configuration of a computer system of an embodiment to which the first invention and the second invention are applied.

As shown in FIG. 3, the computer system is mainly composed of a CPU 1, a PC value change controller 40, a memory 62, an I / O 64, and a system bus 3 connecting them. .
Further, the CPU 1 is mainly composed of the program counter 1
0, the timing control circuit 32, and the instruction decoder 34
And an instruction register 36 and an ALU 38. In the computer system having such a configuration, the first invention is applied to the program counter 10. Also, the PC value change controller 40
In, the second invention is applied.

First, in the CPU 1, the program instructions stored in the memory 62 in advance are sequentially executed one by one. First, the program counter 10 sequentially outputs an address value to a predetermined address bus BA forming the system bus 3 so that a predetermined data bus BD forming the system bus 3 is passed. The instruction register 3
It is to read in 6. Further, the instruction content of the program instruction read into the instruction register 36 is judged by the instruction decoder 34. Also, depending on the contents of the program command, the A
LU38 is used. In addition, various operations of the CPU 1 including such operations are performed by the timing control circuit 3
It is controlled by 2.

On the other hand, with respect to the PC value change controller 40, a total of four hardware interrupt request signals CHa to be inputted from the outside of the computer system concerned.
CHd is entered. The PC value change controller 4
For 0, each address value is stored for each of the interrupt request signals CHa to CHd. The P
The C value change controller 40 changes the address value held in the program counter 10 according to the address value stored for each of the interrupt request signals CHa to CHd.

FIG. 4 is a block diagram showing the configuration of the program counter 10 of the embodiment.

As shown in FIG. 4, the program counter 10 mainly includes a PC register 12 and a PC register.
It is composed of an output buffer 18 and an adder 22.
Further, the program counter 10 is composed of an input side multiplexer 14, an output side multiplexer 16 and a program counter input buffer (hereinafter, simply referred to as a PC input buffer) 20. The PC register 12, the PC output buffer 18, and the adder 2
2 is the same as that described above with reference to FIG.

The input multiplexer 14 receives the address input A1 or the adder 2 according to the input selection signal SI.
One of the two outputs is selected and the PC register 1
Output to 2. In the input side multiplexer 14, when the input selection signal SI is "1", the address input A1 is selected to the PC register 12. On the other hand, when the input selection signal SI is "0", the output of the adder 22 is selected to the PC register 12.

In the input side multiplexer 14, "0" is normally input to the input selection signal SI, and the address value held in the PC register 12 is changed every time the CPU 1 executes a program instruction. It should be incremented sequentially. On the other hand, when the instruction decoder 34 determines, for example, a jump instruction or the like, "1" is input to the input selection signal SI, and a value according to the branch destination address is output from the address input A1. It is written to the PC register 12.

The output side multiplexer 16 selects either the address input A2 or the output of the PC register 12 according to the output selection signal SO and outputs it to the PC output buffer 18. In the output side multiplexer 16, when the output selection signal SO becomes "1", the address input A2 is selected to the PC output buffer 18. On the other hand, when the output selection signal SO becomes "0", the output of the PC register 12 is selected to the PC output buffer 18.

In the output side multiplexer 16, "0" is usually input from the output selection signal SO, and the address value held in the PC register 12 is the CP value.
Each time the program instruction of U1 is executed, it is sequentially incremented. On the other hand, when the instruction determined by the instruction decoder 34 is to access and handle data at a predetermined address, the output selection signal is used to address the data to be processed (not the program instruction itself). SO becomes "1". Further, when the output selection signal SO becomes "1", a predetermined address value for addressing is given as the address input A2.
It is input to the output side multiplexer 16. At this time, the address value by the address input A2 is
The data is output to the address bus BA via the output buffer 18.

The PC input buffer 20 is used as an input buffer when the adder 22 reads an address value from the address bus BA. The PC input buffer 20 is composed of a total of n buffer gates according to the bit width n of the address value to be read.

In the program counter 10 having such a configuration, when the input selection signal SI becomes "0" and the output selection signal SO becomes "0", the program counter shown in FIG.
To operate in the same manner as described above.
At this time, as described above, while inputting the PC value change signal SPC, the PC register is passed through the address bus BA, the PC input buffer 20, the adder 22 and the input side multiplexer 14. The address value held in 12 can be changed. As a result, the flow of instruction execution of the CPU 1 is
Can be changed externally.

FIG. 5 is a block diagram showing the configuration of the PC value change controller 40 used in the above embodiment.

As shown in FIG. 5, the PC value change controller 40 shown in FIG. 3 is mainly composed of a timing circuit 42, a multiplexer 44, and a total of four address registers 46a to 46d. ing. Further, the timing circuit 42 receives the system clock Φ and the read / write selection signal R / W from the system bus 3. Further, the timing circuit 42
Inputs the external input signals CHa to CHd. The timing circuit 42 also outputs a PC value change signal SPC to the system bus 3. The timing circuit 42
Is sent to the multiplexer 44 by the address selection signal S
Output EL.

In the timing circuit 42 as described above, the PC value change signal generating circuit of the first invention,
Similarly, the address value output timing detection circuit of the first aspect of the invention is configured.

The PC value change signal generating circuit constituted by the timing circuit 42 is operated by the external input signal CHa.
Input of ~ CHd is a PC value change request. Also, the PC
When a value change request is made, the system clock Φ and the read / write selection signal R / W are used to monitor the operating state of the CPU 1 to detect the change start timing of the program counter value, and the PC value change signal SP
At “C”, “changed” is transmitted to the program counter 10 provided in the CPU 1.

The address value output timing detection circuit provided in the timing circuit 42 detects the unused state of the address bus of the system bus 3 at the system clock Φ.

One address value is stored in advance in each of the address registers 46a to 46d corresponding to each of the external input signals CHa to CHd.
When an interrupt request signal is input from any one of the external input signals CHa to CHd, it is held in the program counter 10 provided in the CPU 1 by the address value stored in the address register 46a to 46b corresponding to the interrupt request signal. Change the address value that is set. When an interrupt request signal is input from any one of the external input signals CHa to CHd, the timing circuit 42 causes the multiplexer 44 to select the corresponding address register 46a to 46d.

Further, in the timing circuit 42 and the multiplexer 44, "changed" is transmitted by the PC value change signal SPC in the PC value change signal generation circuit, and in the address value output timing detection circuit. When the unused state of the address bus is detected, the address registers 46a-46d selected as described above are used.
The address value stored in is output to the address bus which constitutes the system bus 3. That is, in the PC value change controller 40 of the present embodiment, the first
The address value output circuit of the invention mainly comprises the address registers 46a to 46d and the multiplexer 4
It is composed of four.

FIG. 6 is a time chart showing the operation of this embodiment.

In the time chart of FIG. 6, the system clock Φ is arranged in order from the top of the time chart.
, The address bus BA, and the PC value change signal SP
C, the address output by the CPU 1 and the address output by the PC value change controller 40 are shown.

The entire computer system of this embodiment is
It operates according to the system clock Φ. The cis
The system clock Φ is a signal with a constant frequency, and
The signal has a duty ratio of 50%. The shi
One cycle of the stem clock Φ is the computer system
Data on the system via the system bus 3
Corresponds to one machine cycle related to delivery, etc.
It has become a thing. In one machine cycle,
Rui or an integer number, in one unit of the system bus 3
Read related program instructions, access data, etc.
Done. Further, in FIG. 6, each machine cycle
Starts at time t₁~ Time t₃, Time t ₇, Time t₈of
It is each time.

In the time chart of FIG. 6,
Without the time t₁In the machine cycle immediately before
The PU address output is the address value A. this
As a result, the address bus BA is also
The response value is A. The time t ₁Next machine starting with
In the cycle, the CPU address output and the address
The address value of Subas BA is (A + 1).
ing. The time t₂Next machine cycle starting from
Then, the CPU address output and the address bus B
The address value of A is (A + 2).

In the time chart of FIG. 6, the external input signal C is added between the time t ₂ and the time t _3.
An interrupt request signal is generated for Ha.

Accordingly, the PC value change signal generation circuit monitors the rise of the system clock Φ in order to detect the change start timing of the program counter value. The PC value change signal generating circuit generates the PC value change signal S after a predetermined time from the rise of the system clock Φ.
The program counter 1 indicates "changed" by the PC.
Transmit to 0.

In order to transmit "changed", the PC value
The change signal SPC is the time t in FIG._FourAt "0"
ing. In addition, the PC value change signal SPC
By "changed", the program counter 10
The PC output buffer 18 has the address bus B
The output to A is in a high impedance state. Therefore,
This time t_FourImmediately after, the CPU address output is invalid
Becomes Also, the time t _FourFrom immediately after the address bus
BA is in an unused state.

Subsequently, the PC value change controller 40
Is the address value output timing detection circuit,
The unused state of the address bus BA included in the system bus 3 is detected. The address value output timing detection circuit detects the time t by the fall of the system clock Φ.
_{At 5} , it is detected that the address bus BA is already unused.

"There is a change" is transmitted by the PC value change signal SPC output from the PC value change signal generation circuit, and the unused state of the address bus BA is notified by the address value output timing detection circuit. When detected, the output of the PC value change controller 40 outputs the address value "B". The address value B corresponds to the above-mentioned interrupt request signal input to the PC value change controller 40. Further, when the output of the PC value change controller 40 becomes the address value B in this way, the address value of the address bus BA also becomes "B".

In this way, when the address value B is output to the address bus BA, the PC register 12 of the program counter 10 stores the address value B in the adder 22 by time t _6. Then, the address value (B + 1) incremented is written.

After that, in the next machine cycle starting from the time t ₇ , both the CPU address output and the address value of the address bus BA become (B + 1). In addition, starting from the time t ₈ In the next machine cycle, the CPU address output and the address bus BA
The address values of all are (B + 2).

As described above, in this embodiment,
It is possible to construct a computer system centering on the CPU 1 using the program counter 10 to which the first invention is applied. Further, in such a computer system, the PC to which the second invention is applied
By the value change controller 40, the external input signal C
According to the interrupt request signal input to Ha to CHd,
The address value held in the program counter 10 can be changed. This makes it possible to change the flow of instruction execution of the CPU 1 when the interrupt request signal as described above is input. As described above, in this embodiment, an additional function provided outside the CPU 1, that is, an interrupt control function can be incorporated, and a more flexible system can be constructed.

FIG. 7 is a block diagram showing an example of the structure of a conventional program counter.

FIG. 7 shows a conventional program counter 10 shown for comparison with the program counter 10 of the embodiment shown in FIG. Compared with the conventional one shown in FIG. 7, in the program counter 10 of the embodiment, the general PC output buffer 18a is the tri-state output buffer type of the PC output buffer 18, and the PC input buffer 20 is further provided.
It is equipped with. Further, the connection on the input side of the adder 22 is changed.

The program counter 10 of this embodiment can be realized by adding a relatively small number of circuit elements as compared with the conventional one. Even with the addition of a relatively small number of circuit elements, according to the program counter 10 of the present embodiment, various functions can be achieved by the controller provided outside the CPU 1 such as the PC value change controller 40. It can be realized, and the degree of freedom in designing a computer system can be further increased.

[0084]

As described above, according to the present invention, C
In order to increase the degree of freedom in designing a system using a PU, the flow of instruction execution of the CPU is
It is possible to obtain an excellent effect that it is possible to provide a program counter and a program counter value changing controller that can be changed more effectively from the outside.

[Brief description of drawings]

FIG. 1 is a block diagram showing a summary of a program counter according to a first invention of the present application.

FIG. 2 is a block diagram showing a summary of a program counter value change controller according to a second invention of the present application.

FIG. 3 is a block diagram showing a configuration of an embodiment of a computer system to which the first invention and the second invention are applied.

FIG. 4 is a block diagram showing a configuration of a program counter used in the CPU of the embodiment.

FIG. 5 is a block diagram showing the configuration of a program counter value change controller used in the above embodiment.

FIG. 6 is a time chart showing the operation of the embodiment.

FIG. 7 is a block diagram showing a configuration of an example of a conventional program counter, which is compared with the program counter of the embodiment.

[Explanation of symbols]

 1 ... CPU (central processing unit) 3 ... System bus 10 ... Program counter 12 ... Program counter register 14 ... Input side multiplexer 16 ... Output side multiplexer 18 ... Program counter output buffer 20 ... Program counter input buffer 22 ... Adder 32 ... Timing Control circuit 34 ... Instruction decoder 36 ... Instruction register 38 ... ALU (arithmetic logic unit) 40 ... PC value change controller 42 ... Timing circuit 44 ... Multiplexer 46a-46d ... Address register 62 ... Memory 64 ... I / O A1, A2 ... Address input SPC ... PC value change signal SI ... Input selection signal SO ... Output selection signal SEL ... Address selection signal CHa to CHd ... External input signal BA ... Address bus R / W ... Read / write selection signal n ... Program counter bit Number

Claims (2)

[Claims] 1. A program counter for outputting and addressing an address value to a predetermined address bus in order to sequentially read program instructions stored in a memory onto a predetermined data bus, wherein the program counter holds the address value. When “no change” is input from the register and a PC value change signal input from the outside of the program counter, the address value held in the program counter register is output to the address bus, On the other hand, the P
When "changed" is input from the C value change signal,
A program counter output buffer whose output to the address bus is in a high impedance state; and, at the time of addressing, after reading the address value output to the address bus and adding the value "1" to the address value, A program counter comprising: an adder for writing the result of the addition to the program counter register by the next address designation. 2. A central processing unit having a program counter whose program counter value is to be changed detects a program counter value change start timing by monitoring a signal input to or output from the system bus, and a predetermined value is detected. PC
A PC value change signal generation circuit for transmitting "changed" to the program counter by a value change signal; an address value output timing detection circuit for detecting an unused state of an address bus of the system bus; An address value output circuit that outputs “changed” by a value change signal and outputs an address value related to the program counter value change to the address bus when the unused state is detected is provided. Characteristic program counter value change controller.