JPS62271028A - Microprocessor - Google Patents

Abstract

PURPOSE:To replace a program with another one by storing the designated frequency value in a memory means, subtracting '1' from the designated frequency value every time a designated address is read out and delivering a mask unable interruption signal when said frequency value is equal to zero. CONSTITUTION:A designated address memory circuit 7A stores the designated frequency value. When the output data received from the circuit 7A is equal to '1', a '1' subtracting circuit 11 subtracts '1' from the designated frequency value and said output data is replaced with the data on a bus 6 by a data switching circuit 12. At the same time, the '1' subtracted value is written to each bit following an MSB of the circuit 7A and stored there. Then a CPU 1 continues execution of a program 4 to be checked. When the data following the MSB of the circuit 7A are equal to zero owing to a '-1' action carried out each read-out of the designated address, this fact is detected by a zero detecting circuit 10. Then this detection signal is delivered to a mask unable interruption signal generating circuit 8A and a mask unable interruption signal 9 is sent to the CPU 1. Thus the execution of the program 4 is stopped and the control is shifted to a monitor program 5.

Description

[Detailed Description of the Invention] 3. Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a microprocessor that has a switching function that switches execution of one program at a required timing when executing another program. It is something.

[Prior Art] Normally, in a microprocessor, in order to check a program called debugging, a debugging program called a monitor program is executed separately from the checked program.

The monitor program performs the initial setting of the checked program and displays the execution results, etc. When the checked programger 11 is executed, the checked programger t1 is stopped at the required timing (when a specified address is accessed), and the checked programger t1 is stopped.
The above monitor program is switched and started.

FIG. 2 is a block diagram showing a schematic configuration of a conventional microprocessor having a program switching function (breakpoint circuit) as described above. In FIG. An address bus that outputs the address of the instruction to be executed; 3 is a program memory that stores instructions; 4 is a part of the contents of the program memory 3; here, a checked program is the object of debugging; 5 is the same a debugging monitor program that forms part of the contents of the program memory 3;
A data bus 6 sends the output data of the program memory 3 to CPTJI, and a data bus 7 is accessed at the same address as the program memory 3.

A designated address memory circuit 8 detects whether or not it is a designated address and stores the presence/absence in a memory, and stops the execution of the checked program 4 based on the output data of the designated address memory circuit 7, that is, the designated address detection signal. C
The non-maskable interrupt signal generating circuit 9 outputs to the PUI, and is a non-maskable interrupt signal line output from the non-maskable interrupt signal generating circuit 8.

Next, the operation will be explained. When debugging the checked program 4, the CPU first causes the CPU to execute the checked program 4. CPU1 uses address bus 2
The address of the next instruction to be read is output to the program memory 3 via the program memory 3, and the instruction of the checked program 4, which is the contents of the address, is output from the program memory 3 to the data bus 6. The CPU then reads the command output to the data bus 6 and executes the command.

At this time, the designated address memory circuit 7 is accessed via the address bus 2 at the same address as the program memory 3, and stores whether or not that address is the designated address. Namely.

If the address is not a designated address, data "0" is simply written and stored in the designated address memory circuit 7, and the execution of the checked program 4 by C and PU1 is continued.

On the other hand, if the address is a designated address, data "1" is written in the designated address memory circuit 7, and this data "1" (designated address detection No. 42) is output to the non-maskable interrupt signal generation circuit 8. Accordingly, the non-maskable interrupt signal generation circuit 8 generates a non-maskable interrupt signal and outputs it to the CPU 1. Therefore, CPUI is 1
After accepting the interrupt and executing the instruction read at that time, execution of the checked program 4 is stopped and control is transferred to the monitor program 5. That is, program switching is performed.

[Problems to be Solved by the Invention] However, since this type of conventional microprocessor is configured as described above, control is immediately transferred to the monitor program 5 when one instruction at a specified address is executed. However, in order to execute an instruction at a specified address a plurality of times, the checked program 4 must be switched and re-executed each time, which is complicated.

This invention was made to solve the above problems, and only when an instruction at a specified address is executed a specified number of times when debugging a program, etc. The object of the present invention is to obtain a microprocessor capable of executing switching to

[Means for Solving the Problems] The microprocessor according to the present invention stores whether or not the address is a designated address by accessing the same address as the program memory, and also stores the desired designated number of times. a storage means; a specified number of times subtraction means for subtracting the specified number of times stored in the storage means each time the specified address is read; A zero detection T' stage for outputting a zero detection signal and a non-maskable interrupt signal generating means for outputting a non-maskable interrupt signal in response to the zero detection signal from the zero detecting means are provided. .

[Function] In this invention, the microprocessor stores a specified number of times in the storage means, and each time a specified address is read, the specified number of times subtraction means subtracts a required number from the specified number of times, and the specified number of times is calculated. Only when the zero detection means detects that the numerical value has become zero, the non-maskable interrupt signal generation means outputs a non-maskable interrupt signal, and when this non-maskable interrupt signal is received, one program can output a non-maskable interrupt signal. Executes switching to the program.

[Embodiment of the Invention] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In the figure, 1 is the CPU that executes the instruction, 2 is the second CPU
3 is a program memory that stores instructions; 4 is a part of the contents of this program memory 3; 5 is a monitor program for debugging as another program that also forms part of the contents of program memory 3;
This is a data bus that sends data to the PUI.

Further, 7A is a designated address memory circuit as a storage means for detecting whether the address is a designated address by being accessed at the same address as the program memory 3, and storing the presence or absence of the designated address, as well as storing a desired designated number of times. , 8
A is a non-maskable interrupt signal generation circuit which receives a zero detection signal from the zero detection circuit 10 and outputs a non-maskable interrupt (No. 3 9 to the CPUI). 9 is a non-maskable interrupt signal generation circuit. This is a non-maskable interrupt signal line output from 8A.

Further, reference numeral 10 denotes zero detection means for detecting when the specified number of times stored in the specified address memory circuit 7A becomes zero and outputting a zero detection signal to the non-maskable interrupt equal signal generation circuit 8A. It is a detection circuit. 11
1 is a 1 subtraction circuit that subtracts 1 from the specified number of times in the specified address memory circuit 7A, and 12 is a data switching circuit for selectively connecting the data bus 6 or the 1 subtraction circuit 11 to the specified address memory circuit 7A. These circuits 11
．． 12 constitutes a designated number of times subtraction means that subtracts the designated number of times value stored in the designated address memory circuit 7A each time a designated address is read out.

Next, the operation will be explained. When debugging the checked program 4, the CPU first causes the CPU to execute the checked program 4. CPU1 uses address bus 2
The address of the next instruction to be read is output to the program memory 3 via the program memory 3, and the instruction of the checked program 4, which is the contents of the address, is output from the program memory 3 to the data bus 6. The CPU then reads the command output to the data bus 6 and executes the command.

At this time, the specified address memory circuit 7A is accessed via the address bus 2 at the same address as the program memory 3, but in this specified address memory circuit 7A, in addition to storing the specified number of times, the specified address memory circuit 7A is also accessed by the CPU. Whether or not the address of the issued instruction is a designated address is stored.

That is, if the above address is not a designated address, simply write data "O" to the MSB (most significant bit) of the data in the designated address memory circuit 7A and store it.
The execution of the checked program 4 by the CPU is continued.

On the other hand, if the address is a designated address, data "1" is written to the MSB of the designated address memory circuit 7A. Then, when the output data from the specified address memory circuit 7A is "1" (when the specified address is read), the 1 subtraction circuit 11 subtracts 1 from the specified number of times, The data switching circuit 12 switches that value (specified number of times value - 1) with the data on the data bus 6, and after writing and storing it in the bits below the MSB of the designated address memory circuit 7A, the CPU 1 executes the checked program 4. continue.

In this way, the program to be checked 4 continues to be executed by the CPU, and each time the specified address is read, it is subtracted by 1. When the data below the MSB of the specified address memory circuit 7A becomes zero, zero is detected. The circuit 10 detects this and outputs a detection signal from the non-maskable interrupt signal generating circuit 8A, and the non-maskable interrupt signal 9 is output from the non-maskable interrupt signal generating circuit 8A.
Output to PUI.

Accordingly, CPtJl accepts the interrupt, executes the instruction that was being read at that time, then stops execution of the checked program 4 and transfers control to the monitor progera tx 5.

In this way, when the checked program 4 is executed at the specified address the specified number of times.

Its execution is stopped, and the monitor program 5 is switched and executed.

In the above embodiment, the program to be stopped at a specified address is the checked programger 11, and the program started by a software interrupt instruction is the monitor program.However, the checked program is the execution program, and the monitor program If you use this as a modification program, you can make a normally running program run as a different program without changing it.

That is, the present invention is widely applicable to real-time program switching of designated addresses.

Further, as the designated number value subtraction means, one may be used which subtracts the designated number of times stored in the storage means by a required number each time a designated address is read out.

[Effects of the Invention] As described above, according to the present invention, the storage means stores the presence or absence of a designated address by being accessed at the same address as the program memory, and also stores the desired designated number of times. and a specified number of times subtraction means that subtracts the specified number of times stored in the storage means each time the specified address is read, and zero detection when the specified number of times becomes zero. Since the configuration includes a zero detection means for outputting a signal and a non-maskable interrupt signal generation means for receiving the zero detection signal from the zero detection means and outputting the non-maskable interrupt signal, it is possible to specify an instruction at a specified address. It has the effect that it can be executed continuously a number of times, and only when it has been executed that number of times can the program being executed be switched to another program.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a schematic configuration of a microprocessor according to an embodiment of the present invention, and FIG. 2 is a block diagram showing a schematic configuration of a conventional microprocessor. In the figure, 1- CPU, 3- program memory,
4 Checked program as one program 11.
5 Monitor program as the other program, 7A
- Specified address memory circuit as storage means, 8A. Non-maskable interrupt signal generation circuit as non-maskable interrupt signal generating means, 9- Non-maskable interrupt signal line, 10
- Zero detection circuit, 11 A 1 subtraction circuit constituting the specified number of value subtraction means. In addition, in the figures, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Claims] In a microprocessor that switches execution of one program by outputting a non-maskable interrupt signal at the required timing when executing one program, it is possible to check whether the program memory is at the specified address or not by accessing the same address as the program memory. A storage means for storing the presence/absence and a desired specified number of times;
A designated number of times subtraction means that subtracts the designated number of times stored in the storage means each time the designated address is read, and a zero detection signal is sent when the designated number of times becomes zero. A microprocessor comprising: a zero detecting means for outputting an output; and a non-maskable interrupt signal generating means for receiving a zero detection signal from the zero detecting means and outputting the non-maskable interrupt signal.