JPS61166646A - Memory access control system - Google Patents

Abstract

PURPOSE:To attain the common start control by sending the 1st address to a main memory, then checking the inhibition items for memory access and sending the 2nd address to the main memory only when a memory access is possible. CONSTITUTION:A memory controller 2 sends unconditionally a row address strobe RAS to a main memory 3 by an address converting mechanism 6 after a prescribed period of time when a memory access is started from a CPU1. Then the controller 2 performs various types of checks including the success/ failure check of decoding and address conversion, the storage protection check, etc. Then a row address strobe CAS is sent to the memory 3 for execution of the control according to each access mode. If some trouble is detected through said various checks, the transmission of the CAS is inhibited regardless of the type of the access. Then the transmission of the RAS is through automatically. Thus it is possible to perform the common start control regardless of the type of the access mode. This accelerates the memory access.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a memory device in a computer system, and particularly relates to a memory access control system for dynamic RAM and the like in which addresses are supplied in a time-division manner.

[Conventional technology]

Generally, in a virtual memory computer system, the logical address of an operand associated with instruction execution is converted to a physical address using a dynamic address translation mechanism, and after further checking the address translation and storage protection key, etc.
Actual memory access operations are performed. This results in considerable over-head.

Conventionally, hardware mechanisms such as TLB and MAP have been used to reduce the overhead caused by address translation, but there are limits to their improvement, and this is one of the factors that prevents speeding up memory access. ing.

In addition, recent memory devices include 64 to 256 DRA.
M is increasingly used.

In order to input two row addresses and a column address in a time-sharing manner, RAM uses timing control signals including a row address strobe called RAS and a column address strobe called CAS, and also uses fetch cycles and write cycles. A unique control sequence is executed depending on the memory access mode such as , refresh cycle, etc.

For example, if we look only at RAS and CAS.

In the fetch cycle and write cycle, RAS is applied and CAS is applied after a certain period of time as shown in FIG. 2, and in the refresh cycle.

CAS is not applied after RAS is applied as shown in FIG.

[Problem that the invention seeks to solve]

The present invention is a dynamic R
The present invention aims to provide a means for reducing the access time of main memory using memory such as AM compared to the conventional method.

[Means for solving problems]

The present invention is a dynamic R
Taking advantage of the fact that there is a time difference between the 9th row address strobe RAS and the column address strobe CAS in the fetch and write memory access modes of memory devices such as AM, first apply RAS after address conversion to start the memory. After that, operations such as address conversion check and memory protection key check are performed in parallel between the next CAS and the next CAS.

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In a computer system having a memory device of a type in which a memory address consisting of a first address and a second address is time-divisionally input, a memory control device, and a CPU, the memory control device is
When memory access is activated from , the first address is first supplied to the memory device, secondly, memory access prohibitions are checked, and only if memory access is possible as a result of the check, the second address is supplied to the memory device. It is characterized by supplying the memory to the memory and executing memory access.

[Action of the invention]

According to the present invention, when the logical address is determined.

Prior to performing address conversion and various checks, the CPU activates the memory control device to access the memory.

When the memory control device starts memory access,
A row address strobe (RAS) is unconditionally sent to the memory device after a predetermined period of time when a physical address will be available by the address translation mechanism. Next, after a certain period of time, various checks (decoding, address conversion success/failure, memory protection check, etc.) are performed for prohibited access items.
The next column address strobe (CAS) is sent to the memory device and control is performed according to each access mode (store, fetch). If any inconvenience is detected in the previous various checks, the type of access (store, Hue'7)
Prohibits CAS transmission regardless of the

Automatically ends RAS transmission. As a result, the memory device operates as if it were in refresh mode.

In this way, common activation control can be performed regardless of the type of access mode, and memory access becomes faster.

〔Example〕

The details of the present invention will be explained below based on two examples.

FIG. 1 is a configuration diagram of a system according to an embodiment of the present invention, and FIG. 4 is an operation timing chart thereof. In the figure, 1 is a CPU, 2 is a memory control device, and 3 is a dynamic RAM.
4 is a CPU control unit, 5 is a logical address register, 6 is an address conversion mechanism, 7 is a physical address register, 8 is a decoder, 9 is a CPU register control circuit, 10 is an I10 control circuit, 11 is a delay circuit, 12 is RA
13 is an error display FF, 14 is an AND gate, 15 is a CAS control FF, 16 is a refresh control section, and 17 and 18 are OR gates.

The logical address space of this embodiment system is as follows.

It includes a memory address, a 10 device address, and a CPU register address. In CPUUI, CPU
The control unit 4 performs control based on each instruction in the execution program. At this time, the address information 414 included in the instruction
Therefore, necessary address calculations are performed to determine the logical address and set it in the logical address register 5. That is, the control content indicated by the OP code of the instruction is executed for the destination indicated by the logical address.

The address conversion mechanism 6 converts a logical address into a physical address using means such as TLB, and sets it in the physical address register 7. The decoder 8 decodes the physical address, and the memory controller 2 . CPU register control circuit9. Select one of the I10 control circuits 10. Note that, as shown in FIG. 4, the CPU control section 4 applies an access activation signal to the memory control device 2 at the same time as generating the logical address (2). This is done regardless of whether the instruction being executed requires memory access or not.

The access activation signal (2) is passed to the delay circuit 11 in the memory control device 2, and is given a fixed time delay. The delay time of the delay circuit 11 is determined to be approximately commensurate with the time required to convert the logical address (2) to the physical address (2).

The access activation signal delayed by the delay circuit 11 sets the RAS control FF 12 to ON, and transfers the fourth access activation signal to the main memory 3.
A row address strobe RAS as shown in the figure @ is sent out.

''' (7) -54,: Lr, I, ((-IJ
3 (7) II[15”s7z゛,・ is started. However, at this point, various checks regarding prohibited access are still being performed, for example.

Address translation errors in the address translation mechanism 6 and decoding errors in the decoder 8 Checks for the memory protection key, etc. have not been completed, and the validity of fetching or writing data is not guaranteed, so sending of the 3-column address strobe CAS is suspended. .

The results of the various checks described above are notified to the error display FF 13 of the memory control device 2. AND gate 14 is
When the selection signal from the decoder 8 matches a predetermined timing signal, the value of the error display FF 13 is read, and the CAs control FF 15 is set according to the result. That is, the error display FF13 indicates that there is no error.
Only when in the FF state, the CAs control FF 15 is set to ON, and a column address strobe CAS as shown in FIG. 4 is sent to the main memory 3.

On the other hand, when the error display FF 13 is in the ON state indicating the existence of an error, the CAS is not sent, access is prohibited, and instead the fresh signal REF is sent as the main signal via the OR gate 17 as shown in FIG. The data is sent to the memory 3 and a refresh operation is performed.

Also, at this time, an error response is returned to the CPU control unit 4 via the OR gate 18.

Note that the original refresh operation is performed by the refresh control section 16 sending out the main memory 3 refresh signal REF via the OR gate 17.

In this way, since the RAS is sent to the main memory before the various checks are completed, memory access can be started earlier and the access time can be shortened. Furthermore, even if an access prohibition instruction is issued as a result of various checks, the tertiary CAS is not sent, and the fresh operation is directly performed, so that the previously sent RAS can be effectively used.

By the way, if a refresh operation is in progress when the memory access is started, and the error display FF 13 detects that access is prohibited, an error response can be returned to the CPU control unit 4 without waiting for the end of the refresh operation. This allows the processing efficiency of the CPU to be increased.

FIG. 5 shows the configuration of one embodiment of the memory control device 2. In the figure, 19 is an access activation display FF, 20 is a refresh activation display FF, and 21.21'
is RAS control FF, 22 is response FF, 23 is access/
Refresh control circuit.

24 is a selector, and 25 to 29 are AND gates.

30 represents a NOR gate, 31 represents an inverter, and 32 represents an OR gate.

To briefly explain the operation, when a refresh activation is applied and the refresh activation display FF20 is set to ON, unless access is in progress.

The output of the ANDNO gate is “1” due to the action of the inverter 31.
", and the RAS control FF 21' is set to ON. As a result, the access/refresh control circuit 23 sets the selector 24 to the RAS control FF 21' side, and the RAS control FF 21' is set to ON.
S is sent to the main memory 3 and a refresh operation is executed.

Here, when access activation is applied from the CPU control unit 4 of FIG. 1, the access activation display FF 19 is first set to ON. Note that at this time, the RAS control FF 21 has been reset.

After access activation, various checks regarding address translation, decoding, and access prohibitions are performed as explained in FIG.
5 to one input. The timing signal applied to the other input of the AND gate 25 provides the timing for error checking, and is generated when a certain period of time has elapsed after access activation, regardless of whether a refresh operation is in progress or not.

AND gates 25, 26, 27 and NOR gate 30
operates to transfer the ON state of the access activation display FF 19 to the RAS control FF 21 only when the refresh operation is not in progress and no error is detected. This occurs during refresh operation or when an error is detected. This is to prohibit banma aqus. 1. ,.

Note that if no error is detected but the refresh operation is in progress, the RAS control FF is
21 is set to ON.

When RAS control FF21 is set to ON.

The access/refresh control circuit 23 includes a selector 24
is set on the RAS control FF21 side, and the RAS is set on the main memory 3 side.
, and executes a fetch or write access operation.

The response signal to the CPU control unit 4 (Fig. 1) is sent to the response FF2.
2. AND game)29. generated by OR gate 32. The ANDNO gate performs the same operation as the AND gate 25, and when an error is detected, it immediately responds via the OR gate 32 even during the refresh operation.
Set 2 to ON.

Output a response signal. This allows the CPU control unit 4 to identify the error response and immediately switch control to perform other possible operations.

Note that at this time, the access activation display FF19 is reset.

Also, even if the memory access operation ends normally,
Needless to say, the response FF 22 is set to ON, a response signal is output, and the access activation display FF 19 is reset.

〔Effect of the invention〕

As described above, according to the present invention, at the time of starting memory access of the Guinami Soku RAM using RAS and CAS,
Since the RAS is sent in parallel with address conversion and various checks, memory access time can be shortened, and the processing efficiency of the CPU can be improved by speeding up error response.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram of a system according to an embodiment of the present invention. Figure 2 is a timing diagram for fetch and write cycles, Figure 3 is a timing diagram for fresh cycles, Figure 4 is an operation timing diagram of the embodiment system in Figure 1, and Figure 5 is the configuration of one embodiment of the memory control device. It is a diagram. In the figure, 1 is a CPU, 2 is a memory control device, 3 is a main memory, 4 is a CPU control unit, 5 is a logical address register, 6 is an address translation mechanism, 7 is a physical address register, 8 is a decoder, and 11 is a delay circuit. . 12 is RA S; i control FF, 13 is error display FF
. 14 is an AND gate, 15 is a CAS control FF, 16
indicates a refresh control section, and 17 and 18 indicate OR gates. Patent Applicant Panafacom Co., Ltd. Representative Patent Attorney Fumihiro Hase (1 other person) No. 2c21 No. 312] $ 4 圀■ ShakeεE

Claims (2)

[Claims] (1) In a computer system having a memory device of a type in which a memory address consisting of a first address and a second address is input in a time-sharing manner, a memory control device, and a CPU, the memory control device controls memory input from the CPU. Upon access activation, first the first address is supplied to the memory device, then the memory access prohibitions are checked,
A memory access control method characterized in that the second address is supplied to the memory device and the memory access is executed only when the memory access is possible as a result of the check. (2) In the above paragraph 1, the memory control device includes a CPU
When a memory access is started from a memory device, the memory access prohibition item is checked after a certain period of time, and if memory access is prohibited as a result of the check, it is determined that the memory device is in the refresh operation at that time. A memory access control method characterized in that an error response is sent to a CPU regardless of the situation.