JPS58109950A - Hidden memory access control circuit - Google Patents

Abstract

PURPOSE:To eliminate requirement of special time for switching of memory, by making a selected program instruction arbitrarily out of the program instructions of memory access exclusively used one of hidden memory access. CONSTITUTION:An operation code coincidence detection circuit 6 interprets the operation code detected from a memory 4. When a selected access is detected out of program instructions of memory access, a memory change signal HCHG is outputted from the circuit 6, to switch a data bus switching circuit 7 to the hidden memory 2. Thus, even after the memory is switched, the switched memory is accessed in the normal instruction reading and execution cycle and no special time is required for the access. Since this switching is independently of the program progress, the address designation of the switched memory is done, allowing to attain memory usage efficiently.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a hidden memory access control circuit.

Generally, when a CPU (Central Processing Unit) accesses a memory, various methods are possible for reading/writing the memory. For example, BC, DE, and HL provided in the CPU.

IX, IY, etc. (for ZIOcpu), certain Iha Ro-
By arbitrary program instructions using each register named R, etc. (in the case of other general minicomputer CPUs),
Can access (read/write) memory.

By the way, the memory range that the CPU can access is limited to a predetermined amount (J (ZK bytes) for a 2♂0 CPU) based on its address capacity.When expanding this, conventionally, the memory range that can be accessed by the CPU is etc., to set the flip-flop height and switch the memory page by page.However, in this case, as mentioned above, there is a separate 4-instruction program for switching, which needs to be executed. One problem was that it took a long time to access the program area, and the additional memory had the disadvantage that the address portion corresponding to the program area could not be used.

The expanded memory is what is called hidden memory, but in view of the fact that there are generally various program instructions for memory access, the present invention arbitrarily selects one of them and dedicates it to hidden memory access. This eliminates the drawbacks of the conventional method.

An embodiment of the present invention will be described below with reference to the drawings.

Figure 1 shows a block diagram of the main parts. Practically speaking, it is desirable to use an iphrogram instruction, which is rarely used in normal memory access, among various instructions, as an instruction exclusively for hidden memory access. Here, for example, BC register/
Access using is used to access hidden memory.

■ LD A, (BC) OAH ■ LD (
BC), A02H■ is an instruction (read) to read the data at the address specified by the BC register/ into the A register 3, and the operation code is expressed as "OAH". Also, ■ is an instruction (write) to write the contents of A register 3 to the address specified by BC register /, and the operation code is expressed as "OJH".

The memory rig is a memory that has a predetermined program area and is normally equipped. When accessing using other registers such as the DE register 5 shown in the figure, the memo rig is accessed and read/written.

The operation code match detection circuit B decodes the operation code detected from the memory register in order to execute various programs.

When the above-mentioned operation code "OAH" or 0.2H" is detected by this operation code coincidence detection circuit, the memory change signal [(CHG) is output and the data bus switching circuit 7 is switched to the hidden memory side. That is,
When the operation code is "OkH" or "0.2K", the corresponding instruction is executed in the switched hidden memory t.

Figure 1 is a time chart showing this situation.

φ is the clock, MI is the opcode read cycle, M
REQ indicates a memory request, and MCHG indicates a memory change signal. As shown, the opcode is fetched and decoded during the instruction read period. When the operation code "OAH" or "0.2H" is detected in this decoding, the hidden memory is accessed during the execution period by the memory change signal MCHG, and the instruction is executed in the hidden memory. Execution When the period ends, the memory returns to IJF and returns to its normal operating state.

In other words, according to this example, even if the memory is switched, the switched memory can be accessed (read/written) in a normal instruction read and execute cycle, and no special time is required for access.

Furthermore, since this switching has no relation to program progress, any address in the switched memory can be specified, allowing for efficient memory use.

As shown in Figure IJ1, this is constructed by using the opcode match detection circuit g for decoding the opcode for program execution in the CPUr, and with some modifications for deriving the memory change signal. There is, but cpu,
For data bus switching, a dedicated opcode coincidence detection circuit may be provided for data bus switching, which detects only the opcodes "OAH" and "/(7,2H") and generates a memory change signal.

Note that it is clear that the same procedure can be implemented using not only the instruction using the BC register/, but also other instructions that do not allow memory access. It is also possible to select an appropriate instruction and expand the hidden memory by that amount, as long as it does not interfere with normal memory access. Of course, there is no problem if the conventional I10 instruction and memory switching using a flip-flop F/F are used together.

As described above, according to the present invention, it is possible to provide a useful hidden memory access control circuit with high practical value, since it does not take much time to switch memories and the hidden memory can be used effectively without any restrictions.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of essential parts showing an embodiment of the present invention, and FIG. 1 is a flowchart explaining the operation thereof. /,! ,! ...Register, code...hidden memory, group...memory, t...opcode match detection circuit, 2.
...Data bus switching circuit, ♂...CPU. Agent Patent Attorney Aihiko Fukushi

Claims (1)

[Claims] 1. A hidden memory access control circuit comprising: means for detecting a selected operation code for memory access; and means for switching a data bus to a hidden memory based on the output of the detecting means.