JPS62279442A - Japanese language processing device - Google Patents

Abstract

PURPOSE:To add data for processing Japanese language without eroding a main memory by forming an address space required by data for processing Japanese in a back memory of a CPU having two address areas by bank switching. CONSTITUTION:When key code that designates a KANJI (Chinese character) conversion mode is outputted from a keyboard 8, a CPU 1 outputs a select signal CM that accesses a main memory space, and controls a switching circuit 10. In accordance with the signal from the CPU 1, the switching circuit 10 outputs switching signals S1, S2 and activates an ROM 3. Thereby, the mode is changed from a BASIC mode to a KANA (Japanese syllabary) KANJI conversion mode, and a KANJI processing program in the ROM 3 is executed. When displaying KANJI, the CPU 1 outputs the select signal CM, and controls a selector circuit 11 to select a block that stores KANJI patterns, and outputs a select signal CS to store data in a register. Then, the CPU outputs the CM signal and writes the data in a VRAM 6.

Description

[Detailed Description of the Invention] 3. Detailed Description of the Invention <Industrial Application Field> This invention provides a Japanese language processing device using an 8-bit CPU (Central Processing Unit), such as a main memory get computer. The present invention relates to a Japanese language processing device suitable for adding processing functions.

<Prior art> Conventionally, when constructing a Japanese language processing system that requires at least 64 KB of memory on an 8-bit CPU that only has an address space of 64 KB in a pocket computer, etc., it is normal to use one part of the 64 KB address space. For example, change the bank of 16KI3 and map Japanese processing data to this bank area, but if all 64KB address space is already used in some way, in order to add Japanese processing data, There is a problem that after switching banks, the space cannot be used. In other words, if Japanese processing data is added, the main memory will be eroded, and there is a problem that the block diagram will not be compatible with current models.

Furthermore, FIG. 4 is a memory map of a Japanese language processing device using a conventional 8-hint CPU. This r1. M+
, -k6 i1 2 i dimension1 /n (person'44 force'h-
14-kyll? b is a system program area, and C and d are RAM (random access memory) areas. bl is Kanji conversion processing program area, 01-C
I8 is an area for storing kanji data, dictionaries, etc. necessary for kanji conversion processing.

However, although banks can be switched with this conventional memory arrangement, if an attempt is made to access a 256 KB memory area by switching banks, 17 banks will be required even if 16 KB is allocated, making bank switching control complicated. However, there was a problem that the circuit became complicated.

<Object of the Invention> Therefore, the object of this invention is to add a large capacity of Japanese data that is larger than the main memory, without encroaching on the main memory, and thus while maintaining compatibility with current machines.
Another objective is to simplify the circuit by reducing bank switching.

<Configuration of the Invention> In order to achieve the above object, the Japanese language processing device of the present invention includes a table memory (MMi) that stores at least program data and processing data and is accessed by an address signal from the CPU, and a table memory (MMi) that stores at least program data and processing data. consists of the same size as, and
A control command that selects the back memory (SMi) that stores data necessary for Japanese processing and is accessed by an address signal in the same address space as the above address signal from the CPU, and the front memory or back memory of the above program. The present invention is characterized in that it has a decoding means and a CPU that outputs a selection signal.

Function: Use a CPU with two address areas, create a memory address space required for Japanese processing data in a back memory area separate from the main memory area, and store the Japanese processing data. By doing this, data for Japanese processing can be added without encroaching on the main memory, in other words, while maintaining program compatibility with current machines. Furthermore, bank switching is reduced and the circuit is simplified.

<Examples> The present invention will be described in detail below with reference to illustrated examples.

FIG. 1 is a memory map of one embodiment of the present invention, and E is the l10 (input/output) boat area, which corresponds to a in FIG. 4. F is a system program area and corresponds to b in FIG. G is a flAM (random access memory) area and corresponds to C and d in FIG.

M is a kanji conversion processing program area and corresponds to bl in FIG. H, 1, J, and L are areas for storing data necessary for kanji conversion processing, and correspond to C1 to C18 in FIG. 4. Kanji patterns are stored in H, proper noun dictionary data is stored in ■, kana-kanji conversion dictionary data is stored in J,
Onkun dictionary data is stored in K, and grammatical information data necessary for kana-kanji conversion is stored in 7. MM in FIG.

MM, is the main memory space, and SM,,SM,.

8M3.3M4 corresponds to the back memory space.

Further, FIG. 2 is a block diagram of the above embodiment.

1 is a CPU that performs various control processes according to given instructions
It is. This CPUI is an address control unit, ;4y1r
"m7AAlt++4'In1117.!Q#+l<m
ap+,,'jM)jIN? The program counter register (hereinafter referred to as PC register) reads instructions from the designated program area of the 64 KB main memory space (table memory space) and performs program processing.

In addition to the above-mentioned front memory space, this CPU has a memory space (back memory space) of the same size that can be switched according to instructions, and by sharing the above-mentioned address control section,
The memory is being accessed.

Instructions for the CPU to read or write to memory include the data read instruction LDA (n) from the table memory space and the data write instruction STA.
(n), and also has a data read instruction RE A D (n) and a data write instruction WRTT to the back memory space.
(n). CP[Jl responds to the instructions by decoding these spare instructions, outputting the signal CM for access to the front memory space, and outputting the signal C8 for accessing the back memory space. Select address signal.

Reference numeral 2 denotes a ROM (read-only memory) that stores system programs such as a BASIC (Hönock) interpreter, and is assigned to F on the memory map in FIG. 3 is the first ROM that stores the kanji conversion processing program.
Assigned to M on the diagram.

ROM2 (F) and ROM3 (M) are the switching circuit 11 described later.
The selection is made by the select signals S, , S, from.

4 is a RAM (RAM) that stores data, user programs, etc.
random access memory) and is allocated to G in FIG. 5 is an I10 device such as a floppy disk. 6 is a video RAM (
VRAM). ■／○Device 5. VRAM6 is allocated to E on the memory map in FIG. 7 R that stores kanji data, dictionaries, etc. necessary for ephemeral alphabet conversion processing
OM, internally 7-1. ? -2.7-3.7-4
It is divided into four blocks, each having a capacity of 64 KB, and corresponds to SM, , SMt, and SM3°9M4 in FIG. 8 is a keyboard, and 9 is a display device for displaying and outputting the contents of the VRAM 6. 10 is a switching circuit that switches between R)M2 and ROM3 based on code data from the CPUI. This switching circuit IO is equipped with an internal register allocated in the address space (E) that holds code data supplied from the CPUI indicating which one to select before reading data from the ROM after switching. There is. Based on the code data of this register, ROM2
A signal S1 for selecting ROM3 or a signal S2 for selecting ROM3 is output. Therefore, the banks of the memory spaces (P) and (M) can be switched in the table memory space by the signals s1 and S. II is RO by the signal from cPUl.
7-1.7-2.7-3 in M 7. This is a selection circuit that selects L-4.

This selection circuit 11 includes the ROM 7 (RAM) after the above selection.
RO before reading data from
It has an internal register allocated in the address space (E) that holds code data supplied from the CPUI indicating which one of M7-1.7-2.7-3.7-4 to select. Based on the code data of this register, r(
It outputs any one of the signal B8 for selecting 0M7-1, the selection signal B2 for ROM7-2, the selection signal B3 for ROM7-3, and the selection signal B4 for ROM7-4. Therefore, 31-B
4, the memory space S M in the back memory space
1. Bank switching between SM-, SM3, and SM- can be performed.

Also, D is a data bus, A is an address bus, R/W is a read/write signal, CS is a select signal issued when accessing the CPUI or back memory space, and CM is a CPLII
is the select signal issued when accessing the main memory space.

Next, the operation of the above embodiment will be explained.

When a key code specifying a kanji conversion mode is output from the keyboard 8, the CPU outputs a select signal CM for accessing the main memory space and controls the switching circuit 10. The switching circuit IO outputs switching signals S, , S, and activates the ROM 3 in accordance with a signal from the CPU 1.

As a result, the Kana-Kanji conversion mode is entered from the BASIC mode, and the Kanji processing program in ROMa is executed. When displaying a kanji character during kanji processing, the CPU outputs a select signal CM, controls the selection circuit 11 to select a block that stores the desired kanji pattern, outputs a select signal C8, and connects the address bus A to the data Bus D
Store data in registers through . Then, it outputs the CM signal and writes data to the VRAM 6 through the address bus A1 and the take bus D. By storing kanji data in one of the memory spaces of the CPU 1, which can be switched between two memory spaces by a command, program processing is simplified and the bank switching circuit 10 can be easily configured in terms of hardware. can.

In this way, the memory space that can be accessed using general commands such as read and write (main memory) and the memory space that can only be used with 1-byte read/write commands (back memory) can be effectively used. This makes it possible to process kanji characters without standardizing the main memory structure.

FIG. 3 is a flowchart of the kanji processing program in the above embodiment, and the kanji processing program is shown in FIG.
It is stored in M3.

The CPU reads the keys in step S1 and performs kanji conversion according to the kanji processing program of R0M3.

When the CPUI reads the key, it determines whether the key is a conversion key or not in step S2. If it is not a conversion key, a CM signal is output by the S T A (n) command, the address n of the original text buffer in RAM 4 of the table memory space is output from address bus A, and the key code is sent to the original text buffer via data bus D. The data is written and displayed (step SJ). And CPU I is L D
A (n) command writes the contents of the source text buffer to RAM
4, and from the read code, find the storage address of the character pattern data corresponding to the code,
READ A(n) outputs the C3 signal, reads pattern data from ROM7 in the back memory space that stores character pattern data, and writes the pattern data to V RAM 6 using the S'I'A(n) command. (Step S4). When the conversion key is pressed, the process moves to kana-kanji conversion processing, and the CPU reads the contents of the original text buffer from RAM II according to the command from ROM3, stores it, and converts it to R.
The dictionary data in the back memory space is accessed by the EAD command, and the same data as the original text buffer is retrieved (step S5). If the same data exists, read the kanji code from that data area using the READ command, and then write it to the ROM.
3, the kanji code is written into the result buffer in RAMd (step S7). Then, in the same manner as when displaying the contents of the original text buffer, the kanji pattern data in the back memory space is read from the contents of the result buffer and written to the VRA and M6 (step S). If the output kanji is the desired kanji, step S1
Proceed to step 2, and if the mote has ended, switch the bank of the main memory space and I'? OM2's BA, jump to SIC interprogram. To continue processing kanji, press 11.
Jump to the beginning of the program at 0M3.

The back memory is memory located in the back memory space that has the same address as the main memory (front memory) space that can normally be accessed by the CPU, and is used by the LD that accesses the front memory space.
, ST commands, etc. can only be accessed, and READ and WrllTE commands that access the back memory space cannot be accessed by CP.
It can only be accessed when given to the UI. Also, unlike the memory in the main memory space, the back memory can only transfer one byte at a time.

As described above, since switching access to the memory area can be performed by commands in the program, bank switching becomes easy, and wiring within the device such as the bar switching circuit and selection circuit can be simplified.

<Effects of the Invention> As is clear from the above, according to the present invention, in a CI (CI) U having two address areas, data for Japanese processing is required to be stored in the back memory in addition to the main memory by bank switching. A] response space is generated, so by making it pine pink, it is possible to add data for Japanese processing without encroaching on the main memory, or in other words, while maintaining program compatibility with current machines. The circuit can be simplified by reducing bank switching.

[Brief explanation of the drawing]

FIG. 1 is a memory map diagram of an embodiment of the present invention, FIG. 2 is a block diagram of the embodiment described above, FIG. 3 is a flowchart of the embodiment described above, and FIG. 4 is a memory map diagram of a conventional device. 1...CPU, 2.3...ROM, 4...RA, M. 6.VRAM, 10.Switching circuit, [l Selection circuit. Patent applicant Noyab Co., Ltd. Agent
Patent attorney: 2 people (excluding Mr. Uegi) Figure 4

Claims (1)

[Claims] (1) A table memory (MMi) that stores at least program data and processing data and is accessed by address signals from the central processing unit, and a table memory (MMi) that is the same size as the table memory and that stores data necessary for Japanese processing and a back memory (SMi) which is stored and accessed by an address signal in the same address space as the address signal from the central processing unit, and means for decoding a control command for selecting either the front memory or the back memory of the program. , and a central processing unit that outputs a selection signal.