JPH04262475A - Microcomputer with built-in fuzzy arithmetic circuit - Google Patents

Abstract

PURPOSE:To make conventional development support device and program procedure available with a simple configuration without changing the conventional function for conventional CPU core. CONSTITUTION:Fuzzy processing end flag F is installed in special purpose microcomputer exclusive register group 10 of CPU core section 1, and a fuzzy arithmetic processing end signal line 24 at a fuzzy section is connected to the fuzzy arithmetic processing end flag F so that the flag can be set when fuzzy arithmetic processing terminates.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microcomputer that integrates a CPU core section and a fuzzy core section.

0002

2. Description of the Related Art Conventionally, a microcomputer with a built-in fuzzy arithmetic circuit has not been used, but a microcomputer having a structure in which a CPU chip and a chip dedicated to fuzzy arithmetic are connected via a bus has been used. FIG. 4 shows a conventional configuration diagram. In this configuration, a control/status register area is allocated within the address space of the fuzzy processor. Further, the fuzzy processor outputs a BUSY signal to the CPU during fuzzy processing.

FIG. 5 shows the address space of a fuzzy processor. Control registers and status registers are equally allocated to the register area. When writing to the register, it becomes a control register, and when reading from it, it becomes a status register. After writing the input data into the input data area, the CPU starts the fuzzy calculation, and at this time sets a processing start flag in the control register. The fuzzy processor starts the fuzzy operation by knowing the set state of the flag. Further, the fuzzy processor drops the BUSY signal to "L" when the fuzzy operation is completed. B.U.
The SY signal is connected to the CPU's interrupt terminal IRQ, and the CPU
detects an interrupt by looking at the change in the BUSY signal, and reads the fuzzy calculation result from the output data area. Alternatively, fuzzy arithmetic processing is detected by reading the processing end flag of the status register.

0004

In order to incorporate a fuzzy arithmetic circuit into a microcomputer, an internal interrupt controller and a read cycle timing controller for the status register of the fuzzy core are required in the CPU core. However, with this configuration, a complicated processing circuit must be added, and the development load increases, leading to an extension of the development period. Moreover, not only the development of microcomputers but also the problem arises that conventional microcomputer development support equipment cannot be used anymore, and such equipment needs to be newly developed.

An object of the present invention is to provide a microcomputer with a built-in fuzzy arithmetic circuit that can utilize conventional development support equipment and user program procedures without changing the conventional functions of a conventional CPU core. It is about providing.

[0006]

[Means for Solving the Problems] A microcomputer incorporating a fuzzy arithmetic circuit according to the present invention is composed of a CPU core section and a fuzzy core section, and a fuzzy processing end flag is provided in a dedicated register of the CPU core section to perform fuzzy processing. The present invention is characterized in that a fuzzy arithmetic processing end signal line in the core section is connected to the fuzzy processing end flag, so that the flag is set when the fuzzy arithmetic processing ends.

[0007]

[Operation] A fuzzy processing end flag indicating the end of fuzzy processing is assigned to the condition code register (flag register) in the dedicated register group provided in the CPU core, and the fuzzy arithmetic processing end signal line is connected to this flag. As a result, the fuzzy core unit sets the flag by activating the fuzzy arithmetic processing end signal line at the same time as it ends the fuzzy arithmetic processing. Since the dedicated register of the CPU core section can be used by the user program, the user program can detect the end of the fuzzy arithmetic processing. In other words, no extra burden is placed on the CPU. Further, when developing a program, the conventional microcomputer development support device can be used as is since the configuration of the CPU core remains unchanged.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a block diagram of an embodiment of the present invention. This microcomputer is composed of a CPU core 1, a fuzzy core 2, a data buffer 3 and an address buffer 4 connected to an external bus. CPU core 1
are the microcontroller dedicated register group 10, ALU 11, and CP
The fuzzy core 2 is composed of a U-core control section 12 and an instruction register 13, and the fuzzy core 2 is composed of a fuzzy operation section 20, a knowledge memory 21, a fuzzy input/output register 22, and a fuzzy core control section 23. A fuzzy arithmetic processing end signal line 24 is connected from the fuzzy core control unit 23 to the microcomputer dedicated register group 10, and when the fuzzy core control unit 23 ends the fuzzy arithmetic operation, the fuzzy end flag is set via this signal line. Output a signal. In reality, as shown in Figure 2, microcomputer-specific register group 1
A fuzzy end flag F is assigned to the fourth bit of the condition code register provided in 0, and the fuzzy end flag set signal is input to this flag F via a gate not shown. N, Z, V, and C of this register are the same as the flags assigned to the registers of a normal microcomputer. In FIG. 1, the fuzzy core 2 is connected in a subordinate manner to the CPU core 1, and the
When a calculation start signal is sent from the PU core control unit 12 to the fuzzy core control unit 23, the fuzzy core 2 starts fuzzy calculation, and when the fuzzy calculation is finished, it outputs a fuzzy end flag set signal and sets the condition code in the condition code register. Set the fuzzy end flag F of . C.P.
The U core 1 transfers the fuzzy input data to the fuzzy input/output register 22 before issuing the calculation start signal to the fuzzy core 2. Further, this flag F is monitored in the user program, and when it is detected that the flag F is set, fuzzy output data is read from the fuzzy output register of the fuzzy input/output register 22. Note that flag F can be easily monitored by using a conditional branch instruction. That is,
The following four functions are added to the CPU core in this embodiment compared to the conventional CPU core.

(1) Transfer of fuzzy input data to the fuzzy input register (2) Transfer of fuzzy output data from the fuzzy output register (3) Output of a calculation start signal to the control unit 23 of the fuzzy core 2 by decoding the fuzzy start command (4) Conditional branch instruction processing using the F flag of the condition code register By simply adding the above four functions, the fuzzy operation related processing can be completed according to the flowchart shown in FIG.

That is, in step n1, input data is written to the fuzzy input register, in step n2, a fuzzy operation start instruction is issued, and in step n3, a fuzzy end flag is monitored by a conditional branch instruction, and this fuzzy end flag is set. In this state, output data is read from the fuzzy output register in step n4.

When the fuzzy operation start command is issued at n2, the fuzzy core control section 23 receives the operation start signal and starts fuzzy operation processing in the fuzzy core 2. When the fuzzy operation is completed, the fuzzy core control unit 23 outputs a fuzzy end flag set signal to the signal line connected to the fuzzy end flag of the condition code register in the CPU-dedicated register group 10.

The above process is particularly different from conventional microcomputers in that the CPU core 1 only outputs a calculation start signal to the fuzzy core 2, and the end of the fuzzy calculation process is monitored by an interrupt control circuit or the like. This is not the case.

[0013] This monitoring can be performed by a conditional branch instruction in the user program. Therefore, it is possible to reduce the load on the CPU core 1.

As is clear from FIG. 1, the above (1) to (
Addition of the function 4) only requires adding a decoding circuit to the CPU core control unit 12, and there is no need to newly add or change an interrupt controller, timing controller, etc. Therefore, the conventional development support device can also be used. Furthermore, programs created by the user can be created using exactly the same procedure as in the past, making the chip easy for the user to use. In particular, conditional branch instructions can be used, the number of program steps can be reduced, and processing can be done quickly.

[0015]

Effects of the Invention (1) It is not necessary to add an internal interrupt controller or a status register read timing controller.

(2) Since there is no need to change the conventional functions of the CPU core, the microcomputer development support device can be used as is. Furthermore, various CPU cores and fuzzy cores can be connected.

(3) A user program can be created using the same procedure as before, making the chip easy for the user to use. Furthermore, since conventional conditional branch instructions can be used, the number of program steps can be reduced and high-speed processing can be achieved.

[Brief explanation of the drawing]

FIG. 1 shows a block diagram of a microcomputer according to an embodiment of the present invention.

FIG. 2 shows an example of bit allocation of a condition code register.

FIG. 3 shows a processing flow of a user program, a CPU core, and a fuzzy core.

FIG. 4 shows an example of the configuration of a microcomputer with a conventional fuzzy calculation function.

FIG. 5 shows the conventional fuzzy processor address space.

[Explanation of symbols]

1-CPU core 2-Fuzzy core 10-Microcontroller dedicated register group 23-Fuzzy core control section 24-Fuzzy operation processing end signal line F-fuzzy end flag

Claims (1)

[Claims] Claims: 1. Consisting of a CPU core section and a fuzzy core section, a fuzzy processing end flag is provided in a dedicated register of the CPU core section, and a fuzzy arithmetic processing end signal line in the fuzzy core section is connected to the fuzzy processing end flag. A microcomputer with a built-in fuzzy arithmetic circuit, characterized in that the flag is set when the fuzzy arithmetic processing is completed.