JPS6158039A - Microprogram controller - Google Patents

Abstract

PURPOSE:To improve the processing capability of a microinstruction by using the microinstruction for generating an access address or generating write data to transmit an access request signal before a read/write microinstruction is executed. CONSTITUTION:In accessing from a microprocessor section 1 to a storage section 3, the microinstruction read from a control storage section 2 is set to an instruction register 15. An access request signal (MPUREQ) of the storage section 3 is set to a flip-flop 17, the write/read designation signal is st to a flip-flop 18 and transmitted to the storage section 3. When the storage section 3 receives the MPUREQ signal, the section 3 transmits an access reception signal to the microprocessor section 1 to start the access to the memory. On the other hand, the access address generating microinstrudction is executed by an operation section 13, the acess address is set to the register 14 to execute write/read to the storage section 3.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a vertical microprogram control device in a data processing device, and more particularly to a separate access system for its storage section.

(Prior Art) In a conventional vertical microprogram control device, the order of execution of microinstructions when accessing a storage section is that an address generation microinstruction that generates an access address for the storage section is first executed, and then the microinstruction for accessing the storage section is executed. In the case of writing, a write data generation microinstruction for generating write data is executed.

The execution order of this write data generation microinstruction may be reversed from that of the address generation microinstruction.

Following the above execution, microinstructions for accessing the storage section and microinstructions for reading/writing are executed.

Execution of address generation microinstructions and write data generation microinstructions completes in one machine cycle, but since accessing the memory section takes time, execution of memory section access microinstructions takes 2 to 3 machine cycles. is necessary. FIG. 4 is a timing chart showing 10 operation implementations of the conventional device. Since three machine cycles are required, the processing time of the microprogram becomes long and the throughput is reduced.

An object of the present invention is to send an access request signal to a storage section using a microinstruction for generating a storage section access address or a microinstruction for generating write data, and to execute a read/write microinstruction in one machine cycle. It is an object of the present invention to provide a microprogram control device configured to eliminate the above-mentioned drawbacks, increase the processing speed of microprograms, and improve the cost/performance ratio.

(Means for Solving the Problems) A microprogram control device according to the present invention includes a storage section, a control storage section, and a processor.

The storage unit is for storing information.

The control storage section is for storing vertical microinstructions.

The processor is connected to the storage unit and the control a11 storage unit, and is for executing vertical micro-instructions to perform processing, and has access information processing and sending means, write information processing and sending means, and address registers. It is established from

The access information processing and sending means executes an adreno generation microinstruction and a write/read specification microinstruction when accessing the storage unit, and, following the write/read specification microinstruction, sends a write/read request signal to the storage unit. It's for sending out.

The write information processing and sending means executes a write data generation microinstruction and a write designation microinstruction when writing information to the storage unit, and sends out a write request signal to the storage unit following the write designation microinstruction. It is for.

The address register is for specifying a write address to the storage section.

(Function) The present invention provides a microprogram control device that executes vertical microinstructions, in which a storage section access request signal is generated by executing an access address microinstruction or a storage section write data generation microinstruction when accessing a storage section. By executing the sending and main memory access microinstructions in one machine cycle, the processing speed of the microprogram is improved.

(Embodiment 11) Next, an embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing an implementation of a microprogram control device 1m N according to the present invention. In FIG. 1, 1 is a microprocessor unit for executing vertical microinstructions, 2 is a control storage unit for storing microprograms, 41 is a storage unit, 41 and 42 are input/output device connection units, and 100 is a traffic light 105 that transmits an address for accessing the control memory 2 and input/read information;
is the microprocessor section 1 and the input/output device connection sections 41 and 42.
101 indicates the address bus signal resistance 1 when accessing the storage section 3. 102 indicates the bus signal resistance for accessing/reading data to the storage section 3. Access to the storage section is performed by exiting the storage section request signal from the microprocessor section 1 and the input/output device connection sections 41 and 42.

FIG. 2 is a block diagram showing the operation of the microprocessor section according to the present invention.

FIGS. 3(a) and 3(b) are time charts when accessing data W15.

The present invention will be described in detail below with reference to FIGS. 2 and 3. In FIG. 2, 11 is a general purpose working register group (GPR) composed of RAM, 12 is an accumulator (ACC), 13 is an arithmetic unit (ALU), and 14
is an address register (MMAR) 1 used when accessing the memory section from the microprocessor section 1;
5 is a microinstruction register (MIR), 16 is a decoder, 17 and 18 are flip-flops, and 19 is an OR
Gate 20 is an AND gate.

In the access operation from the microprocessor unit 1 to the storage unit 6, the microinstruction read from the control storage 2 is set in the microinstruction register 15, and this microinstruction is processed by the decoder 16 as a microinstruction for generating an access address for the storage unit B. (ADG). Identification signal and timing signal T1 on signal line 161
Toyoυ storage unit 3 access request signal (MPUREQ)
is set in the flip-flop 17, a write/read designation signal (MMRWT) is set in the flip-flop 18 according to the value of the write/read mode pit of the access address generation microinstruction ADG and the tiling signal on the signal line 11, The data is sent to the storage unit 3.

When the storage unit 6 receives the MPUREQ signal, the storage unit 3 sends a permission signal MPUACK to the microprocessor unit 1 to start accessing the memory element. The MPUREQ signal is reset by the MPUACK signal.

On the other hand, the access address generation microinstruction ADG is
This is executed by the arithmetic unit 13 to generate an address for accessing the storage unit, and the execution result is set in the address register 14 using the timing signal T2. Two operands during address operation are executed between the general-purpose working register group 11 and the accumulator 12, or between the general-purpose working register group 11 and the constant part of the microinstruction register 15. This is for calculations performed.

The output signal of the address register 14 is valid when the MPUACK signal is 1. Following the access address generation microinstruction ADG, the write/read microinstruction RWO to the storage unit 3 is executed, and when data is written to the storage unit 6 (, MMRWT = -1〃), the write data is transferred from the accumulator 12. Bus signal line 10
2 and read data from the storage unit 3 (MMR
When WT=-Ol), an operation is performed to take the contents of the data bus signal line 102 into the accumulator 12.

Data on the data bus signal line 102 remains valid when the MPUACK signal is 11#. When writing data to the storage unit 6, access address generation microinstruction A
A microinstruction to set the write booter accumulator 12 is executed before executing DG. This microinstruction does not have the function of requesting access to the storage unit 6. When writing data to the storage unit 6, the write operation can be performed using a microinstruction (DTG) for generating write data to the storage unit 6 and a subsequent microinstruction for accessing the storage unit.

When the write data generation microinstruction DTG is read from the control memory 2 and set in the microinstruction register 15, the decoder 16 identifies it as a write data generation microinstruction (DTG) to the storage unit 3. . Based on the identification signal on the signal line 162 and the timing signal T1, an access request signal MPUREQ to the storage unit 6 is set in the flip-flop 17, and a write/read designation signal MM is set.
RWT is set in the flip-flop 18 and the storage unit 3
sent to. When the storage unit 6 receives the MPUREQ signal, the storage unit 6 accepts the access and sends a permission signal MPUACK to the microprocessor unit 1 to start accessing the memory element.

Therefore, the MPUACK signal is MPUACK.
Reset by a signal. On the other hand, the fragrance data generation microinstruction DTG sets the data to be written to the storage section 3 in the accumulator 12. This data is transferred from the constant part of the general-purpose working register group 11 or the microinstruction register 15, or between the general-purpose working register group 11, or between the general-purpose working register group 11 and the accumulation rake 12, or from the general-purpose working register group 11, or between the general-purpose working register group 11 and the accumulation rake 12, or The data is the result of an operation between the group 11 and the constant part of the microinstruction register 15. The output of the address register 14 and accumulator 12 to the address bus signal line 101 and data bus signal line 102 is M
Valid only while PUACK is 1.

(Effects of the Invention) As explained above, the present invention has a vertical microinstruction type microprogram control device that uses a microinstruction for generating an access address or creating write data before executing a read/write microinstruction. By sending out the access request signal for the storage section, the execution time of the access command for the storage section can be shortened and the processing ability of the microprogram can be improved.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a microprogram control device according to the present invention. FIG. 2 is a partial block diagram of the microprocessor section shown in FIG. 1. FIGS. 3(a) and 3(b) are time nayat showing an example of the operation according to the present invention. FIG. 4 shows a timing chart showing the actual operation of the conventional device. 1@...Microprocessor section 2...Control storage section 3...Storage section 41.42...I/O device connection section 11.14.15.Φ.Register 12...Accumulator 13...Calculation Device 16...Decoder 17.18...Flip-flop 19...OR gate 20...AND gate

Claims (1)

[Claims] a storage unit for storing information; a control storage unit for storing vertical microinstructions; and a control storage unit connected to the storage unit and the control storage unit to execute processing by executing the vertical microinstructions. and a processor for executing an address generation microinstruction and a writing/reading designation microinstruction when accessing the storage unit, and following the writing/reading designation microinstruction, access information processing and sending means for sending out a write/read request signal to the storage unit; executing a write data generation microinstruction and a write designation microinstruction when writing information to the storage unit; write information processing and sending means for sending a write request signal to the storage unit following the write designation microinstruction;
A microprogram control device comprising: an address register for specifying a write address to the storage section.