JPS61138344A - Debugging system - Google Patents

Abstract

PURPOSE:To set up a brake point also at an optional address and to attain also the debugging of a ROM software by storing the information of the brake point in a memory different from a main memory. CONSTITUTION:If a certain address in a main mory unit 2 when a processor unit (PU) 1 executes a program, the same address in a brake point memory (BPM) 4 is simultaneously read out. If an output 161 or 162 in a BPM signal 16 of the BPM4 is active, the setting of the brake point in the address is indicated. When the brake conditions of the outputs 161, 162 indicating that the memory access is a memory read or a memory write respectively coincide with each other, an interruption request signal 17 is made active. When an interruption is requested to the PU1, the program in executing is interrupted and a brake point processing routine is started.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a software debugging method for an information processing device 0 and a software debugging method.

(Prior Art) One of the functions for debugging software in a computer system using a microprocessor is to load a program into main memory at a preset address while the routine to be debugged is being executed. A break function that interrupts the processor and starts the debug processing routine when the instruction or data that is currently being accessed is accessed.
There is a point function.

There are two ways to implement this function:

The first is the register that stores the preset break address and the processor address.
Consists of a comparator that compares bus information with
This method compares the contents of this register with the contents of the address bus when the processor accesses main memory, and when the two match, interrupts the processor. FIG. 8 shows a block diagram of this conventional example. A computer system consisting of a processor unit (Pu) 1001 and a main memory unit (MMU) 1002 is broken. Processor unit 1001 and main memory unit 100
2 is an address bus 1011, a data bus 10
12. They are connected via a control bus 1013.

Break-point address register 1003 stores a break address.

Information can be written to this register 1003 manually by using a switch, or by placing this register 1003 in space 10 of processor unit 1001 and setting a break point address by software. The address comparator 1004 is connected to the address bus 10 output from the processor unit 1001.
11 and break point address register 100
This is a circuit that detects a match with the output of 3. When the processor unit 1001 accesses the main memory unit 1002, if the value of the address bus 1011 and the value of the break point address register 1003 match, Match signal 1015 from address comparison fjlo04
is output. This match signal 1015 is connected as an interrupt request signal to the processor unit 1001, and is sent to the break point address register 10.
When the processor unit 1001 accesses the same address as the address in 03, an interrupt occurs and a debug processing routine is started.

The second conventional example is a method of breaking only for instructions. This method is achieved by replacing the instruction you want to break in software with a special instruction (for example, an internal interrupt instruction or illegal instruction), and starting the debug processing routine when the special instruction is executed. It is.

(Problem to be Solved by the Invention) The first method described above requires a pair of break point address register and address comparator for each break point location, and a break point address register and an address comparator are required for each break point location. Setting points involves an increase in hardware proportional to the number. Therefore, this method usually limits the number of breakpoints to a few locations;
There is a problem that sufficient debugging is not possible.

Furthermore, with the second method, it is impossible to set break points regarding data access. Furthermore, since a part of the routine to be debugged is replaced with another instruction, there is a problem in that it is impossible to debug software stored in ROM.

By storing break point information in a memory different from the main memory, the present invention allows break points to be set at any address, which was necessary in the conventional method. The purpose of the present invention is to provide a debugging method that eliminates the need for a register to store the data itself and an address comparator for address comparison, and also enables debugging of software stored in a ROM.

(Means for Solving the Problems) The system of the present invention includes a processor that performs data processing, a first storage unit that stores information including data and programs used for the data processing, and a first storage unit that stores information including data and programs used for the data processing. a second storage means that has the same address space as the storage means and stores special information; and memory access information supplied from the processor and special information supplied from the second storage means. a detection means for detecting a match of a predetermined condition; memory access information when the processor accesses the first storage means while executing the program; and an address to which the first storage means was accessed; and the special information of the second storage means stored at the same address is detected by the detection means, and the process is performed.

will be notified and configured.

(Operation) The present invention stores information regarding break points in the main
The break information is stored in a separate memory, and each time the main memory is accessed, the break information memory is read at the same time, and when the break information is read, the process is interrupted and the break point is processed. By starting the routine, the play coupon function is realized.

(Example) Next, an example of the present invention will be described with reference to the drawings.

Referring to FIG. 1, one embodiment of the present invention
Unit (PtJ)1. Main memory unit (M
MU′)2. Memory controller (MC)3. Break point memory (BPM) 4, condition match detection (9)
) road (CJC) 5. In addition, between each of the above blocks, there is an address bus 11 e and an address bus 12.
．． Control bus 13. Main memory control signal 14° break point memory write signal 15° break point memory output signal 16 and interrupt request signal 17 are connected.

FIG. 3 is a more detailed diagram of the processor unit 1. From processor unit 1 there is an address bus 11.
A control bus 13 is connected for output, and a data bus 12 is connected for inputting and outputting commands and data. The address bus 11 and data bus 12 are composed of a plurality of lines depending on the address space and the data length.

The control bus 13 includes a memory IJ-)” signal (MRD) 131 and a memory write signal (MWR) 13.
2. Consists of input/output device read signal (l0RD) 133° and input/output device i write signal (l0WR) 134,
It controls the transmission and reception of instructions and data between the processor unit 1 and memory and input/output devices. Interrupt request signal (IN
When T) 17 becomes active', the processor □ unit 1 interrupts the running 10gram and starts an interrupt processing routine. □ Figure 2 shows the memory controller 3. The memory controller 3 controls reading and writing of the main memory unit 2 and writing of break point information to the break point memory 4. That is, when the program is normally executed, the output 200 of the D flip-flop (DF/F) 31 is 0, and when the memory write signal 132 becomes active, the AN
The main memory write signal (MMWR) i 42, which is the output of the D gate 35, becomes active and the data on the data bus 12 is written to the main memory unit 2.

When setting break point information to the break point stand memory 4, set the output 200 of the D flip-flop 31 to 1, and when all memory writes are performed, the break point memory write signal (BPMWR) 1 is set.
5 becomes active and break point memory 4
The data on data bar 9 = bar 12 is written. Therefore, before running the software to be debugged, D flip-flop 3
Write break point information to the address where you want to break in the break point memory 4, reset the D flip-flop 31 to 0, and then execute the software to be debugged. Follow the steps.

The D flip-flop 31, which determines whether to write the main data of the data bus 12 to the main memory e unit 2 or the break point memory 4, is a processor.
It exists in the bus 10 space of the bus unit 1, and the data on the data bus 12 is set when both the address decoder (DEC) 32 and the input/output device write signal 134 become active. Therefore, when writing data to break point memory 4, D2 lip-flop 31
Execute an instruction to set .

FIG. 7 shows a timing chart showing the above operation. In the main memory write cycle■, D flip
The output 200 of the flop 31 is 0 and 110-, and the memory write signal 132 passes through the AND gate 35 to become the main memory write signal 142. This is a normal memory write cycle.

The next three cycles are the write sequence to break point memory 4. In the set cycle (3) of the D flip-flop 31, the data on the data bus 12 is written to the D flip-flop 31, and the output 200 of the D flip-flop 31 becomes 1. The next cycle is the break information writing cycle to the break point memory. In this cycle, processor unit 1 executes a normal memory write cycle. The address at which you want to set a break point is output to the address bus 1, and the data own bus 12
Break information is output. The memory write signal 132 outputted by the processor unit 1 passes through the AND gate 34 and becomes the break point φ memory write signal 15, and data is stored in the break point memory.
Break information on the bus is written. And the next D
In the flip-flop 31 reset cycle ■, the data on the data bus 12 is transferred to the D flip-flop 31.
The output of D flip-flop 31 is 200.
is 0.

Furthermore, when the processor instruction unit 1 reads the main memory unit 2, the memory read signal 13
1 becomes active. This signal 131 directly becomes a main memory read signal (MRD) 141, and the main memory unit 2 outputs the contents of the address specified by the address bus 11 to the data bus 12.

In FIG. 4, the main memory unit 2 is shown. An address bus 11 from the processor unit 1 is connected, and data is read from and written to the memory at an address specified by the address bus 11.

Read and write are determined by a main memory read signal 141 and a main memory write signal 142 output from the memory controller 3.

FIG. 5 shows the break point memory 4. Break point memory 4 has an address space the same size as that of main memory unit 2. The data width of the break point memory 4 varies depending on the break point condition. In other words, if a break is simply to occur when a specified address is accessed, a width of 1 bit is sufficient. On the other hand, multiple bit widths are required to break depending on the type of access such as instruction fetch, data read, and data write.

The required break point memory bit width is
Depends on the number and combination of breakpoint conditions. In other words, if it is possible to have multiple access conditions, it is necessary to allocate one bit to each access condition. Alternatively, if access conditions are required, the number of break point memories can be reduced by 40 bits by encoding the break conditions.

In this embodiment, a case will be described in which break points can be set separately for two types of memory self-read and memory write. Break-point memory 4 therefore has a width of 2 bits. It is assumed that memory read break information is stored in the i-th bit, and memory write break information is stored in the second bit.

The break point memory write signal 15 output from the memory controller 3 causes the data bus 1 to
The data on 2 is written to break point memory 4. Like the main memory 2, the address fist 11 is connected to the break point memory 4,
When main memory unit 2 is accessed while processor unit 1 is executing the software to be debugged, the contents of break point memory 4 at the same address are read, and in response to a memory read at that address. If a break point is set, output 161 of the first bit of break point memory 4 becomes active, and if a break point is set for a write, the output 161 of the first bit of break point memory 4 becomes active. Bit output 162 becomes active.

FIG. 6 shows an example of the configuration of the condition-paper detection circuit 5. In this embodiment, there are two kinds of breaks: a break at memory read time and a break at memory write time, and a break condition match is detected from the type of memory access cycle and the output of the break point memory 4. In other words, break condition detection during memory read is performed using the memory read signal 13.
1 and the output 161 of the break point memory 4 is detected by the exclusive OR gate 51, and the break condition at the time of memory write is detected by the memory write signal 132 and the output of the break point memory 4. 162
An exclusive or gate 52 detects a match. Then, the logical sum of the outputs 51 and 52 of the two exclusive OR gates becomes the condition match signal, that is, the interrupt request signal 17.

Next, the operation of this embodiment will be explained.

It is necessary to store information in advance in the break point memory 4 for the address at which a break is desired. To do this, set the D flip-n-lop 31 in the memory controller 3 to 1, and then write data to the address where you want to break. If you want to break on memory read, write 1, if you want to break on memory write, write 2, and if you want to break on both memory read and write, write 3.

Processor unit 1. When a certain address in the main memory unit 2 is accessed while the program is being executed, the same address in the break point φ memory 4 is also read at the same time. At this time, the break point
If the memory output 161 or output 162 is active, a break point has been set at this address.

At this point, if the break condition matches whether this memory access is a memory read or a memory write and the break point memory outputs 161 and 162, the interrupt request signal 17 becomes active and the processor
An interrupt is requested to unit 1, the program being executed is interrupted, and a break point processing routine is started.

In the above, we have described an example in which a break occurs in response to two types of memory access: memory read and memory write. However, depending on the processor, information regarding memory access may include instruction fetch, data read, data, write, stack, and read. , stacked write, user mode,
There are supervisor modes, etc. Setting a break point in response to each access can be easily done by increasing the bit width of the break point memory and changing the condition/paper detection circuit.

(Effects of the Invention) The present invention has a feature that an arbitrary number of break points can be set by storing break point information in a memory different from the main memory at a location corresponding to a break point address. effective.

Furthermore, if a bit width of the memory for storing breakpoint information and a condition/paper detection circuit are required, breakpoints can be set according to the type of memory access.

Furthermore, since the break point function realized by the present invention stores break point information in a memory separate from the main memory, there is also the effect that software stored in ROM can be debugged.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention, FIG. 2 is a more detailed block diagram of the memory controller shown in FIG. 1, and FIG. 3 is a more detailed block diagram of the processor unit shown in FIG. 4 is a more detailed block diagram of the main memory unit shown in FIG. 1; FIG. 5 is a more detailed block diagram of the break point memory shown in FIG. Figure 6 is a more detailed diagram of the paper detection circuit under the conditions shown in Figure 1, Figure 7 is a timing diagram of data writing to the main memory unit and break point memory, and Figure 8 is a more detailed diagram of the paper detection circuit. FIG. 2 is a block diagram showing a conventional example. 1...Processor unit) (PU), 11.
...Address bus (5), 12...Data...
Bus ([), 13... Control bus, 1
31...Memory read signal (MRD), 13
2...Memory write signal (MWR), 133
...Input/output device read signal (IORD), 13
4...Input/output equipment/write signal (IOWR),
14... Main memory control signal,
141... Main fist memory read signal (MM
RD), 142...Main memory write signal (MMWR), 15...Break point memory write signal (BPMWR,), 16...
...Break point mesori output signal, 161...
...First break point memory output, 16
2...Memory output of second break point, 17...Interrupt request signal (INT), 2...
...Main Memory Uni, ) (MMU), 3.
... Mesori Controller (MC), 31...
D flip-flop (D F/F), 32...
・Address decoder (DEC), 33...
AND gate, 34...AND gate, 3
5...AND gate, 36...NO
T gate, 4... Break point memory (BPM), 5... Condition-Paper unloading circuit (CJ
C), 51... Exclusive OR gate, 52... Exclusive OR gate, 53... Negative BN input Kaor gate, 1001
...Processor Units) (PU), 1002
...Main memory unit (MMU), 1
003...Break point address register (ADH8RG), 1004...Address comparison i (CMP), 1011...Address
Bus, 1012...Data bus, 1013...
...Control bus, 1014...
Break own point address register output, 101
5...Condition match signal. ~C-Procedure, MiscellaneousC＼＼＼＼＼＼＼N Procedural amendment (voluntary) 1. Display of incident 1982 Patent application No. 26036
No. 8 No. 2, Title of the invention Debugging method 3, Relationship with the person making the amendment Applicant: 5-33-1-4, Shiba 5-chome, Minato-ku, Tokyo, Agent: 5-37-8 Shiba, Minato-ku, Tokyo 108 Sumitomo Sanda Building NEC Co., Ltd. 5, "Detailed Description of the Invention" column 6 of the specification to be amended, page 13, line 18 of the details of the amendment wi Correct to "If not."

Claims (1)

[Scope of Claims] A processor that performs data processing, a first storage unit that stores information including data and programs used in the data processing, and a processor that has the same address space as the first storage unit. a second storage means for storing special information; and a detection means for detecting a match between a predetermined condition from the memory access information supplied from the processor and the special information supplied from the second storage means. and memory access information when the processor accesses the first storage means while executing the program, and the memory access information stored at the same address as the accessed address of the first storage means. 2. A debugging method characterized in that the detecting means detects a match between the condition and the special information stored in the storage means of No. 2 and notifies the processor.