JPH05108550A - Central processing unit - Google Patents

Abstract

PURPOSE:To observe a program operating state for an arbitrary period as the locus of executing a program without using any exclusive equipment. CONSTITUTION:A write control circuit 9 compares a previously set starting address with the state of an internal address bus AB. When the set starting address is coincident with address data on the internal address bus AB, the control circuit 9 starts outputting a write timing signal WR and during a period set in advance, the timing signal WR is continuously outputted. When the control circuit 9 outputs the timing signal WR, first and second storage circuits 10 and 11 respectively write the state of an internal data bus DB and the state of the internal address bus AB in the internal parts of those storage circuits for that period and preserve those states. Afterwards, when the control circuit 9 stops outputting the timing signal WR, the bus states preserved in the storage circuits 10 and 11 can be read out by a program for debugging.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a central processing unit which constitutes a computer system.

[0002]

2. Description of the Related Art Generally, a computer system, as shown in FIG. 2, has a central processing unit 1 mainly having a computing function as a computer system and a control function for various devices, and a main storage device for storing programs and data. 2 and an input / output device 3 that controls input / output of data to / from the outside of the computer system.

As shown in FIG. 3, the central processing unit 1 includes an arithmetic logic circuit 4 for executing actual arithmetic operations and logical operations as a central processing unit, and an instruction decoding for decoding a program executed by the central processing unit. The circuit 5 and the timing control circuit 6 for controlling various timings and circuits based on the result of decoding the instruction by the instruction decoding circuit 5.
And a program counter 7 for managing the sequential access operation of programs stored in the main memory 2, and a general-purpose register group 8 for temporarily storing the processing result in the central processing unit.

The arithmetic logic circuit 4, the instruction decode circuit 5, and the general-purpose register group 8 are connected to an internal data bus DB of the central processing unit, and the internal data bus DB is shown in FIG. 2 through a data bus buffer (not shown). It is connected to the external data bus ODB shown. Also,
The program counter 7 and the general-purpose register group 8 are each connected to the internal address bus AB of the central processing unit, and the internal address bus AB is connected to the external address bus OAB shown in FIG. 2 through an address bus buffer (not shown). .. On the other hand, the timing control circuit 6 generates various timing control signals based on the instruction decode signal SD output from the instruction decode circuit 5, and the external control shown in FIG. 2 through the internal control bus CB and a control bus buffer (not shown). Bus OCB
It is connected to the.

Next, the operation of the central processing unit thus constructed will be described. The output of the program counter 7 is supplied to the main memory device 2 through the address buses AB and OAB, and the program read control signal from the timing control circuit 6 is supplied to the main memory device 2 through the control buses CB and OCB. According to the address information and the read control, the corresponding instruction is read from the main storage device 2 and input to the instruction decoding circuit 5. This instruction is decoded by the instruction decode circuit 5, the operation corresponding to the instruction is determined, and the information is used as the instruction decode signal S.
It is input to the timing control circuit 6 as D. The timing control circuit 6 controls the actual operation of various circuits according to the instruction decode signal SD. For example, when a data read operation from the main memory device 2 is required, the address information and the data read control signal for the data are supplied to the main memory device 2 so that the data required by the main memory device 2 can be obtained. It is read into the central processing unit 1. Further, when the arithmetic processing is required, the data necessary for the arithmetic processing is set in the arithmetic logic circuit 4, and the required processing and the timing of the processing are controlled.

The operation cycle of the central processing unit 1 for one instruction is generally called a machine cycle.

As described above, the central processing unit 1 executes the program operation required by the program stored in the main memory 2 by sequentially executing the machine cycle operation according to the program.

In such a conventional central processing unit, the state of program operation of the central processing unit has been observed by the following method for the purpose of debugging the program. (1) Address bus and data bus outside the central processing unit,
Also, the behavior of each bus of the control bus is observed by a dedicated device (in-circuit emulator, logic state analyzer, etc.). (2) A program for program debugging is installed inside the program executed by the central processing unit, and the operating state of the program is observed without using special equipment.

[0009]

However, these methods for observing the program operating state of the central processing unit have the following disadvantages.

That is, the method (1) requires a dedicated device as described above. Since the device itself is required to have high speed, the device is relatively large. Therefore, this method is suitable for the debugging stage at the early stage of program development, but is not suitable for observing the actual program operating state of the entire computer system.

On the other hand, in the method (2), what is observable is that the central processing unit executes the memory content as a result of the actual program operation or the predetermined portion of the program preset by the debug program. It is only whether or not, and the operating state of the program cannot be observed as an actual execution locus.

An object of the present invention is to eliminate such drawbacks and provide a central processing unit capable of observing a program operating state in an arbitrary period as a program execution locus without using a dedicated device. Especially.

[0013]

According to the present invention, in a central processing unit constituting a computer system, an internal address bus for connecting a first component, an internal data bus for connecting a second component, and a designation are specified. A write control circuit that outputs a predetermined timing signal for a specified period from a specified timing, and a first memory that writes the state of the internal data bus during the period when the write control circuit outputs the timing signal. A circuit and a second memory circuit for writing the state of the internal address bus while the write control circuit is outputting the timing signal.

[0014]

Embodiments of the present invention will now be described with reference to the drawings. FIG. 1 is a schematic block configuration diagram showing an example of a central processing unit according to the present invention. It is assumed that this central processing unit constitutes a computer system in which the central processing unit 1 in FIG. 2 is replaced by the central processing unit of this embodiment.

This central processing unit includes an arithmetic logic circuit 4 for executing actual arithmetic operations and logical operations as the central processing unit, an instruction decoding circuit 5 for decoding a program executed by the central processing unit, and an instruction decoding circuit. 5, a timing control circuit 6 for controlling various timings and various circuits based on the result of decoding the instruction by the program 5, a program counter 7 for managing a sequential access operation of a program stored in the main memory 2, and a central processing unit. General-purpose register group 8 for temporarily storing the processing result, and a write control circuit 9 for generating a write timing signal WR for a predetermined period based on predetermined information set in advance.
And the write control circuit 9 causes the write timing signal WR
And the write control circuit 9 for sequentially writing the state of the internal data bus DR during the period
Is generating the write timing signal WR,
It comprises a second memory circuit 11 for sequentially writing the state of the internal address bus AB.

The arithmetic logic circuit 4, the instruction decode circuit 5, and the general-purpose register group 8 are connected to an internal data bus DB of the central processing unit, and the internal data bus DB is shown in FIG. 2 through a data bus buffer (not shown). It is connected to the external data bus ODB shown. Also,
The program counter 7 and the general-purpose register group 8 (?)
Each is connected to the internal address bus AB of the central processing unit, and the internal address bus AB is connected to the external address bus OAB shown in FIG. 2 through an address bus buffer (not shown).
It is connected to the. On the other hand, the timing control circuit 6 generates various timing control signals based on the instruction decode signal SD output from the instruction decode circuit 5, and the external control shown in FIG. 2 through the internal control bus CB and a control bus buffer (not shown). It is connected to the bus OCB. In addition, the write control circuit 9
Is connected to the internal data bus DB and the internal address bus AB, generates the write timing signal WR, and supplies the write timing signal WR to the first memory circuit 10 and the second memory circuit 11.
In the first storage circuit 10, the state of the internal data bus DB is maintained during the period in which the data input unit and the data output unit are connected to the internal data bus DB and the write control circuit 9 outputs the write timing signal WR. Can be sequentially written and saved, and the saved contents can be read out at any timing. On the other hand, in the second memory circuit 11, the data input section is connected to the internal address bus AB, and the data output section is connected to the internal data bus DB. Then, while the write control circuit 9 is outputting the write timing signal WR, the state of the internal address bus AB can be sequentially written and saved, and the saved contents can be read at an arbitrary timing.

Next, the operation will be described. Since the normal operation of the central processing unit is the same as that of the conventional central processing unit, its explanation is omitted here. Hereinafter, operations related to the write control circuit 9 and the first and second memory circuits 10 and 11, which are the features of the central processing unit of this embodiment, will be described. In the present embodiment, it is assumed that a program for program debugging is incorporated in the program executed by the central processing unit as in the case of the conventional debugging method (2).

First, the program debug program sets in advance the write control circuit 9 with the start address of the program whose operation state is to be observed and the information of the period (the number of steps of the program) to be observed.

Thereafter, the write control circuit 9 compares the set start address with the state of the internal address bus AB. Then, when the set start address and the address data on the internal address bus AB match, the write control circuit 9 starts outputting the write timing signal WR, and writes during the set period. The timing signal WR is continuously output. When the write control circuit 9 outputs the write timing signal WR, the first and second memory circuits 10 and 11 store the state of the internal data bus DB and the state of the internal address bus AB in the memory circuit during that period. Write and save.

After that, when the write control circuit 9 stops the output of the write timing signal WR, the state of the bus stored in each of the first and second memory circuits 10 and 11 is read by the program for program debugging. Is possible.

The first and second memory circuits 10,
Read the state of the bus stored in 11 respectively,
By displaying them on the display device as a part of the input / output device 3, the actual execution locus of the program can be observed.

[0022]

As described above, according to the present invention, in the central processing unit constituting the computer system, the internal address bus connecting the first component and the internal data bus connecting the second component, From the specified timing,
A write control circuit that outputs a predetermined timing signal for a designated period, a first storage circuit that writes the state of the internal data bus during the period when the write control circuit outputs the timing signal, and a write control circuit. A second memory circuit for writing the state of the internal address bus during the period of outputting the timing signal. Therefore, in the central processing unit of the present invention, it is possible to observe the program operating state in an arbitrary period as a program execution trajectory without using a dedicated device. As a result, it becomes possible to observe the actual program operation state of the entire computer system as direct information.

[Brief description of drawings]

FIG. 1 is a schematic block configuration diagram showing an example of a central processing unit according to the present invention.

FIG. 2 is a schematic block configuration diagram showing an example of a computer system configured by a conventional central processing unit.

FIG. 3 is a schematic block configuration diagram showing an example of a conventional central processing unit.

[Explanation of symbols]

 2 main memory device 3 input / output device 4 logical operation circuit 5 instruction decode circuit 6 timing control circuit 7 program counter 8 general-purpose register group 9 write control circuit 10 first memory circuit 11 second memory circuit AB internal address bus CB internal control Bus DB Internal data bus OAB External address bus OCB External control bus

Claims (3)

[Claims] 1. In a central processing unit constituting a computer system, an internal address bus for connecting a first component, an internal data bus for connecting a second component, and a designated timing are designated. A write control circuit that outputs a predetermined timing signal during a period; and a first write state that writes the state of the internal data bus during the period when the write control circuit outputs the timing signal.
And a second memory circuit for writing the state of the internal address bus while the write control circuit is outputting the timing signal. 2. The specified timing corresponds to the timing at which predetermined address data is output to the internal address bus, and the specified period corresponds to the number of address data output to the address bus. The central processing unit according to claim 1, characterized in that: 3. The first component includes a program counter, the write control circuit, and the second memory circuit, and the second component is an arithmetic logic circuit and a general-purpose register group. An instruction decode circuit, the write control circuit,
The central processing unit according to claim 1, comprising the first and second memory circuits.