JPH0619751A - Central processing unit - Google Patents

Abstract

PURPOSE:To observe a program operation state in a central processing unit as the operation locus of a program without using a private program debug unit and to observe an internal state at that time. CONSTITUTION:A read/write control circuit 9 outputs a write timing signal WR1 at the time of reading the program. Thus, a first and second storage circuits 10 and 11 store the contents of an internal data bus DB and an internal address bus AB. Then, the read/write control circuit 9 sequentially outputs a read timing signal RD to respective registers constituting a general-purpose register group 8 and outputs a write timing signal WR2 synchronized with a read timing signal RD. Thus, the contents of the respective registers constituting the general-purpose register group 8 are stored in a third storage circuit 12.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a central processing unit which is a main constituent element in a computer system, and a central processing unit capable of observing an operating state of a program as an actual execution locus without using special equipment. Regarding a processing device.

[0002]

2. Description of the Related Art Generally, a computer system, as shown in FIG. 3, has a central processing unit 1 having an arithmetic function and a control function for various devices, a main storage unit 2 for storing programs and data for the computer system, and a computer. The input / output device 3 controls input / output of data to / from the outside of the system.

As shown in FIG. 4, the conventional central processing unit 1 includes an arithmetic logic circuit 4 for executing arithmetic operations, logical operations, etc., an instruction decoding circuit 5 for decoding a program for the central processing unit 1, and an instruction. A timing control circuit 6 for executing various timings and control of various circuits based on a result of decoding the instruction by the decoding circuit 5, and a main memory device 2.
It comprises a program counter 7 for managing the sequential access operation of the programs stored therein, and a general-purpose register group 8 serving as a temporary storage area for the processing result in the central processing unit 1.

The logical operation circuit 4, the instruction decoding circuit 5, and the general-purpose register group 8 are each connected to an internal data bus DB in the central processing unit 1, and the internal data bus DB is shown in FIG. It is connected to the external data bus ODB shown in FIG.

The program counter 7 and the general-purpose register group 8 are connected to the internal address bus AB of the central processing unit 1, and the internal address bus AB is connected to the external address bus OA shown in FIG. 3 via an address bus buffer (not shown).
Connected to B.

The timing control circuit 6 generates various timing control signals based on the instruction decode signal SD output from the instruction decode circuit 5, and includes an internal control bus CB and a control bus buffer (not shown). It is connected to the external control bus OCB shown in FIG.

Next, the actual operation of the central processing unit thus configured will be described.

The output of the program counter 7 is supplied to the main memory device 2 via the internal address bus AB and the external address bus OAB, and a program read control signal is sent from the timing control circuit 6 to the internal control bus C.
It is supplied to the main memory device 2 via B and the external control bus OCB.

According to the address information and the program read control signal, the corresponding instruction is read from the main memory 2 and input to the instruction decoding circuit 5.

This instruction is decoded by the instruction decode circuit 5, and an instruction decode signal SD indicating the operation corresponding to the instruction is supplied to the timing control circuit 6.

The timing control circuit 6 controls the actual operation of various circuits according to the instruction decode signal SD.

For example, when a data read operation from the main storage device 2 becomes necessary, the address information of the data and the data read control signal are supplied to the main storage device 2 so that the main storage device 2 can perform the operation. Data to be read into the central processing unit 1. When the arithmetic processing is required, the data necessary for the arithmetic processing is set in the arithmetic logic circuit 4 and the required processing and the timing of the processing are controlled.

The operation cycle of the central processing unit 1 for one instruction is generally called a machine cycle.

As described above, by sequentially executing the machine cycle operations according to the program, the central processing unit 1 executes the operation requested by the program stored in the main memory 2.

By the way, in the computer system using the conventional central processing unit shown in FIG. 4, the following method is used to observe the operating state of the program.

(1) Observation of bus state movements of the external address bus OAB, external data bus ODB, and external control bus OCB outside the central processing unit with dedicated equipment (in-circuit emulator, logic state analyzer, etc.) A method of observing the program operating state of the central processing unit by performing.

(2) A method of observing a program operating state on a central processing unit without using a special device by incorporating a program for program debugging into a program executed on the central processing unit.

Further, in order to observe the internal state of the central processing unit (contents of general-purpose register group, etc.), the following method is adopted.

(3) A method of stopping the central processing unit itself by executing a break instruction, a single step instruction, etc., and reading and observing the internal state of the central processing unit at that time.

[0020]

[Problems to be Solved by the Invention] However, (1)
Each of the conventional techniques described in (3)-(3) has the following problems.

In the conventional technique using the dedicated device shown in (1), the device is required to have high speed, and the device itself becomes relatively large. Therefore, the device is connected to an actually operating computer system. Difficult to do. Therefore, the conventional technique shown in (1) is suitable for the initial debugging stage of program development, but is not suitable for observing the program operating state in a computer system that is actually operating. is there.

In the conventional technique shown in (2), the memory contents as the operation result of the program are confirmed, and whether the central processing unit has executed an arbitrary portion of the program (which can be set by the debug program). However, there is a problem that the operating state of the program cannot be observed as an actual execution locus.

In the conventional technique shown in (3), since it is necessary to stop the operation of the target central processing unit at the time when it is desired to observe, it is necessary to read the internal state of the central processing unit. Will be affected by the stop. Therefore, the conventional technique shown in (3) has a problem that it is not suitable for observing the central processing unit in the real-time processing operation state.

An object of the present invention is to provide a central processing unit capable of observing an operating state of a program as an actual execution locus and observing an internal state at that time without using a special device. To provide.

[0025]

In order to achieve the above object, the present invention provides a program stored in a main memory device as a data by supplying the value of a program counter to the main memory device via an address bus. In a central processing unit that reads and executes via a bus, at the time of reading a program, it outputs a first write timing signal, and then sequentially outputs a read timing signal to each element holding the internal state. And its contents are output to the data bus, and a read / write control circuit that outputs a second write timing signal synchronized with the read timing signal; and data on the data bus according to the first write timing signal are stored. A first memory circuit and the address buffer according to the first write timing signal. A second memory circuit for storing the above address; and a third memory circuit for storing the contents of each element holding the internal state output onto the data bus in accordance with the second write timing signal. Is provided.

[0026]

When the program is read, the read / write control circuit first outputs the first write timing signal.

As a result, the data (instruction) on the data bus is stored in the first storage circuit, and the address (the address from which the instruction is read) on the address bus is stored in the second storage circuit.

After that, the read / write control circuit sequentially outputs the read timing signal to each element such as a general-purpose register which holds the internal state to output its contents to the data bus, and is synchronized with the read timing signal. The second write timing signal is output.

As a result, the internal state such as the value of the general-purpose register is stored in the third storage circuit.

[0030]

Embodiments of the present invention will now be described in detail with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention, showing an example of the configuration of the central processing unit 1 of FIG.

As shown in FIG. 4, the central processing unit 1 is shown in FIG.
Similar to the conventional central processing unit 1 shown in FIG. 1, an arithmetic logic circuit 4, an instruction decoding circuit 5, and a timing control circuit 6
And a program counter 7.

Further, the central processing unit 1 of this embodiment has a read / write control circuit 9 and first to third storage circuits 10 to 10.
12 and.

The read / write control circuit 9 is connected to the internal data bus DB and the internal address bus AB, and after the start address set by the debugging program via the internal data bus DB appears on the internal address bus AB. Write timing signal WR to the first and second memory circuits 10 and 11 each time a program read control signal is output from the internal control bus CB.
1 and then sequentially outputs the read timing signal RD to each register constituting the general-purpose register group 8 and outputs the write timing signal WR2 synchronized with the read tamming signal RD to the third memory circuit 12. The process of doing is performed. This process is executed the number of times set by the debug program.

Each time the registers forming the general-purpose register group 8 receive the read timing signal RD from the read / write control circuit 9, the contents of the registers are stored in the internal data bus D.
Output to B.

The first memory circuit 10 has a data input section and a data output section connected to the internal data bus DB, and each time the write tamming signal WR1 is applied, the contents of the internal data bus DB at that time are stored. The data is stored in order from the start address. Further, the storage contents of the first storage circuit 10 can be read out via the internal data bus DB.

In the second memory circuit 11, the data input section is the internal address bus AB and the data output section is the internal data bus D.
Each time the write timing signal WR1 is applied, the contents of the internal address bus AB at that time are stored in order from the head address. Further, the storage contents of the second storage circuit 11 can be read out via the internal data bus DB.

In the third memory circuit 12, the data input section and the data output section are connected to the internal data bus DB, and every time the write timing signal WR2 is applied, the contents of the internal data bus DB at that time are stored. The data is stored in order from the start address. Here, the write timing signal WR2
Is synchronized with the read timing signal RD, and at the time when the write timing signal WR2 is output,
Since the contents of one of the registers forming the general-purpose register group 8 are output to the internal data bus DB, the contents of each register forming the general-purpose register group 8 are stored in the third storage circuit 12. Will be stored. Further, the contents stored in the third storage circuit 12 are the internal data bus D.
It is possible to read through B.

FIG. 2 is a timing chart of this embodiment. The operation of this embodiment will be described below with reference to the drawings.
Incidentally, the normal operation of the central processing unit 1 is the same as that of the conventional central processing unit shown in FIG.
Here, only the operation of the read / write control circuit 9, the first to third memory circuits 10 to 12 and the operation of the general-purpose register group 8 newly added in this embodiment will be described. Also,
In this embodiment, it is assumed that the program executed on the central processing unit 1 also includes a debugging program.

First, the start address for starting the observation of the operating state and the number of steps (period) for performing the observation are set in the read / write control circuit 9 using the debug program.

After that, when the start address set on the internal address bus AB appears, the read / write control circuit 9 causes the timing control circuit 6 to move to the internal control bus C.
Each time the program read control signal is output to B, the following processing is performed.

As shown in FIG. 2, the read / write control circuit 9 outputs the program read control signal from the timing control circuit 6 to the internal control bus CB.
The write timing signal WR1 is output to the first and second memory circuits 10 and 11 at the timing when the data Dn appears on the internal data bus DB.

As a result, the first memory circuit 10 stores the data Dn on the internal data bus DB, and the second memory circuit 11 stores the address An on the internal address bus AB.

Next, the read / write control circuit 9 sequentially outputs the read timing signal RD to the i registers constituting the general-purpose register group 8 and outputs the write timing signal WR2 synchronized with the read timing signal RD to the third register. Output to the memory circuit.

As a result, the contents R1 to Ri of the i registers constituting the general-purpose register group 8 are sequentially output to the internal data bus DB, and the contents R1 to Ri of each register output to the internal data bus DB are sequentially output. Third memory circuit 1
Stored in 2.

The above operation is performed for the number of steps set by the debug program.

Then, the first to third storage circuits 10 to 12
When the data and addresses corresponding to the number of steps specified in are stored, the debug program is stored in the first to third storage circuits 1.
It is instructed to read the contents of 0 to 12 and display the read contents on a display device such as a display device. As a result, the first to third units are connected via the internal control bus CB.
A read timing signal is added to the memory circuits 10 to 12, and the data and address read by the read timing signal are displayed on the display device. It becomes possible to observe the internal state (contents of general-purpose register group, etc.).

[0048]

As described above, according to the present invention, the first write timing signal is output to the first and second memory circuits at the time of program reading, and the data bus at that time is output to the central processing unit. Store the contents of the address bus,
Furthermore, the read timing signal is output to output the contents of an element such as a general-purpose register that holds the internal state to the data bus, and the second write timing signal synchronized with the read timing signal is output to output the third write timing signal. Since the memory circuit is provided with the read / write control circuit for storing the contents of the general-purpose registers output to the data bus,
There is an effect that it is possible to observe the operation state of the program as a movement trajectory of the program without using special equipment, and it is possible to observe the state inside the central processing unit at that time. .

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a timing chart of an example.

FIG. 3 is a block diagram showing a configuration example of a computer system.

FIG. 4 is a diagram showing an example of a conventional central processing unit.

[Explanation of symbols]

 1 ... Central processing unit 2 ... Main memory unit 3 ... Input / output unit 4 ... Arithmetic logic circuit 5 ... Instruction decoding circuit 6 ... Timing control circuit 7 ... Program counter 8 ... General-purpose register group 9 ... Read / write control circuit 10 ... First Storage circuit 11 ... Second storage circuit 12 ... Third storage circuit AB ... Internal address bus DB ... Internal data bus CB ... Internal control bus SD ... Instruction decode signals WR1, WR2 ... Write timing signal RD ... Read timing signal OAB ... External address bus ODB ... External data bus OCB ... External control bus

Claims (2)

[Claims] 1. A central processing unit for supplying a value of a program counter to a main memory device via an address bus to read a program stored in the main memory device via a data bus and execute the program. When reading a program, a first write timing signal is output, and then a read timing signal is sequentially output to each element holding an internal state to output the contents to the data bus and the read timing. A read / write control circuit that outputs a second write timing signal synchronized with the signal, a first storage circuit that stores data on the data bus according to the first write timing signal, and the first write timing signal A second memory circuit for storing an address on the address bus according to Central processing unit characterized by comprising a third storage circuit for storing the contents of the elements holding the internal state which is output onto the data bus in accordance with the second write timing signal. 2. The central processing unit according to claim 1, wherein the element holding the internal state is a general-purpose register.