JPH04102934A - Microprocessor - Google Patents

Abstract

PURPOSE:To obtain a dynamic BT capable of using a counter as a pattern generator by allowing a microprocessor to execute a defined instruction as a substitute for an undefined instruction. CONSTITUTION:This microprocessor 101 is provided with an instruction decoding part 13 for decoding an instruction code inputted from the external, generating plural execution control signals, and if an instruction code is an undefined instruction, generating a logical NOT signal and a control means 15 for controlling whether the logical NOT signal is to be validated or invalidated in accordance with a test signal inputted from the external. In a test mode, the undefined instruction is executed as a NOP instruction. Consequently, the microprocessor capable of using the counter 17 as the pattern generator can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to microprocessors, and more particularly to test circuits for microprocessors.

[Conventional technology]

One of the accelerated IC reliability tests is the Guinamic Hearn-in Test (hereinafter referred to as Dynamic BT). This means that the IC being tested is exposed to high power supply voltage and high ambient temperature.
A test pattern is applied to the external terminals of an IC, the internal parts are operated, and defects in the IC that would not occur for several decades under normal operating conditions can be caused in a few hours.

By selecting and shipping ICs that have undergone dynamic BT, the reliability of the ICs can be guaranteed over a long period of time.

In general, dynamic BT is more effective by operating a wider area of the TC under test at a higher frequency.

By the way, there are various methods for generating test patterns to be applied to the IC under test in dynamic BT.
An inexpensive method is to use a binary counter as a pattern generator.

FIG. 4 is a block diagram showing an example of a conventional microprocessor dynamic BT used as a binary counter and a pattern generator. The output from data terminal 24 of binary counter 17 is input to data terminal 21 of microprocessor 11, and the same clock φ is input to clock terminals 25 and 22 of binary counter 17 and microprocessor 11, respectively. The microprocessor 11 has a fixed-length instruction code of n bits, and its interior includes a data buffer 12 and an instruction decoder 1.
There are three blocks: 3 and an instruction execution unit 14. The data on the data terminal 21 is input to the data buffer 12,
Data output from the data buffer 12 is input to an instruction decoder 13.

An execution control signal 36 output from the instruction decoding section 13 and an NE signal 32 indicating undefined instruction decoding are input to the instruction execution section 14.

Next, the operation will be explained. The binary counter 17 is a counter that increments in synchronization with the clock φ, generates all n-bit binary codes, and outputs all n-bit binary codes to the data terminal 24.
Output from. Microprocessor 11 is connected to data terminal 2
1 into the data buffer 12. The code taken into the data buffer 12 is read by the instruction decoder 1
3 and decoded. As a result of the decoding, the instruction decoder 13 uses an execution control signal 36 to instruct the instruction execution unit 4 on what kind of processing to perform.
4 does it.

In this example, since the binary counter generates n binary codes over all combinations, all predefined instructions are executed by the microprocessor ]-1, so it is thought that almost the entire area of the microprocessor 11 will be executed. We can expect high effects in dynamic BT.

[Problem to be solved by the invention]

However, as mentioned above, since the binary counter 17 generates n-bit binary codes over all combinations,
Codes for undefined instructions will also be generated. The code is then input to the microprocessor 11, and the instruction decoder 13 that has decoded the undefined instruction makes all execution control signals 36 inactive and the NE signal 32 active. Start exception handling.

An exception is an event that occurs depending on the execution of a program, and processing is performed by a microprocessor depending on the event. Exception handling is performed as follows.

■Moving to privileged mode, ■Retrieving the vector of the corresponding exception from the system jump table, ■Storing information such as the program counter value when the exception occurred and the code of the exception that occurred in the stack, depending on the type of exception. , ■Start exception handling from the address pointed to by the previously extracted vector.

That is, the instruction decoding is restarted from ■, and since internal processing is performed for more than ten clocks from ■ to ■, the code generated by the binary counter 17 is discarded. FIG. 5 shows an instruction code map. In the diagram, upper and lower bits refer to the upper 4 bits and lower 4 bits of the instruction code.
Bits are expressed in hexadecimal notation. For example, an instruction code of 03 in hexadecimal notation is a NOT instruction. In the instruction code of FIG. 5, if the binary counter 17 does not generate the code 02 in hexadecimal notation, it is an instruction for which the instruction is not defined on the instruction map, that is, an undefined instruction, so it is not taken into the microprocessor 11. If this occurs, the exception handling described above is performed. During the internal processing period, the binary counter 17 is expressed in hexadecimal notation as 03, 04,
05°... is generated by the microprocessor 11. is discarded without being decoded because it is only used for internal processing. In other words, N.

T commands and OR commands are not executed. Similarly, the M○■ instruction is not executed.

Therefore, because some defined instructions are not executed, some areas of the microprocessor 11 do not operate.
It has not been possible to use a counter as a pattern generator in dynamic BT.

An object of the present invention is to provide a microprocessor that can use a counter as a pattern generator.

[Means to solve the problem]

The microprocessor of the present invention includes an instruction decoder that decodes an instruction code input from the outside, generates a plurality of execution control signals, and generates a logical negation signal when the instruction code is an undefined instruction; It is characterized by comprising a control means for controlling whether to enable or disable the logic negation signal in accordance with a test signal inputted from the logic negation signal.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing a binary counter and a dynamic BT of a microprocessor according to an embodiment of the present invention. The output of the data terminal 24 of the binary counter 17 is input to the data terminal 21 of the microprocessor 11,
The same clock φ or the respective clock terminals 25 and 2 of the binary counter 17 and one microprocessor
2 is entered.

The microprocessor 101 has a fixed length instruction code of n bits, and includes a data buffer 12 and an instruction decoder 1.
3, instruction execution unit 14, test circuit] 5, and has the two types of terminals described above and a test terminal 23.

The data input to the data terminal 21 is input to the data buffer 12, and the data output from the data buffer 12 is input to the instruction decoder 13.

The execution control signal 36 output from the instruction decoder 1-3 is input to the instruction execution unit 14 except for the NOP signal 34 requesting execution of a know operation (hereinafter referred to as NOP) instruction.
The NOP signal 34 and the NE signal 32 indicating undefined instruction decoding are input to the test circuit 15. Test circuit 15
In addition, a test signal 3] is inputted to the test terminal 23 through a test terminal 23, and an effective NOP signal 35 and an effective NE multiplied signal 3 are outputted. The circuit is an OR circuit that outputs the logical sum of one input, and an AND circuit that outputs the logical product of two inputs.
Contains circuits. The negative of the NE signal 32 and the test signal 31 is input to the first AND circuit, and the effective NE multiplied signal 3 is output from the first AND circuit. The NE signal 32 and the test signal 31 are input to the second AND circuit, and the second AN
The output of the D circuit and the NOP signal 34 are input to the OR circuit,
An effective NOP signal 35 is output from the OR circuit. Effective N
The OP signal 35 and the effective NE multiplication signal 3 are sent to the instruction decoder 14.
is input.

On the Naoki side, the execution control signal 36. NE signal 3
All of the signals 31 are active high signals.

Next, the operation will be explained. The binary counter 17 is a counter that increments in synchronization with the clock φ, and generates all n binary codes and outputs them to the data terminal 24.
Output from. The microprocessor 10 takes the code into the data buffer 12 via the data terminal 21.

The code taken into the data buffer 12 is sent to the instruction decoder 13 and decoded there. The subsequent operations differ between normal mode and test mode.

First, the normal code will be explained. When the test signal 31 is a logic “0” level (hereinafter referred to as low level),
The signal 31 is transmitted to the test circuit 15 via the test terminal 23, and the normal mode is set. In a normal mote, the NOP signal 34 is equal to the effective NOP signal 35,
The NE signal 32 becomes equal to the effective NE multiplied signal 3. If it is a code decoded by the instruction decoder 13 or a defined instruction,
The instruction decoder 13 makes the NE signal 32 inactive, and uses the execution control signal 36 to instruct the instruction execution section 14 to perform the following processing, and the instruction execution section 14 executes the instruction accordingly. If the code is an undefined signal, the execution control signal 36 is made inactive, the NE signal 32 is made active, and the instruction execution unit 14 that receives this starts exception processing. In other words, in normal mode, it operates in the same way as a conventional microprocessor.

Next, we will explain the test mode. Test signal 31
When is at the logic "1" level (hereinafter referred to as high level), a test signal is transmitted to the test circuit 15 via the test terminal 23, and the test mode is set.

The operation when the result decoded by the instruction decoding unit 13 is a defined instruction is the same as the operation in the normal mode. When the decoded result is an undefined instruction, all execution control signals 36 become inactive as in the normal mode, and
The NE signal 32 becomes active, but the NE signal 32 is masked by the test circuit, the effective NE multiplication signal 3 does not become active, and the effective NOP signal 35 becomes active, so an instruction to execute the NOP instruction is sent to the instruction execution unit 14. Given. As a result, the instruction execution unit 14 executes the NOP instruction.

In this manner, the microprocessor 101 of this embodiment executes undefined instructions as NOP instructions in the test mode.

FIG. 2 is a block diagram showing a dynamic BT of a microprocessor according to a second embodiment of the present invention using a binary counter. The overall configuration is almost the same as the first embodiment, but in this embodiment, there is no execution control signal 36 input directly from the instruction decoding section 13 to the instruction execution section 14, and all of the execution control signals 36, NE signal 32 and test signal 3
1 is input to the test circuit 16, and the test circuit 16 outputs an effective execution control signal 37 and an effective NE multiplication signal 3, which are input to the instruction execution unit 14. The test circuit 16 includes Lm OR gates, one AND gate, and a ring counter 18, the same number as the number of execution control signals 36 that instruct execution of a single instruction.

An operation time chart of the ring counter 18 is shown in FIG. When CE is at low level, Ql, Q2, ・
..., Q□ are all at low level.

On the other hand, when CE is at high level, only Ql becomes high level at the first high level of T after CE becomes high level, then T becomes low level, and Ql
becomes low level. Next high level of T, this time Q2
Q2 goes to high level, then T goes to low level and Q2 goes to low level.

Thereafter, the same operation is repeated until Qm, and at the next high level of T after Qm becomes high level, the process returns to the beginning and Ql becomes high level. The above is the operation of the ring counter 18.

The ring counter 18 has an NE signal 32 at its T input and a C
B large input test signal 31 is input, Ql, Q2 .・・・
・, Qm is output. Q+ of ring counter 18
, Q2 , ..., 9m outputs are input to m OR circuits, and one of each of the m execution control signals 36 is input to the other input of the OR circuit, and the output of the OR circuit are m effective execution control signals 37.

On the other hand, the negative of the NE signal 32 and the test signal 31 is input to an AND circuit, and the AND circuit outputs an effective NE multiplied signal 3.

Next, its operation will be explained. The method of setting the normal mode and the test mode, the operation in the normal mode, and the operation when a defined instruction is decoded in the test mode are the same as in the first embodiment, and therefore will not be described here. The operation when an undefined instruction is decoded in test mode will be explained. When the instruction decoder 13 decodes the undefined instruction, it makes all the execution control signals 36 inactive and makes the N and E signals 32 active. Since the effective NE multiplication signal 3 is masked by the test signal 31, it does not become active.

On the other hand, since the ring counter is in the test mode, a high level is input to CE, and since the NE signal 32 has become active, a high level is input to T, and as a result, Q1 becomes high level.

When Ql becomes high level, the first of m OR gates
The output of the OR circuit becomes active, that is, the first one of the effective execution control signals 37 becomes active. Therefore, the instruction execution unit 14 performs the execution instructed by the first effective execution control signal.

Next, when the undefined instruction is decoded again, Q2 of the ring counter 18 becomes high level, so the second OR
The output of the circuit, that is, the second one of the effective execution control signals 37 becomes active, and the instruction execution unit 14 executes the instruction thereof. Thereafter, each time an undefined instruction is decoded, each of the m effective execution control signals 37 becomes active one after another, and a different command execution instruction is given to the instruction execution unit 14 each time for execution.

In this embodiment, compared to the first embodiment, undefined instructions are
Because it is executed in place of all defined instructions, not just the instructions, microprocessor 1 is executed in test mode.
This has the effect that a wider area of 02 can be expected to operate more frequently.

〔Effect of the invention〕

As explained above, the present invention replaces undefined instructions with scheduled instructions and causes the microprocessor to execute them.
Dynamic B using a counter as a pattern generator
It has the effect of realizing T.

FIG. 1 is a block diagram of a microprocessor showing a first embodiment of the invention, FIG. 2 is a block diagram of a microprocessor showing a second embodiment of the invention, and FIG. 3 is a block diagram of a microprocessor showing a second embodiment of the invention. Waveform diagram for explaining the operation of the counter, No. 4
The figure is a block diagram of a conventional microprocessor, and FIG. 5 is a diagram showing an instruction code.

1]...Conventional microprocessor, 101°]02.
...Microprocessor of the present invention, 12.. Data buffer, 13.. Instruction decoding section, 14.. Instruction execution section, 1
5. :1.6...Test circuit, 17...Binary counter, 18...Ring counter, 21.24...
Data terminal, 22.25...Clock terminal, 23.Test terminal, 31...Nas 1~signal, 32...NE times signal 33...Effective NE times signal 34...NOP signal,
35... Effective NOP signal, 36... Execution control signal,
37...Effective execution control signal.

Claims (1)

[Scope of Claims] 1. An instruction decoder that decodes an externally input instruction code and generates a plurality of execution control signals, and also generates a logical negation signal when the instruction code is an undefined instruction;
A microprocessor comprising: control means for controlling whether to enable or disable the logical NOT signal according to a test signal input from the outside. 2. Claim 1, further comprising means for validating any one of the plurality of execution control signals each time the logical NOT signal is generated during a period in which the logical NOT signal is invalid.
Microprocessor as described.