JPH03201043A - Control signal generator - Google Patents

Abstract

PURPOSE:To detect the factor of a fault in a short time by providing a trace register which fetches the addresses produced by a sequencer in plural steps and stores the history of executed instructions. CONSTITUTION:A trace register 21 secures the cascade of registers 21A - 22C and applies the address signal outputted from a sequencer 11 to the register 21A of the first stage. Then the register 21 shifts successively the address signal to the registers 21B and 21C of the following stages synchronously with a clock CK. Therefore the address stored in the register 21B is equal to the address that read the executed instruction stored in a register 13. Then the addresses stored in the registers 21A - 21C can be taken out by a multiplexer 22. When a fault occurs, it is possible to specify a specific address where the fault is produced with execution of the executed instruction read out of said address by reference to the address stored in the register 21. In such a way, the factor of the fault is detected in a short time.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] This invention relates to a control signal generator that generates control signals in a predetermined order in order to operate various devices in a predetermined order.

"Prior Art" For example, in order to operate various devices such as IC test equipment in a predetermined order, various execution instructions are written in an instruction memory, and the execution instructions written in this instruction memory are sent to an address generated by a sequencer. The execution instructions are read out according to the instructions, and the read execution instructions are output to the execution unit to execute various operations.

FIG. 2 shows the configuration of a conventionally used control signal generator.

In the figure, reference numeral 10 indicates the entire control signal generator. The control signal generator 10 is composed of a sequencer 11, an instruction memory 12, a register 13, and an exception processing controller 14.

In the instruction memory 12, various execution instructions such as an addition operation processing routine and a comparison operation processing routine are written in blocks.

The sequencer 11 decodes the microcontrol instruction 15 included in the execution instruction read from the instruction memory 12, and outputs an address signal 16 in which an execution instruction to be executed next is written. This address signal 16 is applied to the instruction memory 12, and an execution instruction 17 to be executed next is read out.

The execution instruction 17 read from the instruction memory 12 is temporarily stored in the register 13, outputted to the control bus 18 in synchronization with clock clock CK, and sent to the execution unit 19.

When the exception processing controller 14 receives a signal Trap that detects the occurrence of a failure in the device, it gives a signal to the sequencer 11 that prompts the sequencer 11 to generate an address specifying an exception processing routine stored in the instruction memory 12.

The instruction memory 12 reads the exception handling routine according to the address given from the sequencer 11, outputs the exception handling instruction written in this exception handling routine through the register 13 to the control bus 1, and sends it to the execution unit 19.
Execute exception handling.

"Problem to be Solved by the Invention" When the conventional control signal generator 10 executes exception processing,
Since the execution instruction stored in the register 13 is rewritten to an exception handling execution instruction, it is not possible to refer to which instruction was executed in the state in which the failure occurred.

Therefore, it has the disadvantage that it takes a lot of time and effort to find the cause of the failure.

An object of the present invention is to provide a control signal that enables the user to know the address from which an execution instruction was read when a failure occurred and the address from which an execution instruction executed before the failure occurred, thereby allowing the cause of the failure to be found in a short time. It is intended to provide a generator.

"Means for Solving the Problems" The present invention includes an instruction memory in which various execution instructions are written, and a sequencer that stores addresses for reading out the execution instructions written in the instruction memory in a predetermined order. , a register that temporarily stores execution instructions read from the instruction memory and outputs them to the execution unit, and an exception handling controller that rewrites the execution instructions written in the register into exception handling instructions when a failure occurs and performs exception handling. In the control signal generator configured by, the address generated by the sequencer is captured in multiple steps,
It is characterized by a structure that includes a trace register that stores the history of executed instructions, and a multiplexer that selectively retrieves addresses stored in this trace register.

According to the configuration that characterizes the present invention, the address from which the execution instruction executed one step ago was read, the address from which the execution instruction currently being executed was read, and the execution instruction to be executed in the next step are read in the trace register. Memorize the address for sending.

Therefore, even if the execution instruction written in the register at the time of the failure is rewritten to an execution instruction that executes an exception handling routine, the trace register contains the address of the execution instruction executed one step before, and the current execution instruction. The address of the executing instruction being executed and the return address for returning from the exception handling routine are left.

Therefore, by referring to the address left in the trace register, it is possible to immediately determine which execution instruction was executed when a failure occurred, and the cause of the failure can be found in a short time.

"Embodiment" FIG. 1 shows an embodiment of the present invention. 1 shown in Figure 1
0 is a control signal generator, 11 is a sequencer, 12 is an instruction memory, 13 is a register, 14 is an exception handling controller, and 19 is an execution unit, which is the same as the configuration of the conventional technology explained in FIG. .

In the present invention, a control signal generator 1 having such a configuration is used.
0 is characterized in that it is provided with a trace register 21 that stores the history of addresses output by the sequencer 11, and a multiplexer 22 that arbitrarily takes out the history of the addresses stored in this trace register 21.

The trace registers 21 are three registers 21 in this example.
A, 21B, and 21C are connected in cascade, and the first stage register 21
The address signal output from the sequencer 11 is applied to A, and this address signal is sequentially shifted to the next stage registers 21B and 21C in synchronization with the clock CK.

Assuming that one step worth of execution instructions is stored in the register 13, the address stored in the trace register 21 has the following meaning.

In other words, the address currently accessing the instruction memory 12 resides in the register 21A, the address from which the execution instruction was read out one step ago resides in the register 21B, and the address from which the execution instruction was read out two steps ago resides in the register 21G. The address will be resident.

This means that the address stored in the register 21B is the address from which the execution instruction stored in the register 13 was read, and this is the address from which the execution instruction currently given to the execution unit 19 was read.

Further, the address stored in the register 21C is the address from which the execution instruction given to the execution unit 19 was read last time.

The addresses stored in the trace registers 21A to 21C are arbitrarily transferred to the data bus 23 by the multiplexer 22.
Configure it so that it can be taken out.

"Effect of the invention" If a problem occurs due to this configuration,
By referring to the address stored in the trace register 21, it is possible to specify which address the execution instruction read from was executed when the failure occurred.

In addition, it is possible to know from which address the currently executed execution instruction was jumped to the read address, and the cause of the failure can be found in a short time.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention, and FIG. 2 is a block diagram for explaining the conventional technology. 10: Control signal generator, 11: Sequencer, 12: Instruction memory, 13: Register, 14: Exception processing controller, 15: Micro control instruction, 16: Address signal, 17: Execution instruction, 18 Two control lot, 19: execution department,
21 Nidrace register, 22: Multiplexer.

Claims (1)

[Claims] (1) A: an instruction memory in which various execution instructions are written; a sequencer that stores addresses for reading out the execution instructions written in this instruction memory in a predetermined order; A control signal generator consisting of a register that temporarily stores execution instructions and outputs them to the execution unit, and an exception handling controller that rewrites the execution instructions written in the register to an exception handling instruction and performs exception handling when a failure occurs. In the vessel,
B. A trace register that stores a plurality of steps of addresses generated by the sequencer and stores a history of executed instructions; C. A multiplexer that selectively extracts the addresses stored in the trace register.