JP2000122882A - Multi-thread processor and debugging device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a multi-thread processor for performing multi-thread processing capable of easily performing debug and a debugging device capable of debugging the multi-thread processor. SOLUTION: This processor is provided with an operation processing means 101 which performs data operation processing in a thread unit, a register file 102 which consists of plural registers 20 and stores data obtained through the operation processing of the thread unit by the means 101 in any of the plural registers 20 in a thread unit, a thread information holding means 107 which holds thread information corresponding to data stored by each register 20 of the file 102 in accordance with each register 20 and a debug controlling means 108 which performs read control of the thread information stored by the means 107.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-thread processor for performing processing in units of a plurality of threads and a multi-thread processor debugging apparatus, and more particularly, to a multi-thread processor having a debugging support function and a multi-thread processor. Related to a debugging device.

[0002]

2. Description of the Related Art In recent years, the number of devices that require real-time processing for simultaneously processing a plurality of tasks in real time within a predetermined time has been increasing. As a technique for efficiently executing a plurality of task processes as described above, there is a multi-thread process in which a plurality of processes perform data processing in units called "threads" which are small-scale execution processing units. Regarding multi-thread processing in units of a plurality of threads, for example, there is a technique introduced in “Multi-thread Programming” by MIX Software, Inc., published by Brandeis Hall.

In the multi-thread processing, the processor that executes the processing uses the contents of the registers by switching them in units of a plurality of threads, or executes the processing by switching the resources of the arithmetic units in a time-division manner. This is called context switching. In a processor that performs multi-thread processing, in real-time processing in which context switching is efficiently performed and a plurality of threads are switched to advance execution of processing, processing including many exception processing such as occurrence of an exception thread due to an external interrupt or the like is performed. Must be advanced.

[0004]

However, in each of the thread control processes of the multi-thread as described above, the procedure for switching a plurality of processing units in a very short time is efficiently controlled, and the resources of the processor executing the process are efficiently used. It is very difficult to manage well. For example, in a processor that performs multi-thread processing, if the contents of a register file or a shared register that shares data between specific threads cannot be guaranteed at a specific time, subsequent processing can continue normally. Disappears.

[0005] As a means for protecting such data, there is a method of protecting data by protecting data in a thread. However, in many cases, it is necessary to protect the data at a program level, and furthermore, an interrupt is required. When a large number of asynchronous processes or the like are involved, unexpected data access and resource access occur, and the contents of a predetermined register cannot be protected, so that the predetermined process cannot be executed normally. Such problems occur especially when there is a strong correlation between the processes between threads, when data is shared between threads, and when data is communicated, or in the initial development stage of a multi-thread program that requires high real-time performance. Is more likely to do so.

[0006] Unlike ordinary single thread level processing, debugging for such an error involves a plurality of threads, making debugging more difficult. In particular, in recent years, in a multimedia system that executes a plurality of processes in real time, the number of threads related to a specific time tends to increase, and thus, the above-described program debugging is increasingly difficult. In particular,
In a multi-threaded program, because multiple threads share the registers and resources of the processor that executes the process, simply specify the problem by step execution using a normal debugging system such as ICE (In Circuit Emulator). Is very difficult. As described above, the conventional processor that performs multi-thread processing has a problem that it is very difficult to debug a program.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and a multi-thread processor for executing multi-thread processing capable of easily performing debugging. It is an object to provide a debugging device capable of debugging.

[0008]

A multi-thread processor according to the present invention comprises an arithmetic processing means for performing data arithmetic processing in units of threads, and a plurality of registers, and is obtained by the arithmetic processing in units of threads by the arithmetic processing means. A register file for holding the obtained data in one of the plurality of registers in a thread unit, and a thread for holding information of a thread corresponding to the data held in each register of the register file in correspondence with each register An information holding means and a debug control means for controlling reading of the thread information held in the thread information holding means are provided.

[0009] The program counter holding means for holding a program counter value corresponding to data held in each register of the register file corresponding to each register is provided, and the debug control means is provided in the program counter holding means. The reading control of the held program counter value is performed.

[0010] In addition, a plurality of registers of the register file are switched in units of threads to control writing of data obtained by processing in units of threads to the registers of the register file, and information of each thread is stored in the thread information. A thread control means for outputting to the holding means is provided.

The thread information holding means comprises a plurality of thread registers paired with the respective registers of the register file. The thread control means switches between the plurality of registers and simultaneously executes a thread register of the thread information holding means. And writes the data in a thread register of the thread information holding means that is paired with the register in which the data of the register file is written.

[0012] The present invention further comprises a data bus used for data transfer between the arithmetic processing means and the register file, and used for data transfer when reading data from the thread information holding means. is there.

[0013] Further, a debugging device according to the present invention includes:
An arithmetic processing means for performing data arithmetic processing in units of threads, and a plurality of registers, and holds data obtained by the arithmetic processing in units of threads by the arithmetic processing means in any of the plurality of files in units of threads. A register file, thread information holding means for holding thread information corresponding to the data held in each register of the register file, and thread information holding means for holding the thread information held in the thread information holding means; Debug control means for performing read control; and host control for controlling execution of arithmetic processing to the arithmetic processing means and controlling the debug control means to read data held in the register file and the thread information processing means. Means.

[0014] The program control apparatus further comprises program counter holding means for holding a program counter value corresponding to data held in each register of the register file in accordance with each register. The read control of the held program counter value is performed, and the host control means reads the program counter value of the program counter holding means when reading the data of the register file.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1 FIG. 1 is a block diagram showing a structure of a multi-thread processor according to the first embodiment of the present invention.
Numeral 0 denotes arithmetic processing means 101 for executing arithmetic processing, a register file 102 including a plurality of registers 20 for holding arithmetic data, and switching control of a thread connected to the arithmetic processing means 101 and the first control signal line 10. Control means for executing data input / output between the multi-thread processor 100 and the outside via the IO bus 105, and an IO control means 104
Control signal line 1 for connecting the
1 and the thread control means 1 via the thread signal line 14.
Thread information holding means 107 for holding thread information (thread ID), comprising a plurality of thread registers 30 paired with each register 20, connected to the register 06.
A debug control means 108 for executing debug control of the multi-thread processor 100 connected to the arithmetic control means 101 by a third control signal line 12; an arithmetic processing means 101; a register file 102;
04 and the data bus 103 inside the multi-thread processor 100 connected to the debug control means 108
, Register file 102 and thread information holding means 1
07 and the debug control means 108
And a selector 109 connected via the fourth control signal line 13 to select the data in the register file 102 and the thread information holding means 107 and output the selected data to the internal data bus 103.

In the multi-thread processor 100 configured as described above, the arithmetic processing means 101 includes a predetermined processing input from a control means such as a host computer connected to the outside of the multi-thread processor 100 via the IO bus 105. A predetermined arithmetic processing is executed in accordance with the instructions and data of the above or predetermined instructions and data held therein. Further, the arithmetic processing unit 101 transmits the first control signal using the first control signal line 10 and instructs the thread control unit 106 to execute a thread switching process and a context switching process of the register file 102.

The context switching is an operation for updating data in the register file 102 with data for each thread, and is prepared outside the multi-thread processor 100 through the IO bus 105 using the data bus 103 and the IO control means 104. This is executed by exchanging data with the data holding unit.

When the arithmetic processing means 101 writes and updates data in a specific register 20 of the register file 102 in a series of arithmetic processing, the thread control means 1
Reference numeral 06 denotes a thread register 3 of the thread information holding means 107 prepared to be paired with the register 20.
At 0, the information of the thread executing the data writing is written to the register 20. This thread information is information that can specify a thread indicating which thread has processed the data held in the register 20. For example, a thread number or the like is used, and this is held in the thread register 30. That is, the thread information held in the thread register 30 corresponds to a history of thread processing of data of the register 20 that is paired with the thread information. This processing is performed such that each time a data write access is performed to the register file 102 in a series of arithmetic processing of the multi-thread processor 100, the thread register 30 paired with the register 20 to which the data is to be written is written. Executed.

Next, for a series of arithmetic processing executed by the multi-thread processor 100, the register file 1
When the debug process, which is the process of reading the data written in the data 02 and the thread information on which the data was written, is executed, the multi-thread processor 10 is used.
For example, a host computer can transmit a debug instruction to the outside of the host computer and monitor the processing result.
(Not shown), instructs a predetermined debug instruction to the arithmetic processing means 101 via the IO bus 105, and upon receiving the instruction, the arithmetic processing means 101 sends the third control signal line 12
Register file 1 to debug control means 108 through
02 and the data of the thread information holding means 107 are
Output to the data bus 103 through the selector 109,
Further, the arithmetic processing means 101 outputs a second control signal to the IO control means 104 through the second control signal line 11,
In response to this, the IO control unit 104 outputs the data on the data bus 103 to the outside of the multi-thread processor 100 via the IO bus 105. This output is received by the above-described external monitoring means, and the multi-thread processor 1 uses the output data and thread information.
A series of processes is debugged by checking whether the process matches the predetermined process executed at 00.

FIG. 2 shows a multi-thread processor 100.
3 shows a flow of a process of writing data to a register file in a series of processes executed by the process shown in FIG. In addition,
In the following description, the process number of the thread is indicated by a number preceded by the symbol "#". In the figure, a first access time 201 of a time flow 200 showing a flow of processing time indicates a specific time when the thread # 1 has written data into a specific register 20, and a second access time 202. Indicates specific times at which the thread # 3 writes data to the same register 20 as the register 20 to which data was written during the first access time 201, respectively. The first data guarantee period 203 is a period in which data of the thread # 1 written in the first access time 201 and held in a specific register is guaranteed, and the second data guarantee period 204 is a second data guarantee period 204. Access time 20
This is a period in which the data of thread # 3, which has been written in 2 and held in a specific register, is guaranteed.

FIG. 3 is a diagram showing a flow of processing similar to the processing of FIG. 2. In the processing flow of FIG. 2, writing of data outside a predetermined range occurs in a predetermined register. This is an example of the case. In the figure, the same reference numerals as those in FIG. 2 indicate the same or corresponding parts, and the third access time 205 is a non-predetermined access time other than the first access time 201 and the second access time 202, The non-predetermined processing period 206 is a non-predetermined processing period generated by the occurrence of the third access time 205.

FIGS. 4 and 5 are diagrams showing how to access the register file and thread information holding means of the multi-thread processor 100. In the figures, the same reference numerals as those in FIG. 1 denote the same or corresponding parts. Is shown.

Hereinafter, the multi-thread processor 10
The process of writing data to the register file of 0 will be described. During a normal operation, as shown in FIG. 2, in the time stream 200, the thread # 1 writes predetermined data to the predetermined register 20 at the first access time 201. During the first data assurance period 203, the write data is guaranteed to be held by prohibiting the writing and updating of the data, and the held data is subjected to a data reading process and the data and other data. An arithmetic process using the data is performed. In the second access time 202, the thread # 3 writes and updates data in the same register 20 that has written data in the first access time 201.
Thereafter, a predetermined process is performed in the second data guarantee period 204.

In contrast to the case where the scheduled normal processing operation is executed as shown in FIG. 2, as shown in FIG. 3, unscheduled data writing by thread # 2 during the third access time 205 is performed as shown in FIG. When the operation is performed on the register that is the object of the guarantee period 203, the guarantee period of the first data guarantee period 203 shown in FIG. 2 is not guaranteed, and a non-scheduled processing period 206 occurs. Processing period 20
The processing after 6 is not guaranteed, and the execution of the processing stops or
This results in a processing result other than the predetermined one.

Here, in the first embodiment, as shown in FIG. 4, a thread # of the first access time 201 is assigned to a predetermined register 20 of the register file 102.
1 executes predetermined data writing, and at the same time, the thread information S1 indicating that the data writing has been executed is written to the thread register 30 of the thread information holding means 107 corresponding to this register.

Similarly, in the third access time 205,
Register file 10 written by thread # 1
At the same time as the thread # 2 of the first access time 201 executes the predetermined data writing to the predetermined register 20 of the second thread, the data writing to the thread register 30 of the thread information holding unit 107 corresponding to this register 20 is performed. Is written, indicating that thread information S2 has been executed. Thereafter, the same processing is performed.

In the debugging process, the multi-thread processor 100 receives an instruction of a predetermined debug command from the outside to the arithmetic processing means 101, and the arithmetic processing means 101 performs debugging through the third control signal line 12. The control unit 108 causes the data held in the register file 102 and the thread information holding unit 107 to be output to the data bus 103 through the selector 109, and the arithmetic processing unit 101 further outputs the second data through the second control signal line 11. It outputs a control signal and causes the IO control means 104 to output data on the data bus 103 to the outside of the multi-thread processor 100 via the IO bus 105. Here, since the thread information corresponding to the data of the register file 102 is held in the thread information holding unit 107,
By taking this out, it is possible to check the processing history such as which thread has processed the data in each register 30, and it is possible to identify the cause of the data in which an error has occurred. For example, by extracting the thread information S1, S2, and the like, an unexpected data write is performed by the thread # 2 at a specific time of the first data guarantee period 203 in response to the error as shown in FIG. That is, it is possible to specify that the data is updated by the thread # 2.

As described above, according to the multi-thread processor according to the first embodiment, the thread information holding unit 1
07 holds thread information corresponding to the data of the register file 102, and this thread information can be taken out at the time of debugging. Therefore, at the time of debugging, the flow of register data due to access from a plurality of threads by multi-threading is reduced. It can be easily monitored, and as a result, it is possible to easily find the cause of the runaway of the processing or the abnormality of the processing result caused by unexpected data access in a short time interval of the multi-thread processing. As a result, debugging can be performed early.

Embodiment 2 FIG. 6 is a block diagram showing the structure of the multi-thread processor according to the second embodiment of the present invention. In the figure, the same reference numerals as those in FIG. 1 indicate the same or corresponding parts. The multi-thread processor 300 makes a pair with each of the registers 20 of the register file 102 for the multi-thread processor 100 according to the first embodiment, and sets a program counter value at the time of issuing an instruction to write data to each register 20. PC holding means 301 comprising a plurality of program counter (hereinafter, referred to as PC) registers 40 for holding, and means for the arithmetic processing means 101 to output the program counter value as a data control signal through the data control signal line 15 And the arithmetic processing means 1
01 to the data control signal line 15
Is written into the PC register 40 of the PC holding means 301 through the PC. The output of the PC holding unit 301 is connected to the selector 109.

In the multi-thread processor 300 according to the second embodiment, similar to the first embodiment,
At the same time as writing the data to the predetermined register 20, the thread information for which the data has been written is written to the thread register 30 of the thread holding means 107. The program counter value of the instruction is input from the arithmetic processing means 101 through the data control signal line 15, and the program counter value is written to the PC register 40 corresponding to the predetermined register 20 of the PC holding means 301.

At the time of debugging, as in the first embodiment, a predetermined debug instruction is instructed to the arithmetic processing means 101, and the arithmetic processing means 101
And outputs a third control signal through the debug control unit 1
08 outputs the data of the register file 102, the thread information holding unit 107, and the PC holding unit 301 to the data bus 103 through the selector 109, and further, the arithmetic processing unit 101 controls the IO control unit 104 by the second control signal 11. Controlling the data on the data bus 103,
Multi-thread processor 100 through IO bus 105
Output to the outside of. This output register file 1
By using the data No. 02 and the thread information corresponding thereto, it is checked whether or not the processing matches the predetermined processing executed by the multi-thread processor 100, thereby debugging a series of processing similar to the first embodiment. .

Further, in the second embodiment, P
Since the C counter 301 holds the program counter value corresponding to the data in the register file 102, the program counter value is taken out at the time of debugging, and an error occurs using the program counter value in addition to the thread information. The cause can be specified.

As described above, according to the multi-thread processor of the present invention, the thread information holding means 107 holds the thread information corresponding to the data in the register file 102 so that the thread information can be taken out at the time of debugging. Since the PC counter 301 holds the program counter value corresponding to the data of the register file 102 and can retrieve the program counter value at the time of debugging, the same effect as in the first embodiment can be obtained. Improve the accuracy of debugging,
This has the effect of shortening the debugging process.

Embodiment 3 FIG. 7 is a block diagram showing a structure of a multi-thread processor according to Embodiment 3 of the present invention. In the figure, the same reference numerals as those in FIG. 1 indicate the same or corresponding parts. This multi-thread processor 400 is different from the multi-thread processor 300 according to the second embodiment in that a plurality of shared threads paired with the thread register 30 of the thread information holding means 107 connected to the selector 109 instead of the register file. A shared register file 401 comprising the registers 50;
A register file 102a and a register file 102b, each including a plurality of registers 20a and registers 20b connected to the data bus 103 and paired with the thread register 30 of the thread information holding means 107, are provided.

The operation of the multimedia processor 400 is almost the same as that of the second embodiment. Among the data processed by the threads, the data shared among the threads is stored in the register of the shared register file 401. 50, and those other than those shared are written to the register files 102a and 102b. When data is written to the register 50 of the shared register file 401, the thread information and the program counter value are written to the thread register 30 and the PC register 40 that are paired with the register 50, so that information necessary for debugging can be obtained. Hold. Then, at the time of debugging, similarly to the second embodiment, debug information is obtained by an external monitoring means, and debugging is performed.

According to the third embodiment, the same effects as those of the second embodiment can be obtained. In particular, even when a shared register accessed by a plurality of threads, which is difficult to debug, is provided, the data By retaining the update history, it is possible to easily find an abnormality in the result of the multi-thread processing, and to execute debugging earlier as a result.

In the third embodiment, two register files 102a and 102b are provided. However, in the present invention, the same number of register files may be provided as in the third embodiment. It works.

In the third embodiment, the shared register file 401 and the non-shared register file 1
02a and 102b are provided as independent register files. However, in the present invention, only some of the registers 50 of the shared register file 401 may be used as shared registers, and other registers may be used as non-shared registers. An effect similar to that of the third embodiment is obtained.

In the first to third embodiments, the thread control means is provided inside the multi-thread processor. However, in the present invention, the thread control means is provided outside the multi-thread processor, and the thread information is supplied from outside. May be taken. Further, in the first to third embodiments, the debug control means is controlled by using the IO control means and the arithmetic processing means.
The debug control means may be directly controlled from outside the multi-thread processor. In the first to third embodiments, instructions and data are supplied through the IO control means. However, in the present invention, processing is executed by using a multithread processor as a mode for holding instructions and data inside. Is also good. Further, in the first to third embodiments, the configuration is such that the data of the register file and the data of the thread information holding means are selectively output to the data bus through the selector. The configuration is not limited as long as it has a configuration for outputting means data.

Embodiment 4 FIG. FIG. 8 is a block diagram showing a structure of a debugging device according to the fourth embodiment of the present invention. In the drawing, a debugging device 505 is a register file similar to the multi-thread processor described in the first to third embodiments. A multi-thread processor 500 capable of holding thread information or a program counter value that has made data access to a specific register, or debug information including the thread information and the program counter value, and extracting the debug information; A host computer 501 connected to the IO bus 502 and capable of instructing the multi-thread processor 500 to perform a series of processes necessary for extracting debug information and displaying the extracted debug information is configured.

The debugging device 50 configured as described above
In 5, the multi-thread processor 500 supplies instructions and data through the IO bus 502 according to the instruction of the host computer 501, and executes a predetermined process according to the instruction and data in the designated processing unit.

When the multi-thread processor 500 completes the execution of the processing in the processing unit, the multi-thread processor 500 debugs the processing data held internally according to the instruction of the host computer 501, the thread information or the program counter value, or the thread information and the program counter value. The information is output to the host computer 501 via the IO bus 502. Then, the multi-thread processor 500 executes debugging by checking whether the debug information collected by the host computer 502 complies with a predetermined process.

As described above, according to the debugging device of the present embodiment, a multi-thread processor having thread information holding means for holding thread information, or a thread information holding means for holding thread information and a program counter value, respectively. Since the multi-thread processor having the PC holding means is provided, the cause of unscheduled register access caused by a program error or the like in the multi-thread processor executing the multi-thread can be easily specified.
Debugging efficiency can be improved.

[0044]

As described above, according to the present invention, the arithmetic processing means for performing data arithmetic processing in units of threads and a plurality of registers are provided, and the data obtained by the arithmetic processing in units of threads by the arithmetic processing means is provided. And a thread information holding means for holding thread information corresponding to data held in each register of the register file in correspondence with each register. And the debug control means for reading and controlling the information of the thread held in the thread information holding means, so that the debug control means is instructed at the time of debugging to be held in the thread information holding means. By reading the thread information, the written value of the data that caused the error and the Of it is possible to identify the thread that involved in writing, debugging capable performed easily, there is an effect capable of providing a multi-thread processor executing a multithreaded process.

Further, according to the present invention, there is provided a program counter holding means for holding a program counter value corresponding to data held in each register of the register file in correspondence with each register. Since the reading control of the program counter value held in the program counter holding means is performed,
By reading out the program counter value held in the program counter holding means at the time of debugging, there is an effect that a multi-thread processor that executes multi-thread processing that can easily perform debugging is provided.

According to the present invention, a plurality of registers of the register file are switched in units of threads, and writing of data obtained by processing in units of threads to the registers of the register file is controlled.
Since a thread control unit that outputs information of each thread to the thread information holding unit is provided, there is an effect that a multi-thread processor that executes a multi-thread process that can easily perform debugging is provided.

Further, according to the present invention, the thread information holding means comprises a plurality of thread registers paired with each register of the register file, and the thread control means switches the plurality of registers, Switch the thread register of the information holding means,
A multi-thread processor that executes multi-thread processing that can easily perform debugging because data is written to a thread register of the thread information holding unit that is paired with a register to which data of the register file is written. There is an effect that can be provided.

According to the present invention, a data bus used for data transfer between the arithmetic processing means and the register file and used for data transfer when reading data from the thread information holding means is provided. With this configuration, there is an effect that a multi-thread processor that executes multi-thread processing and that can easily perform debugging can be provided.

Further, according to the present invention, there are provided an arithmetic processing means for performing arithmetic processing of data in units of threads, and a plurality of registers. And a thread information holding means for holding thread information corresponding to data held in each register of the register file in correspondence with each register, A debug control means for controlling reading of thread information held in the information holding means; an execution control of arithmetic processing for the arithmetic processing means; and a control of the debug control means for controlling the register file and the thread information. Host control means for reading data held in the processing means. From the above, at the time of debugging, the host control means instructs the debug control means to read out the thread information held in the thread information holding means, thereby causing the write value of the data causing the error and the writing value of the data to be involved in the writing. This makes it possible to provide a debug device that can specify a thread that has been executed and can easily debug a multi-thread processor that executes multi-thread processing.

Further, according to the present invention, there is provided a program counter holding means for holding a program counter value corresponding to data held in each register of the register file in correspondence with each register. The host control means reads the program counter value of the program counter holding means at the time of reading the data of the register file. In addition, it is possible to specify a cause of an error based on a program counter value at the time of debugging, and to provide a debugging device capable of easily debugging a multi-thread processor that executes multi-thread processing.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a structure of a multi-thread processor according to a first embodiment of the present invention.

FIG. 2 is a diagram for explaining an operation of the multi-thread processor according to the first embodiment of the present invention, showing a state in which a register file is normally accessed in a multi-thread operation.

FIG. 3 is a diagram for explaining an operation of the multi-thread processor according to the first embodiment of the present invention, showing a state where a non-predetermined access to a register file is performed in the multi-thread operation.

FIG. 4 is a schematic diagram showing a state in which data is held by a thread in a register file and thread information holding means of the multithread processor according to the first embodiment of the present invention;

FIG. 5 is a schematic diagram showing a state in which data is held by another thread in a register file and thread information holding means of the multithread processor according to the first embodiment of the present invention;

FIG. 6 is a block diagram showing a structure of a multi-thread processor according to a second embodiment of the present invention.

FIG. 7 is a block diagram illustrating a structure of a multithread processor according to Embodiment 3 of the present invention.

FIG. 8 is a diagram showing a structure of a debugging device according to a fourth embodiment of the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 10 1st control signal line 11 2nd control signal line 12 3rd control signal line 13 4th control signal line 14 thread signal line 15 data control signal line 20, 20a, 20b register 30 thread register 40 PC register 50 Shared register 100, 300, 400, 500 Multithread processor 101 Arithmetic processing means 102, 102a, 102b Register file 103 Data bus 104 IO control means 105 IO bus 106 Thread control means 107 Thread information holding means 108 Debug control means 109 Selector 200 hours Flow 201 First access time 202 Second access time 203 First data guarantee period 204 Second data guarantee period 205 Third access time 206 Non-scheduled processing period 301 PC holding means 401 Sharing Register file 501 the host computer 502 IO bus 505 debugging device.

Claims (7)

[Claims] An arithmetic processing means for performing data arithmetic processing in a thread unit, and a plurality of registers, wherein data obtained by the arithmetic processing means in a thread unit by the arithmetic processing means is stored in one of the plurality of registers. A register file that is held in units of threads, thread information holding means that holds thread information corresponding to data held in each register of the register file corresponding to each register, and a thread information holding means that holds the thread information. And a debug control means for controlling reading of information of the thread. 2. The multi-thread processor according to claim 1, further comprising program counter holding means for holding a program counter value corresponding to data held in each register of the register file in correspondence with each register. The multi-thread processor according to claim 1, wherein the debug control means controls reading of a program counter value held in the program counter holding means. 3. The multi-thread processor according to claim 1, wherein a plurality of registers of the register file are switched in units of threads, and writing of data obtained by processing in units of threads to the registers of the register file is controlled. And a thread control means for outputting information of each thread to the thread information holding means. 4. The multi-thread processor according to claim 3, wherein said thread information holding means comprises a plurality of thread registers paired with each register of said register file, and said thread control means stores said plurality of registers. A multi-thread processor that switches the thread register of the thread information holding means at the same time as the switching, and writes data in a thread register of the thread information holding means which is paired with a register in which the data of the register file is written. . 5. The multi-thread processor according to claim 1, wherein said multi-thread processor is used for data transfer between said arithmetic processing means and a register file, and is used for data transfer when reading data from said thread information holding means. A multi-thread processor comprising a data bus to be used. 6. An arithmetic processing means for performing data arithmetic processing in a thread unit, and a plurality of registers, wherein data obtained by the thread-by-thread arithmetic processing by the arithmetic processing means is stored in one of the plurality of files. A register file that is held in units of threads, thread information holding means that holds thread information corresponding to data held in each register of the register file corresponding to each register, and a thread information holding means that holds the thread information. Debug control means for controlling reading of thread information, and execution control of arithmetic processing for the arithmetic processing means, and controlling the debug control means to be held in the register file and the thread information processing means. A debugging device comprising a host control means for reading data. 7. The debugging device according to claim 6, further comprising: program counter holding means for holding a program counter value corresponding to data held in each register of the register file in correspondence with each register. The debug control means controls the reading of the program counter value held in the program counter holding means. The host control means reads the program counter value of the program counter holding means when reading the data of the register file. A debugging device, characterized in that: