JPH0535392B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a pattern generation method and apparatus for generating a test data pattern given to a semiconductor memory with a high degree of freedom when testing the memory.

[Background of the invention]

Generally, a test data pattern for a semiconductor memory is generated as shown in FIG. 1, but in the past, the test data pattern could not be easily changed and generated.

That is, FIG. 1 shows a general configuration of a general data pattern generator together with a memory under test. According to this, X address 5 and Y address 6 are updated to a predetermined value in address generator 3 by control signal 2 from controller 1, and X address 5
The Y address 6 is input to the memory under test 8 as an address signal. On the other hand, test data pattern 7, which is write data corresponding to It is starting to occur based on this.

Usually, the test data pattern used when testing semiconductor memory is a regular pattern corresponding to the position of the memory cell, but FIGS.
An example of a typical test data pattern is shown in the case of a semiconductor memory consisting of x4 memory cells. The items shown in Figure 2 a to d are called the CHECKER BOAD, ROW BAR, COLUMN BAR, and DIAGONAL, respectively. It can be generated by logically or arithmetically processing the X address and Y address given to the memory under test. For example, Figure 2 d
The test data pattern shown in is "1" if the value obtained by subtracting the Y address from the X address is "0";
Any value other than "0" can be generated as "0".

However, with the increasing complexity of memory structures and demands for improved test accuracy, the current situation is that even more complex test data patterns are required. FIG. 3 shows a method for dealing with this. Memory under test 8
A desired test data pattern is stored in advance in a pattern memory 9 serving as a data generator having a capacity equal to or greater than that of The test data pattern is read out.

However, if a test data pattern is to be generated in this way, it would be necessary to generate a test data pattern with at least the same capacity as the memory under test in order to generate a test data pattern with simple rules as shown in FIG. It is necessary to store the pattern in memory in advance. In other words, a pattern memory with at least the same capacity as the memory under test is required, and each time the pattern is changed, a new test data pattern related to the change must be stored in the pattern memory. There is a problem in that it takes a lot of time to change the test data pattern, and therefore, a test data pattern related to the change cannot be generated quickly and easily.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a pattern generation method and apparatus that can quickly and easily generate various test data patterns with a high degree of freedom while suppressing the capacity of a pattern memory.

[Summary of the invention]

For this purpose, the present invention focuses on how complex the test data pattern is and that it consists of repetitions of basic small patterns that are not random but relatively complex, and the address given to the memory under test. A part of the signal is given as an address signal to one or more pattern memories whose total capacity is smaller than the capacity of the memory under test and whose pattern can be changed, and is given to the memory under test based on the data read from the pattern memory. A test data pattern corresponding to an address signal is generated.

Also, a pattern generating device that generates a pattern of write data given to a memory under test based on an address signal given to the memory, the pattern generation device including one or more pattern memories whose patterns can be changed, and a pattern of write data given to the memory under test. and a bit extraction circuit for extracting the number of bits necessary for the address of the pattern memory from the address signal, the information extracted by the bit extraction circuit is given to the pattern memory as an address signal, and the information is read out from the pattern memory. The device is configured to generate write data corresponding to an address signal to be applied to the memory under test based on the data.

[Embodiments of the invention]

The present invention will be explained below with reference to FIGS. 4 to 6.

First, FIG. 4a shows the main parts of the pattern generator according to the present invention, which is based on the pattern shown in FIG. 2a, together with the memory under test. In this case, the memory under test 8 consists of 4×4 memory cells, but since the entire test data pattern is formed as a repetition of four identical data patterns as shown in the figure, the X address 5, which consists of 2 bits, Y
If the lower bits of each address 6 are given as an A desired test data pattern 7 can be obtained. It goes without saying that the pattern memory 9 stores basic small patterns, but it is clear that the patterns shown in FIGS. 2b and 2c can be generated in a similar manner. Furthermore, the pattern shown in FIG. 2d can be easily obtained by gate-controlling the data read out from the pattern memory in the same way using the result of exclusive ORing of the upper bits of X address 5 and Y address 6. I understand.

FIG. 4b shows the pattern memory and its peripheral control circuit shown in FIG. 4a. In the example shown in FIG. 4A, it is sufficient to extract only the lower bits from each of the 2-bit X address 5 and Y address 6 and provide them as the X address 14 and Y address 15 to the pattern memory 9. Registers 10 and 11 are for selecting address bits, and if X address 5 and Y address 6 are gate-controlled by gate circuits 12 and 13 in order to make use of only the lower bits by their respective 2-bit parallel outputs, Address 14 and Y address 15 are obtained. If the test data pattern written to the memory under test consists of repetitions of basic small patterns, no matter how large the capacity of the memory under test is, the capacity of the pattern memory that generates the test data pattern is small. In other words, it only needs to generate a pattern. In the above example, the capacity of the pattern memory is 4 bits, and the lower 1 bit is required to specify the address. For example, if 4k bits are required as a minimum, the It is sufficient to extract only the lower 6 bits and use it as an address signal for the pattern memory.

Next, the case where test data patterns are generated with a large degree of freedom will be explained with reference to FIGS. 5a and 5b. In FIG. 5a, the pattern memory 9 is composed of pattern memories 9a and 9b with a capacity of 4 bits.
The upper and lower bits of X address 5 and Y address 6 are respectively applied to addresses a and 9b as address signals. For example, the same pattern is stored in the pattern memories 9a and 9b as shown in the figure, and the pattern memories 9a and 9
If the read data from b is ANDed by the AND gate 16, the second test data pattern 7 is obtained.
What is obtained is shown in Figure d. The patterns stored in the pattern memories 9a and 9b can be made different, and the read data from the pattern memories 9a and 9b can be controlled by OR gates, NAND gates, NOR gates, etc.
By processing with an exclusive OR gate, various test data patterns can be easily generated with a small memory capacity.

FIG. 5b generally shows the pattern memory and its peripheral control circuit shown in FIG. 5a. As shown in the figure, the upper bits of X address 5 and Y address 6, which consist of multiple bits, are stored in registers 17 and 1.
8 and the gate circuits 19 and 20, and the X address 2 is extracted to the pattern memory 9a.
1, Y address 22. Similarly, the lower bits are set to register 1.
0, 11 and the gate circuits 12, 13, and the X address 1 is extracted to the pattern memory 9b.
4, Y address is given as 15. If the data read from the pattern memories 9a and 9b is subjected to appropriate logical processing in the logic processing circuit 23, the test data pattern 7 is obtained. In this case, X address 21, Y address 22
It is also possible to use multiple bits of data read out instead of one bit, and to select the processing function in the logic processing circuit 23 using these multiple bits. In this case, the test data pattern 7 can be generated with a greater degree of freedom.

FIG. 6a shows a case where test data patterns are generated with a greater degree of freedom through pattern selection. In this case, pattern memories 9a, 9b
Input the X address and Y address in the same way as in Figure 5a.
Although an address is given, the pattern memory 9b is made up of two types of pattern memories. Thus, one of the two types of pattern memories in the pattern memory 9b is selected according to the data read out from the pattern memory 9a, and the X address 5 according to the selected pattern memory is selected.
A test data pattern is obtained by reading data using the lower bits of Y address 6.

FIG. 6b shows its general configuration. registers 17, 18 and gate circuit 19,
20, the X address 21 and Y address 22 for the pattern memory 9a are extracted from the X address 5 and Y address 6, while the registers 10 and 1
1 and gate circuits 12 and 13, X address 14 and Y address 15 for pattern memory 9b are extracted from X address 5 and Y address 6. The degree of freedom is increased by selecting any of the pattern memories in the pattern memory 9b using data read from the pattern memory 9a, and then reading data from the selected pattern memory using the X address 14 and the Y address 15. Test data pattern 7 is obtained.

Although the present invention is as described above, it goes without saying that it is not limited to the above examples and can be implemented in various ways. When storing different patterns in two or more pattern memories, the same address may be given, and data read from one pattern memory may be used to invert or select data read from another pattern memory. It is clear that the various logical operations of Note that in the above example, the address to the pattern memory is a register,
Although it can be made variable by a gate circuit, it is not necessary if it is fixed, and even if it is made variable, it can be replaced by other means.

〔Effect of the invention〕

As explained above, according to the present invention, it is possible to obtain the effect that various test data patterns can be generated quickly and easily with a high degree of freedom while suppressing the capacity of the pattern memory.

[Brief explanation of the drawing]

Figure 1 shows the general configuration of a general data pattern generator together with the memory under test, Figure 2a
- d are diagrams showing examples of typical test data patterns, respectively, FIG. 3 is a diagram for explaining a method of generating test data patterns according to the prior art, and FIG. 4 a
4 is a diagram showing essential parts of an example of a pattern generation device according to the present invention together with a memory under test, FIG. 4b is a diagram showing a pattern memory and its peripheral control circuit in the configuration, and FIG. FIG. 5b is a diagram generally showing the pattern memory and its peripheral control circuit in the configuration;
FIG. 6a is a diagram showing the main parts of still another example of the pattern generator according to the present invention together with the memory under test, and FIG. 6b is a diagram showing the pattern memory and its peripheral control circuit in the configuration. be. 3...Address generator, 8...Memory under test,
9 (9a, 9b)...Pattern memory, 10,1
1, 17, 18...Register, 12, 13, 1
9,20...gate circuit.

Claims (1)

[Scope of Claims] 1. A pattern generation method in which the pattern of write data given to the memory under test is generated based on an address signal given to the memory, and a part of the address signal given to the memory under test is generated based on the total capacity. is given as an address signal to one or more pattern memories whose patterns are changeable and whose capacity is smaller than the capacity of the memory under test, and an address signal corresponding to the address signal given to the memory under test is given based on data read from the pattern memory. A pattern generation method characterized by generating write data. 2. A pattern generator that generates a pattern of write data given to the memory under test based on an address signal given to the memory, one or more pattern memories whose patterns can be changed, and an address signal given to the memory under test. and a bit extraction circuit for extracting the necessary number of bits from the address of the pattern memory, the information extracted by the bit extraction circuit is given to the pattern memory as an address signal, and the information read from the pattern memory is A pattern generating device characterized in that it is configured to generate write data corresponding to an address signal to be applied to the memory under test.