JP6461831B2 - Memory inspection device - Google Patents

Description

  Embodiments described herein relate generally to a memory inspection apparatus.

  The memory inspection device creates a physical fail bitmap in order to analyze the position of a defective bit of a device under test (DUT (Device Under Tester)). In order to create a physical fail bitmap, a logical-physical conversion process for converting a logical address into a physical address is required.

  In recent years, logical-physical conversion processing has become complicated, and it has become difficult to perform processing with a simple logical expression (so-called scramble). For this reason, an analysis server is used separately from the memory inspection device for logical-physical conversion processing.

  However, when the logical-physical conversion process is performed in the analysis server, the CPU needs to access the HDD and the memory many times in the analytical server, and there is a problem that the logical-physical conversion process and the failure analysis process take a long time. .

JP 2001-324546 A JP-A-10-222998

  Provided is a memory inspection device capable of reducing the time required for logical-physical conversion processing and failure analysis processing.

  The memory test apparatus according to the present embodiment includes first and second conversion units. The first conversion unit stores a conversion table indicating a correspondence relationship between a logical address of data output from the device under test and a physical address of the device under test, and converts the logical address to a physical address based on the conversion table. . The second conversion unit converts the data output from the device under test and having the same physical address into the physical storage arrangement order within the device under test and outputs the data. The first memory stores the data from the second conversion unit at the position according to the physical address in the order of output from the second conversion unit. The first memory outputs the stored data in the physical storage arrangement order in the first memory. The second memory stores the data stored in the first memory in the physical storage arrangement order in the first memory.

FIG. 3 is a block diagram showing an example of the configuration of the memory test apparatus 1 according to the present embodiment. 1 is a conceptual diagram showing an example of a physical storage array inside a memory under test 2 in the present embodiment. The block diagram which shows an example of a structure of the logical-physical conversion part 10 and the data mapping part 15. FIG. The conceptual diagram which shows either the logical-physical conversion table Tc, Ts, and Tl. FIG. 3 is a block diagram illustrating an example of an internal configuration of a mapping circuit 16; FIG. 3 is a block diagram illustrating an example of the configuration of a sort memory 20, a burst address generation unit 30, a row fail bit counter 50, and a column fail bit counter 60. FIG. 4 is a timing chart showing an example of the operation of the memory test apparatus 1 according to the present embodiment. The figure which shows the physical string address and physical column address of the column data output from the sort memory 20A or 20B. The figure which shows the mode of the burst access to the fail bit memory 40 by this embodiment. The flowchart which shows an example of operation | movement of a memory test apparatus. The block diagram which shows an example of a structure of the logical-physical conversion part 10 and the data mapping part 15 by the modification of this embodiment. The block diagram which shows an example of the internal structure of the mapping circuit 16 by the modification of this embodiment.

  Embodiments according to the present invention will be described below with reference to the drawings. This embodiment does not limit the present invention.

  FIG. 1 is a block diagram showing an example of the configuration of the memory test apparatus 1 according to the present embodiment. The memory test apparatus 1 receives a logical fail bit map (theoretical address (X, Y, Z) and data) output from the memory under test 2 (DUT (Device Under Tester)) and based on the logical fail bit map. This is a device for acquiring and storing a physical fail bit map and the number of fail bits in the test memory 2.

  The memory under test 2 is a semiconductor memory such as a NAND type EEPROM (Electrically Erasable Programmable Read-Only Memory). In the NAND type EEPROM, the logical address of the memory cell may not match the physical arrangement (physical address). In such a NAND type EEPROM, in order to improve the yield, the physical position of the internal fail bit and the number of fail bits may be specified and analyzed for failure.

  When testing a fail / pass of a memory cell, data of the same logic (for example, “0”) is once written in the memory under test 2. Next, data is read from the memory under test 2. When the data read from the memory under test 2 is changed to data of opposite logic (for example, “1”), the memory test apparatus 1 determines the memory cell as a fail bit. The fail bit is a memory cell handled as a defective memory cell in the memory under test 2. The memory test apparatus 1 first obtains a logical fail bitmap in the memory under test 2. A logical fail bitmap is data associated with a logical address. Therefore, the memory test apparatus 1 has the following configuration in order to convert a logical fail bitmap into a physical fail bitmap.

  Hereinafter, the memory test apparatus 1 will be described in more detail.

  The memory test apparatus 1 according to the present embodiment includes a logical-physical conversion unit 10, a data mapping unit 15, a sort memory 20, a burst address generation unit 30, a fail bit memory 40, a row fail bit counter 50, a column fail. And a bit counter 60.

  The logical / physical conversion unit 10 as the first conversion unit stores a conversion table indicating the correspondence between the logical address (X, Y, Z) given to the memory under test 2 and the physical address of the memory under test 2. Yes. The logical / physical conversion unit 10 converts a logical address into a physical address based on the conversion table. As described above, the logical-physical conversion process is becoming more and more complex year by year, and it is impossible to perform conversion (scramble) with a simple logical expression. Therefore, in this embodiment, the logical / physical conversion unit 10 stores a logical / physical conversion table, and sequentially converts logical addresses into physical addresses according to the logical / physical conversion table (arbitrary conversion).

  For example, the logical-physical conversion table includes theoretical addresses (X, Y, Z) and physical addresses (for example, column addresses C0 to Cn (n is an integer) shown in FIG. 2), row addresses (or string addresses) R0 to Rm (m Is an integer), layer addresses L0 to Lp (p is an integer), and block addresses B0 to Bq (q is an integer)). The logical address (X, Y, Z) is an address given from the memory inspection device 1 to the memory under test 2, and the memory under test 2 returns the data read according to the logical address to the memory inspection device 1. X is, for example, a column address, Y is, for example, a row address (string address and layer address), and Z is, for example, a block address. The addresses of X, Y, and Z are not limited to this, and can be arbitrarily set. The physical address is an address indicating a physical position in the memory under test 2. Therefore, the physical location in the memory under test 2 where the data is stored is determined by the physical address. The logical / physical conversion table may differ depending on the product of the memory under test 2. In this case, a logical-physical conversion table may be set in advance according to the product of the memory under test 2 before the test of the memory under test 2. A configuration example of the physical addresses (column addresses C0 to Cn, row addresses (or string addresses) R0 to Rm, layer addresses L0 to Lp, block addresses B0 to Bq) of the NAND type EEPROM will be described later with reference to FIG. explain.

  The data mapping unit 15 as the second conversion unit outputs a group of data (hereinafter also referred to as column data) output from the memory under test 2 and having the same physical address in the order of the physical storage arrangement in the memory under test 2. Rearrange to output. The column data is data composed of a plurality of bits (for example, 8 bits) belonging to the same physical address (same block, same row (string, layer), same column) shown in FIG. The column data may include a plurality of bits, and the memory under test 2 outputs the data of the plurality of bits in the column data in an arbitrarily set order different from the storage array order in the memory under test 2. There is a case. In such a case, since the bit arrangement in the column data cannot be specified by the physical address, the data mapping unit 15 stores the output order information set arbitrarily and based on the output order information. The bit array of the column data is rearranged (mapped) in the order of the physical storage array in the memory under test 2 and output. A configuration example of the data mapping unit 15 will be described later with reference to FIG.

  The sort memory 20 as the first memory stores the column data from the data mapping unit 15 at a position according to the physical address. Thereby, the sort memory 20 can store each column data at a position corresponding to a physical storage position in the memory under test 2. The sort memory 20 stores data in the order of output from the data mapping unit 15. The bit arrangement in each column data output from the data mapping unit 15 is in the order of the physical storage arrangement in the memory under test 2. Therefore, the sort memory 20 can store the bit arrangement in the column data in a physical storage arrangement in the memory under test 2. Thereby, the sort memory 20 can store, for example, the entire page including a plurality of column data in a physical storage array in the memory under test 2.

  The NAND-type EEPROM can be read or written in page units. Therefore, when the memory under test 2 is a NAND type EEPROM, the sort memory 20 can store data in units of pages. For example, the sort memory 20 uses an SRAM (Static Random Access Memory) that can be accessed at high speed, and can store data in write units or read units (hereinafter also referred to as pages or page units). The sort memory 20 stores the column data rearranged by the data mapping unit 15 according to a physical address (column address). Accordingly, each column data is stored in the sort memory 20 in the physical storage order in the memory under test 2. When the data capacity is in page units, the sort memory 20 can transfer data to the fail bit memory 40. That is, the sort memory 20 reproduces the physical storage arrangement in the memory under test 2 for each page and transfers the data to the fail bit memory 40.

  The burst address generation unit 30 generates a burst address composed of continuous numerical values. The burst address is, for example, an address (0, 1, 2, 3,...) Incremented from zero in ascending order. The burst address is used when column data is read from the sort memory 20. The sort memory 20 stores data for one page in the physical storage array order in the memory under test 2. Therefore, if the sort memory 20 outputs the column data in the physical storage arrangement order in the sort memory 20 in accordance with the burst address, the fail bit memory 40 stores the column data in the physical storage arrangement in the memory under test 2. Can be stored in order. The burst address may be, for example, an address (... 3, 2, 1, 0) that is deincremented in descending order.

  The burst address generation unit 30 generates continuous burst addresses during the period when the logical-physical conversion unit 10 outputs the address of the same page. On the other hand, the burst address generation unit 30 resets the burst address when the logical-physical conversion unit 10 outputs an address of another page (when the page changes). For example, when the page address (row address) is changed, the burst address generation unit 30 again outputs while incrementing from zero. In this case, the row address is a page address and includes both a string address and a layer address.

  The fail bit memory 40 stores the data in page units stored in the sort memory 20 in the position according to the physical address (block address, row address) in the physical storage arrangement order in the sort memory 20. To do. As described above, the sort memory 20 stores data in the physical storage array order in the memory under test 2 and continuously outputs the data according to the burst address. Therefore, the fail bit memory 40 can store the data of the page in the physical storage arrangement order in the memory under test 2 at the position specified by the physical address (block address, row address). If the data of all the pages in the memory under test 2 are stored in the fail bit memory 40 in this way, the fail bit memory 40 can reproduce the physical data storage array in the memory under test 2. . As the fail bit memory 40, for example, a large capacity and high speed accessible SDRAM (Synchronous Dynamic RAM) is used.

  The row fail bit counter 50 counts the fail bits of the data from the data mapping unit 15 for each page (that is, for each row address R0 to Rm in FIG. 2). For example, the row fail bit counter 50 adds fail bit data (for example, data “1”) transmitted from the data mapping unit 15 to the sort memory 20, and calculates the number of fail bits for each page. The number of fail bits for each page is stored in the row fail bit counter 50.

  The column fail bit counter 60 stores the accumulated value of the number of fail bits at each data storage position of the sort memory 20 (for example, the number of fail bits of each bit in the same column over a plurality of pages). For example, the sort memory 20 stores the data in the physical storage arrangement order in the memory under test 2 for each page. Therefore, when the sort memory 20 sequentially stores a plurality of pages, the same data storage position is stored. The number of bit data stored in is the number of fail bits of each bit data in the same column across a plurality of pages in the memory under test 2 (the number of fail bits of memory cells connected to the same bit line). . Therefore, when the sort memory 20 sequentially stores a plurality of pages, if the number of fail bits at each data storage position of the sort memory 20 is accumulated over a plurality of pages, the column direction over the plurality of pages (Rc in FIG. 2). The number of fail bits of the memory cells arranged in (1) is obtained. The number of fail bits for each column is stored in the column fail bit counter 60.

  FIG. 2 is a conceptual diagram showing an example of a physical storage array inside the memory under test 2 in the present embodiment. The memory under test 2 is a semiconductor memory such as a NAND type EEPROM, for example. The memory under test 2 may be, for example, a memory having a two-dimensional memory cell array structure or a stacked memory having a three-dimensional memory cell array structure. In the present embodiment, description will be made assuming that the memory under test 2 is, for example, a stacked memory.

  The memory cell array MCA of the memory under test 2 is composed of a plurality of blocks B0 to Bq (q is an integer). Each block B0 to Bq is composed of a plurality of layers L0 to Lp (p is an integer). Each layer L0 to Lp includes a plurality of memory cells arranged two-dimensionally. Rows (strings in each layer) R0 to Rm (m is an integer) indicate a plurality of memory cells sharing a word line (not shown). Columns C0 to Cn (n is an integer) indicate a plurality of memory cells connected to one or a plurality of bit lines (not shown). The word line and the bit line intersect each other, and the memory cell is provided so as to correspond to the intersection. The extending direction of the word line is the row direction Rr, and the extending direction of the bit line is the column direction Rc. In FIG. 2, the data of each memory cell or each bit is indicated by squares.

  The memory under test 2 sets data stored in memory cells in the same row (connected to the same word line) as “page”, and writes or reads data in units of pages. For example, data stored in memory cells corresponding to one row R0 and all columns C0 to Cn is one page. In FIG. 2, one page corresponds to one row of data arranged in the row direction Rr.

  On the other hand, data of a plurality of memory cells arranged in the column direction Rc and connected to the same bit line are output from the same input / output port IO (Input / Output) of the memory under test 2. Accordingly, data output from a plurality of memory cells connected to the same bit line via the same input / output port IO is also referred to as “IO data” hereinafter. In FIG. 2, IO data corresponds to one column of data arranged in the column direction Rc.

  When the memory under test 2 has, for example, eight input / output ports IO, the memory under test 2 simultaneously reads eight memory cells corresponding to a certain row and column (eight bit lines) at the time of reading. Output bit data. This 8-bit data is data (one column data) output from the memory under test 2 at a time. Since the memory under test 2 executes reading for each page, reading of all column data in a certain page (row) is completed and the reading operation is finished. Therefore, the page as the read unit is the same row data, and the memory under test 2 outputs the read target page by 8 bit data (one column data). On the contrary, at the time of writing, the memory under test 2 fetches the page to be written one column at a time. A page to be read or written is specified by a physical block address, a physical layer address, and a physical row address (string address). Further, column data (8-bit data) is specified by a physical column address.

  On the other hand, logical addresses (X, Y, Z) output from the memory under test 2 are different from physical addresses within the memory under test 2. Furthermore, as described above, data in the same column may be output in an arbitrarily set order, unlike the physical order stored in the memory under test 2. Accordingly, the memory test apparatus 1 converts the logical address (X, Y, Z) into a physical address (for example, a block address, a layer address, a string address, a column address), and also data in the same column (for example, 8 bit data) must be converted into a physical order in the memory under test 2. Therefore, in this embodiment, the logical / physical conversion unit 10 shown in FIG. 1 executes logical / physical conversion processing for converting logical addresses into physical addresses, and the data mapping unit 15 receives bit data in the same column data. The data is converted into a physical order in the test memory 2.

  FIG. 3 is a block diagram illustrating an example of the configuration of the logical-physical conversion unit 10 and the data mapping unit 15. The logical-physical conversion unit 10 includes an address selector 11, a valid signal generation unit 12, a select setting unit 13, logical-physical conversion processing units 17 to 19, and table selectors 87 to 89.

  The address selector 11 selects the logical address (LAc, LAs, LAl) of the memory test apparatus 1 corresponding to the logical address (X, Y, Z) given to the memory under test 2, and the logical address (LAc, LAs, LAl) is output. The logical addresses (LAc, LAs, LAl) are logical addresses in the memory test apparatus 1 selected corresponding to the logical addresses (X, Y, Z), and correspond to the logical addresses (X, Y, Z). Any address may be used. The logical address (LAc, LAs, LAl) may be the same address as the logical address (X, Y, Z). Accordingly, the logical address (X, Y, Z) and the logical address (LAc, LAs, LAl) may be collectively referred to as a logical address hereinafter without being particularly distinguished.

  The Valid signal generation unit 12 detects a change in the logical address (LAc, LAs, LAl) and activates the permission signals Rvalid_c, Rvalid_s, and Rvalid_l, respectively. As a result, logical addresses (LAc, LAs, LAl) are logically / physically converted as effective logical addresses in the logical / physical conversion processing units 17 to 19.

  The logical / physical conversion processing unit 17 stores a logical / physical conversion table Tc for column addresses, and converts the logical column address LAc to the corresponding physical column address PAc when the permission signal Rvalid_c is activated. . The logical column address LAc is an address indicating physical columns C0 to Cn in the memory under test 2. The logical / physical conversion table Tc is a table indicating the physical column address PAc corresponding to the logical column address LAc. The logical-physical conversion processing unit 17 converts the logical column address LAc to the physical column address PAc, and outputs the physical column address PAc.

  The logical-physical conversion processing unit 17 may store a plurality of logical-physical conversion tables Tc. In this case, the table selector 87 may select one of the plurality of logical-physical conversion tables Tc using a part of the logical address. For example, when the logical-physical conversion processing unit 17 has a plurality of logical-physical conversion tables Tc corresponding to the blocks B0 to Bq, the table selector 87 selects one of the physical columns of the plurality of logical-physical conversion tables Tc according to the block address. The address PAc is selectively output. Thereby, the table selector 87 can selectively output the physical column address PAc corresponding to the specific block.

  The logical / physical conversion processing unit 18 stores a logical / physical conversion table Ts for string addresses (row addresses), and when the permission signal Rvalid_s is activated, the logical string address LAs is converted to the corresponding physical string address PAs. Convert to The logical string address LAs is an address indicating a physical string (rows R0 to Rm) in the memory under test 2. The logical-physical conversion table Ts is a table indicating the physical string address PAs corresponding to the logical string address LAs. The logical-physical conversion processing unit 18 converts the logical string address LAs into the physical string address PAs, and outputs the physical string address PAs.

  The logical-physical conversion processing unit 18 may store a plurality of logical-physical conversion tables Ts. In this case, the table selector 88 may select one of the plurality of logical-physical conversion tables Ts using a part of the logical address. For example, when the logical-physical conversion processing unit 18 has a plurality of logical-physical conversion tables Ts corresponding to the blocks B0 to Bq, the table selector 88 selects one of the physical strings of the plurality of logical-physical conversion tables Ts according to the block address. The address PAs is selectively output. Thereby, the table selector 88 can selectively output the physical string address PAs corresponding to a specific block.

  The logical-physical conversion processing unit 19 stores a logical-physical conversion table Tl for layer addresses, and converts the logical layer address LAl into a corresponding physical layer address PAl when the permission signal Rvalid_l is activated. The logical layer address LAl is an address indicating a physical layer (L0 to Lp) in the memory under test 2. The logical-physical conversion table Tl is a table indicating the physical layer address PAl corresponding to the logical layer address LAl. The logical-physical conversion processing unit 19 converts the logical layer address LAl into the physical layer address PAl, and outputs the physical layer address PAl.

  The logical-physical conversion processing unit 19 may store a plurality of logical-physical conversion tables Tl. In this case, the table selector 89 may select one of the plurality of logical-physical conversion tables Tl using a part of the logical address. For example, when the logical-physical conversion processing unit 19 has a plurality of logical-physical conversion tables Tl corresponding to the blocks B0 to Bq, the table selector 89 selects one of the physical layers of the plurality of logical-physical conversion tables Tl according to the block address. The address PAl is selectively output. Thereby, the table selector 89 can selectively output the physical layer address PAl corresponding to a specific block.

  The address for selecting a specific logical / physical conversion table from a plurality of logical / physical conversion tables (Tc, Ts, or Tl) may be an address other than the block address. In this embodiment, logical-physical conversion processing units are provided corresponding to three addresses (column address, string address, layer address), but the number of logical-physical conversion processing units depends on the type of address. Correspondingly, it may be less than three or more than three.

  FIG. 4 is a conceptual diagram showing one of the logical-physical conversion tables Tc, Ts, and Tl. The logical-physical conversion table is a table showing physical addresses (PAc, PAs, or PAl) corresponding to logical addresses (LAc, LAs, or LAl). For example, if the physical address corresponding to the logical address Add0 is Add8, the logical-physical conversion processing unit outputs the physical address Add8 when the logical address Add0 is input. Assuming that the physical address corresponding to the logical address Add1 is Add1, the logical-physical conversion processing unit outputs the physical address Add1 when the logical address Add1 is input. If the physical address corresponding to the logical address Add2 is Add5, the logical-physical conversion processing unit outputs the physical address Add5 when the logical address Add2 is input.

  As shown in FIG. 4, the logical-physical conversion process may include conversion with no regularity between a logical address and a physical address. Therefore, in this embodiment, arbitrary conversion using the logical-physical conversion table is performed as described above without using scrambling by a logical expression.

  Please refer to FIG. 3 again. The data mapping unit 15 includes a mapping setting unit 14 and a mapping circuit 16. The mapping setting unit 14 stores the relationship between the bit arrangement in the column data output from the memory under test 2 and the bit arrangement of the physical column data in the memory under test 2. Based on the relationship between these bit arrangements, the mapping circuit 16 rearranges the bit arrangement of the column data output from the memory under test 2 into the bit arrangement of the physical column data in the memory under test 2 ( Output after mapping).

  FIG. 5 is a block diagram illustrating an example of the internal configuration of the mapping circuit 16. The mapping circuit 16 includes a plurality of selectors 90 to 97. The plurality of selectors 90 to 97 are provided in a number corresponding to the number of bits included in one column data, and are connected in parallel between the input and the output. For example, when the column data is 8-bit data, the mapping circuit 16 includes at least eight selectors 90 to 97. Each of the selectors 90 to 97 receives column data, and selectively outputs any bit data of the column data based on the bit arrangement relationship in the mapping setting unit 14. For example, it is assumed that the bit arrangement of the column data output from the memory under test 2 is (0461357) and the bit arrangement of the physical column data in the memory under test 2 is (01234567). In this case, each of the selectors 90 to 97 receives column data (0461357) and outputs bit data 0, 1, 2, 3, 4, 5, 6, and 7, respectively. As a result, the data mapping unit 15 rearranges the bit array (0461357) of the column data output from the memory under test 2 into the bit array (01234567) of the physical column data within the memory under test 2 and outputs the data. can do.

  FIG. 6 is a block diagram showing an example of the configuration of the sort memory 20, the burst address generation unit 30, the row fail bit counter 50, and the column fail bit counter 60.

  The sort memory 20 includes a column address sort memory 20A (hereinafter also referred to as sort memory 20A) as a first sort memory and a column address sort memory 20B (hereinafter also referred to as sort memory 20B) as a second sort memory. . For example, SRAMs that can execute both random access and burst access at high speed are used for the sort memories 20A and 20B, respectively. The sort memories 20A and 20B are, for example, SRAMs each capable of storing one page of data.

  The sort memories 20A and 20B execute the data write operation and the data read operation exclusively alternately. When the sort memory 20A is executing the data write operation, the sort memory 20B executes the data read operation. When the sort memory 20B is executing a data write operation, the sort memory 20A executes a data read operation. That is, the sort memories 20A and 20B execute a so-called interleave operation. Since the sort memories 20A and 20B perform an interleave operation, the sort memories 20A and 20B can almost seamlessly capture the column data mapped by the data mapping unit 15 in FIG. It can be delivered to the memory 40. Thereby, the memory inspection device 1 can fetch data into the sort memory 20 in real time without delay with respect to the data reading speed from the memory under test 2.

  For example, when the write enable signal WEN_A is activated, the sort memory 20A receives the mapped column data from the data mapping unit 15 and writes the column data therein. When the write enable signal WEN_B is activated, the sort memory 20B receives the post-mapping column data from the data mapping unit 15 and writes the column data therein. The write enable signals WEN_A and WEN_B are complementary signals. When one is active, the other is inactive, and conversely, when the other is active, one is inactive. Both write enable signals WEN_A and WEN_B are not activated simultaneously.

  The sort memory 20A reads the data stored therein when the read enable signal REN_A is activated. The sort memory 20B reads data stored therein when the read enable signal REN_B is activated. The read enable signals REN_A and REN_B are complementary signals. When one is active, the other is inactive, and conversely, when the other is active, one is inactive. Both of the read enable signals REN_A and REN_B are not activated at the same time.

  The WEN generator 70 is a circuit that generates the write enable signals WEN_A and WEN_B. The WEN generation unit 70 receives the column permission signal Rvalid_c generated by the Valid signal generation unit 12 and the output signal from the Y address detection unit 80, and receives the permission signal Rvalid_c and the output signal from the Y address detection unit 80. And the logical product (AND) of the two as a write enable signal WEN_A or WEN_B. Here, the Y address detector 80 detects that the logical address Y has changed. The logical address Y is a logical address corresponding to the physical layer address and the physical string address. Therefore, when the logical Y address changes, the physical layer address and / or the physical string address (page, row) change. The Y address detector 80 detects a page change and outputs the result. For example, when a certain page is selected, the Y address detection unit 80 raises an output signal. Thereby, the WEN generation unit 70 enables the write enable signal WEN_A. At this time, the write enable signal WEN_B is not activated. On the other hand, when another page is selected, the Y address detection unit 80 causes the output signal to fall. Thereby, the WEN generation unit 70 enables the write enable signal WEN_B. At this time, the write enable signal WEN_A is not activated.

  The WEN generating unit 70 activates one of the write enable signals WEN_A and WEN_B when the permission signal Rvalid_c is activated (when the column address is changed). Thereby, the sort memory 20A or 20B can store the data from the data mapping unit 15 for each column address. At this time, the sort memories 20A and 20B store data at a predetermined position according to the physical column address. When the sort memories 20A and 20B store one page of data, the data in the sort memories 20A and 20B are stored in the physical storage array order of the page in the memory under test 2. That is, the data in the sort memories 20A and 20B are sorted according to the physical column address.

  The REN generator 72 is a circuit that generates read enable signals REN_A and REN_B. The REN generation unit 72 receives the operation signal of the burst address generation unit 30 and the output signal from the Y address detection unit 80, and outputs the operation signal of the burst address generation unit 30 and the output signal from the Y address detection unit 80. A logical product (AND) is output as the read enable signal REN_A or REN_B. As described above, since the Y address detection unit 80 detects page switching, the REN generation unit 72 switches the read enable signals REN_A and REN_B to be activated according to the output signal of the Y address detection unit 80. For example, when a certain page is selected, the Y address detection unit 80 raises an output signal. Thereby, the REN generator 72 enables the read enable signal REN_A. At this time, the read enable signal REN_B is not activated. On the contrary, when the next page is selected, the Y address detector 80 causes the output signal to fall. Thereby, the REN generator 72 enables the read enable signal REN_B to be activated. At this time, the read enable signal REN_A is not activated.

  When the operation signal of the burst address generation unit 30 is activated (when the burst address generation unit 30 outputs a burst address), the REN generation unit 72 activates one of the read enable signals REN_A and REN_B. Let As a result, the sort memory 20A or 20B can continuously read the data stored therein according to the burst address (burst read). Since the data in the sort memories 20A and 20B are sorted according to the physical column address, the data arrangement order is physically stored in the memory under test 2 even if burst read is performed using the burst address as the column address. Output according to the sequence.

  The selectors 72 and 74 selectively output a physical column address and a burst address based on the write enable signal WEN_A or WEN_B. For example, when the write enable signal WEN_A is activated and the sort memory 20A is in the write state, the selector 72 outputs the physical column address from the logical / physical conversion unit 10 to the sort memory 20A. Thereby, the sort memory 20A can store data according to the physical column address. On the other hand, when the write enable signal WEN_A is inactivated and the sort memory 20A is not writable, the selector 72 outputs the burst address from the burst address generation unit 30 to the sort memory 20A. As a result, the sort memory 20A can read data according to the burst address. For example, when the write enable signal WEN_B is activated and the sort memory 20B is in a write state, the selector 74 outputs the physical column address from the logical / physical conversion unit 10 to the sort memory 20B. Thereby, the sort memory 20B can store data according to the physical column address. On the other hand, when the write enable signal WEN_B is inactivated and the sort memory 20B cannot be written, the selector 74 outputs the burst address from the burst address generation unit 30 to the sort memory 20B. Thereby, the sort memory 20B can read data according to the burst address.

  The selector 65 can output the data from either the sort memory 20A or 20B to the fail bit memory 40 based on the output signal of the Y address detector 80. For example, when a certain page is selected, the Y address detection unit 80 raises an output signal. Accordingly, the read enable signal REN_A can be activated, and the selector 65 can selectively output the data in the sort memory 20A to the fail bit memory 40. On the other hand, when another page is selected, the Y address detection unit 80 causes the output signal to fall. As a result, the read enable signal REN_B can be activated, and the selector 65 can selectively output the data in the sort memory 20B to the fail bit memory 40. As a result, the selector 65 can transfer the burst read data to the fail bit memory 40.

  As described above, the sort memories 20A and 20B can store the data for each page in the order of the physical column addresses, and can burst-read the data of the pages. Furthermore, since the sort memories 20A and 20B perform an interleave operation, the sort memories 20A and 20B can alternately deliver data to the fail bit memory 40 in a short time.

  The row fail bit counter 50 includes a row counter 51 and a row fail bit count memory 52. The row counter 51 as the first counter receives the permission signal Rvalid_c and the column data, and counts the fail bits of the column data for each page. For example, if the bit changed to data “1” is a fail bit, the row counter 51 may count (integrate) “1” of each column data. The row counter 51 may be, for example, a register that accumulates data “1”.

  The row fail bit count memory 52 (hereinafter referred to as count memory 52) as the first count memory receives the change (page switching) of the output signal of the Y address detection unit 80, and the number of fail bits counted by the row counter 51. Hold. The count memory 52 may be any memory that can hold the number of fail bits. As a result, the number of fail bits for each page (that is, for each row or each string) is stored in the count memory 52. The count memory 52 can store the number of fail bits of each page (that is, each row R0 to Rm or each string). The number of fail bits in each page can be used when analyzing a failure.

  In the memory under test 2, reading is performed after reading the data of the same page (all columns C0 to Cn in the same row Rk (0 ≦ k ≦ m)). Therefore, the row fail bit counter 50 can obtain the number of fail bits of the page by simply adding the fail bits until the physical row address changes. Therefore, the configuration of the row fail bit counter 50 is simpler than that of the column fail bit counter 60 described later.

  The column fail bit counter 60 includes column fail bit count memories 60A and 60B (hereinafter also referred to as count memories 60A and 60B) and adders 61A and 61B. The column fail bit counter 60 counts the number of fail bits of each IO data (IOa, IOb, IOc... In FIG. 2) over a plurality of pages (that is, a plurality of rows R0 to Rm). That is, the column fail bit counter 60 counts the number of fail bits of data (IO data) of a plurality of memory cells connected to the same bit line.

  Here, since a bit line in a certain column (for example, C0) extends over a plurality of pages (that is, a plurality of rows R0 to Rm), the number of fail bits of IO data in each column is: It is necessary to add IO data over a plurality of pages (that is, a plurality of rows R0 to Rm). For example, the number of fail bits of the IO data IOa in the column C0 in FIG. 2 needs to add (accumulate) the IO data IOa in each of the rows R0 to Rm. The number of fail bits of the IO data IOb needs to be added (integrated) with the IO data IOb in each of the rows R0 to Rm. The number of fail bits of the IO data IOc needs to be added (integrated) with the IO data IOc in each of the rows R0 to Rm. In order to determine the number of fail bits of IO data (IOa, IOb, IOc...) In each column (C0 to Cn) over a plurality of pages, as shown in FIG. , 60B and adders 61A, 61B.

  Count memories 60A and 60B as second count memories are provided corresponding to the sort memories 20A and 20B, respectively. The count memories 60A and 60B may be registers corresponding to IO data for one page. Thereby, the count memories 60A and 60B can count the number of fail bits of each IO data.

  The count memory 60A receives a read enable signal REN_A and a read enable signal REN_B. The count memory 60A uses the read enable signal REN_B as a write enable signal. Accordingly, in FIG. 6, the read enable signal REN_B input to the count memory 60 </ b> A is represented as “REN_B (WEN)”.

  The reason why the read enable signal REN_B (WEN) is used as the write enable signal is as follows. The count memory 60A needs to store the addition result in the adder 61B, and the adder 61B executes addition processing when the sort memory 20B and the count memory 60B are executing a read operation, and the addition result is displayed. Output. Therefore, the count memory 60A needs to execute a write operation in synchronization with a period during which the sort memory 20B and the count memory 60B are executing a read operation (a period during which the read enable signal REN_B is activated). Therefore, the count memory 60A uses the read enable signal REN_B (WEN) as the write enable signal.

  The count memory 60B receives the read enable signal REN_A and the read enable signal REN_B. The count memory 60B uses the read enable signal REN_A as a write enable signal. Therefore, in FIG. 6, the read enable signal REN_A input to the count memory 60B is represented as “REN_A (WEN)”.

  The reason why the read enable signal REN_A (WEN) is used as the write enable signal is as follows. The count memory 60B needs to store the addition result in the adder 61A. The adder 61A executes addition processing when the sort memory 20A and the count memory 60A are executing a read operation, and the addition result is displayed. Output. Therefore, the count memory 60B needs to execute a write operation in synchronization with a period during which the sort memory 20A and the count memory 60A are executing a read operation (a period during which the read enable signal REN_A is activated). Therefore, the count memory 60B uses the read enable signal REN_A (WEN) as the write enable signal.

  The count memories 60A and 60B need to output data in synchronization with the sort memories 20A and 20B. For this reason, the count memories 60A and 60B use burst addresses in read and write operations.

  An adder 61A as an adder is provided corresponding to the sort memory 20A and the count memory 60A. The adder 61A adds the corresponding bit data in the sort memory 20A to the number of fail bits of each IO data stored in the count memory 60A. Here, the sort memory 20 </ b> A stores one page of data in the physical storage array in the memory under test 2. The count memory 60A is a physical storage array in the memory under test 2 and stores the number of fail bits of each bit of the pages stored so far in the sort memories 20A and 20B. Therefore, the adder 61A simply adds the data at each data storage position of the sort memory 20A to the data (the number of fail bits) at each data storage position of the count memory 60A. Since the fail bit is data “1”, the adder 61A can simply add the corresponding data in the sort memory 20A to the number of fail bits stored in the count memory 60A to obtain the integrated value of the number of fail bits. Can be obtained. In this way, the adder 61A adds the corresponding data stored in the sort memory 20A to the number of fail bits of each IO data stored in the count memory 60A. The adder 61A outputs the number of fail bits after the addition to the count memory 60B, and the count memory 60B stores the number of fail bits in a physical storage array in the memory under test 2.

  An adder 61B as an adding unit is provided corresponding to the sort memory 20B and the count memory 60B. The adder 61B adds the corresponding bit data in the sort memory 20B to the number of fail bits of each IO data stored in the count memory 60B. Here, the sort memory 20B stores one page of data in the physical storage array in the memory under test 2. The count memory 60B is a physical storage array in the memory under test 2 and stores the number of fail bits of each bit of the pages stored so far in the sort memories 20A and 20B. Therefore, the adder 61B simply adds the data at each data storage position of the sort memory 20B to the data (fail bit number) at each data storage position of the count memory 60B. Thereby, the adder 61B adds each corresponding data stored in the sort memory 20B to the number of fail bits of each IO data stored in the count memory 60B. The adder 61B outputs the number of fail bits after the addition to the count memory 60A, and the count memory 60A stores the number of fail bits in a physical storage array in the memory under test 2.

  Each time the sort memories 20A and 20B read data, the adders 61A and 61B alternately repeat the above addition operation and store the addition results in the count memories 60B and 60A, thereby reading the data from the sort memories 20A and 20B. The number of fail bits (integrated value) of IO data in each column over all pages is finally stored in the count memory 60A or 60B. The number of fail bits of the IO data in each column can be used for failure analysis.

  The adders 61A and 61B may be shared by one adder. In this case, a selector (not shown) that receives the read enable signal REN_A has only to select the fetch destination of the data to be added in the adder and the output destination of the addition result. For example, when the read enable signal REN_A is in the active state, the selector may add the data from the sort memory 20A and the count memory 60A and output the addition result to the count memory 60B. When the read enable signal REN_B is in the active state, the selector may add the data from the sort memory 20B and the count memory 60B and output the addition result to the count memory 60A.

  7A to 7D are timing charts showing an example of the operation of the memory test apparatus 1 according to the present embodiment. FIG. 7A shows an operation example of the logical-physical conversion process by the logical-physical conversion unit 10. FIG. 7B shows an operation example of logical-physical conversion processing by the sort memory 20. FIG. 7C shows an operation example of row fail bit count processing by the row fail bit counter 50. FIG. 7D shows an operation example of column fail bit count processing by the column fail bit counter 60. Note that the count memories 52, 60A, and 60B store zero as an initial state.

  As shown in FIG. 7A, logical addresses X and Y are input from the memory test apparatus 1 to the memory under test 2. The logical address LAs corresponding to the logical address Y is logically and logically converted to generate a physical string address PAs that identifies the page. The logical address LAc corresponding to the logical address X is logically and logically converted to generate a physical column address PAc. Here, the read operation from the same block and the same layer is shown, and the description of the logical address Z and the physical layer address is omitted.

(Write page P0 to sort memory 20A, read from sort memory 20B)
At t0, the physical string address PAs indicates the page P0. When the physical string address PAs indicates the page P0, the Y address detector 80 in FIG. 6 raises the output signal. As a result, the WEN generator 70 activates the write enable signal WEN_A, and the REN generator 72 activates the read enable signal REN_B. 7B to 7D, “W” indicates activation of the write enable signal, and “R” indicates activation of the read enable signal. Accordingly, as shown in FIGS. 7B and 7D, the sort memory 20A and the count memory 60A can be written, and the sort memory 20B and the count memory 60B can be read. The numerical value of the burst address indicates the column address in ascending order generated by the burst address generation unit 30 in FIG.

  As shown in FIG. 7B, since the sort memory 20A becomes writable at t0, the sort memory 20A stores the column data according to the physical column address C0. On the other hand, since the sort memory 20B can be read, the sort memory 20B continuously outputs column data according to the burst address. The column data from the sort memory 20B is output to the fail bit memory 40 via the selector 65 of FIG. 6, and is also output to the adder 61B. At this time, since the count memory 60B can also be read, the adder 61B sets the number of fail bits of each IO data of the column address C0 in the count memory 60B in the sort memory 20B as shown in FIG. The respective IO data of the column address C0 are added (+) and output to the count memory 60A. Note that “+” shown in FIGS. 7C and 7D indicates addition processing. Since the count memory 60A receives the read enable signal REN_B (WEN) as a write enable signal, the count memory 60A can be written at almost the same time as the sort memory 20B and the count memory 60B can be read. Therefore, the count memory 60A can store the addition result from the adder 61B at a position corresponding to the column address C0. That is, the count memory 60A can store the result of adding the data at each bit position of the column address C0 in the sort memory 20B to the number of fail bits at each bit position of the column address C0 in the count memory 60B.

  Here, since the unfailed bit is data “0” and the fail bit is data “1”, the adder 61B fails each IO data of the column address C0 in the count memory 60B. Each IO data of the column address C0 in the sort memory 20B is added to the number of bits as it is. As a result, the number of fail bits of the data “0” is not counted (not incremented), and the number of fail bits of the data “1” is counted (incremented). Thus, the column fail bit counter 60 can accumulate the number of fail bits of each bit. Since the sort memory 20B and the count memory 60B are all initially in the initial state (zero), the count memory 60A stores zero at t0 to t1. In addition, since the data output from the sort memory 20B at this time is in an initial state (zero), it is not necessary to store it in the fail bit memory 40.

  As shown in FIG. 7C, the row counter 51 adds (+) each bit of the column data at the column address C 0 and stores the addition result in the count memory 52. As described above, since the unfailed bit is data “0” and the fail bit is data “1”, the row counter 51 uses the data “0” of the column address C0 transferred to the sort memory 20A. The number of 1 ″ may be counted. Thereby, the row counter 51 can obtain the number of fail bits in the column address C0.

  As shown in FIG. 7B, at t1, the sort memory 20A stores the column data according to the physical column address C1. On the other hand, the sort memory 20B continuously outputs the column data according to the burst address. As described above, the column data from the sort memory 20B is output to the fail bit memory 40 and also to the adder 61B. At this time, as shown in FIG. 7D, the adder 61B adds each IO data of the column address C1 in the sort memory 20B to the number of fail bits of each IO data of the column address C1 in the count memory 60B. (+) And output to the count memory 60A. The count memory 60A stores the addition result from the adder 61B at a position corresponding to the column address C1. That is, the count memory 60A stores the result of adding the data at each bit position of the column address C1 in the sort memory 20B to the number of fail bits at each bit position of the column address C1 in the count memory 60B.

  As shown in FIG. 7C, the row counter 51 adds (+) each bit of the column data at the column address C 1 and stores the addition result in the count memory 52. As described above, since the unfailed bit is data “0” and the fail bit is data “1”, the row counter 51 reads the data “1” of the column address C1 transferred to the sort memory 20A. The number of 1 ″ may be counted. Thereby, the row counter 51 can obtain the number of fail bits in the column address C1.

  The memory test apparatus 1 operates in the same manner for the column addresses C2, C3. Therefore, the sort memory 20A stores the column data of the physical column addresses C2, C3,. Thereby, the sort memory 20A can store the data of all the columns C0 to Cn of the page P0. On the other hand, the sort memory 20B continuously outputs the column data according to the burst address. The sort memory 20B may be in a standby state when all column data is read.

  As shown in FIG. 7D, the adder 61B adds the number of fail bits of each IO data of the column addresses C2, C3,... In the count memory 60B to the column addresses C2, C3,. The respective IO data are added and output to the count memory 60A. The count memory 60A stores the addition result from the adder 61B at a position corresponding to each of the column addresses C2, C3,. That is, the count memory 60A adds the data at the bit positions of the column addresses C2, C3,... In the sort memory 20B to the number of fail bits at the bit positions of the column addresses C2, C3,. Stores the result of addition.

  As shown in FIG. 7C, the row counter 51 adds the respective bits of the column data of the column addresses C2, C3... And stores the addition result in the count memory 52. By adding the data of all the column addresses C0 to Cn, the count memory 52 stores the number of fail bits of the page P0.

(Write page P1 into sort memory 20B, read page P0 from sort memory 20A)
When the data of all the columns C0 to Cn in the page P0 are stored in the sort memory 20A, the logical address Y and the physical string address PAs change. That is, the page is switched. For example, as shown in FIG. 7A, the logical address Y is switched from Y0 to Y1, and the physical string address PAs is switched from page P0 to page P1. The output signal of the Y address detection unit 80 changes depending on the page switching. As a result, the data of page P1 is written to the sort memory 20B, and the data of page P0 stored in the sort memory 20A is read from the sort memory 20A to the fail bit memory 40.

  For example, at t10, the physical string address PAs designates the page P1. When the physical string address PAs designates the page P1, the Y address detection unit 80 in FIG. 6 causes the output signal to fall. As a result, the WEN generation unit 70 activates the write enable signal WEN_B, and the REN generation unit 72 activates the read enable signal REN_A. Accordingly, as shown in FIGS. 7B and 7D, the sort memory 20B and the count memory 60B can be written, and the sort memory 20A and the count memory 60A can be read.

  As shown in FIG. 7B, since the sort memory 20B becomes writable at t10, the sort memory 20B stores the column data according to the physical column address C0. On the other hand, since the sort memory 20A can be read, the sort memory 20A continuously outputs column data according to the burst address. The column data from the sort memory 20A is output to the fail bit memory 40 via the selector 65 of FIG. 6, and is also output to the adder 61A. At this time, since the count memory 60A can also be read, the adder 61A sets the number of fail bits of each IO data of the column address C0 in the count memory 60A in the sort memory 20A as shown in FIG. Are added to each column address C0 and output to the count memory 60B. Since the count memory 60B receives the read enable signal REN_A (WEN) as a write enable signal, the count memory 60B can be written at almost the same time as the sort memory 20A and the count memory 60A can be read. Therefore, the count memory 60B can store the addition result from the adder 61A at a position corresponding to the column address C0. That is, the count memory 60B can store the result of adding the data at each bit position of the column address C0 in the sort memory 20A to the number of fail bits at each bit position of the column address C0 in the count memory 60A.

  Here, as described above, the unfailed bit is data “0”, and the fail bit is data “1”. Therefore, the adder 61A uses each column address C0 in the count memory 60A. What is necessary is just to add each IO data of column address C0 in the sort memory 20A as it is to the number of fail bits of IO data. As a result, the number of fail bits of the data “0” is not counted (not incremented), and the number of fail bits of the data “1” is counted (incremented). The count memory 60A is in an initial state, and the sort memory 20A stores the data of the page P0. Therefore, the count memory 60B has the number of fail bits of each bit of the column C0 in the page P0 from t10 to t11. (Data “1”) is stored.

  As shown in FIG. 7C, the row counter 51 adds the respective bits of the column data at the column address C 0 and stores the addition result in the count memory 52.

  As shown in FIG. 7B, at t11, the sort memory 20B stores the column data according to the physical column address C1. On the other hand, the sort memory 20A continuously outputs the column data according to the burst address. As described above, the column data from the sort memory 20A is output to the fail bit memory 40 and also to the adder 61A. At this time, as shown in FIG. 7D, the adder 61A adds each IO data of the column address C1 in the sort memory 20A to the number of fail bits of each IO data of the column address C1 in the count memory 60A. And output to the count memory 60B. The count memory 60B stores the addition result from the adder 61A at a position corresponding to the column address C1. That is, the count memory 60B stores the result of adding the data at each bit position of the column address C1 in the sort memory 20A to the number of fail bits at each bit position of the column address C1 in the count memory 60A.

  As shown in FIG. 7C, the row counter 51 adds each bit of the column data of the column address C 1 and stores the addition result in the count memory 52. Thereby, the row counter 51 can obtain the number of fail bits in the column address C1.

  The memory test apparatus 1 operates in the same manner for the column addresses C2, C3. Therefore, the sort memory 20B stores the column data of the physical column addresses C2, C3,. Thereby, the sort memory 20B can store data of all columns C0 to Cn of the page P1. On the other hand, the sort memory 20A continuously outputs the column data according to the burst address. The sort memory 20A may be in a standby state when all the column data is read out.

  As shown in FIG. 7D, the adder 61A adds the column addresses C2, C3,... In the sort memory 20A to the number of fail bits of each IO data of the column addresses C2, C3,. The respective IO data are added and output to the count memory 60B. The count memory 60B stores the addition result from the adder 61A at a position corresponding to each of the column addresses C2, C3,. That is, the count memory 60B adds the data at the bit positions of the column addresses C2, C3,... In the sort memory 20A to the number of fail bits at the bit positions of the column addresses C2, C3,. Stores the result of addition.

  As shown in FIG. 7C, the row counter 51 adds the respective bits of the column data of the column addresses C2, C3... And stores the addition result in the count memory 52. By adding the data of all the column addresses C0 to Cn, the count memory 52 can store the number of fail bits of the page P1.

(Write page P2 into sort memory 20A, read page P1 from sort memory 20B)
Furthermore, when the data of all the columns C0 to Cn in the page P1 are stored in the sort memory 20B, the logical address Y and the physical string address PAs change. For example, the physical string address PAs is switched from the page P1 to the page P2. The output signal of the Y address detection unit 80 changes depending on the page switching. Thereby, the data of page P2 is written to the sort memory 20A, and the data of page P1 stored in the sort memory 20B is read from the sort memory 20B to the fail bit memory 40. The write operation to the sort memory 20A and the read operation from the sort memory 20B are the same as the above-described operations. The operations of the adder 61B and the row counter 51 are the same as those in the processing of the page P0.

  Subsequent page writing and reading are similarly performed. Thereby, the fail bit memory 40 can store the data of each page (each row R0 to Rm) in the order of the physical storage arrangement in the memory under test 2. The fail bit memory 40 stores the data of each page according to the physical address (physical layer address, physical string address, physical block address) after logical-physical conversion. In each bit of data in the fail bit memory 40, data “1” is a fail bit. The count memory 52 stores the number of fail bits of each page (each row R0 to Rm). The count memory 60A or 60B stores the number of fail bits of each IO data over a plurality of pages (a plurality of rows).

  As described above, according to the present embodiment, the data mapping unit 15 converts the bit array of the column data output from the memory under test 2 into a physical storage array within the memory under test 2 and outputs it. The sort memories 20A and 20B each store column data from the data mapping unit 15 according to the physical address until reaching one page. Thereby, the sort memories 20A and 20B can store data for each page in the physical storage array order in the memory under test 2. The data in the sort memories 20A and 20B is output to the fail bit memory 40 by burst read. Since the data is stored in the physical storage array order in the memory under test 2, the fail bit memory 40 is physically stored in the memory under test 2 even when the data in the sort memories 20 </ b> A and 20 </ b> B is burst read. Data can be imported in the order of arrangement. That is, the fail bit memory 40 stores the data in page units stored in the sort memory 20A or 20B at a position according to the physical address (that is, in the physical storage arrangement order in the memory under test 2).

  For example, FIG. 8 is a diagram illustrating physical string addresses and physical column addresses of column data output from the sort memory 20A or 20B. The sort memory 20A or 20B outputs data of the same physical string address (same page) 5 in the order of physical column addresses (0, 1, 2, 3,...). That is, the data in the sort memory 20A or 20B is burst read. At this time, when accessing the fail bit memory 40, burst access is possible.

  For example, if the sort memories 20A and 20B are not provided, the fail bit memory 40 needs to be randomly accessed. In random access, in order to make it possible to access memory cells having different string addresses, it is necessary to precharge the word line and the like, which increases the data write time.

  On the other hand, in this embodiment, when data is written to the fail bit memory 40, the sort memories 20A and 20B output data of the same page (same layer and same string) in the order of physical column addresses. For example, FIG. 9 is a diagram showing a state of burst access to the fail bit memory 40 according to the present embodiment. In the sort memories 20A and 20B, as shown in FIG. 8, the physical string address (page) is not changed until the data of all the columns of the page are burst read. Therefore, as shown in FIG. 9, the fail bit memory 40 activates the word line corresponding to the selected physical string address, and then continuously accesses and writes the data in the sort memory 20A or 20B. Can do. Thereby, the fail bit memory 40 can store the data stored in the memory under test 2 in a short time. That is, when the sort memory (for example, SRAM) 20 is interleaved and the sort memory 20 writes the data into the fail bit memory 40 in a burst form, the memory inspection device 1 reads the data from the memory under test 2. The data can be written to the sort memory 20 in real time without delaying the speed.

  In the present embodiment, the logical / physical conversion process is not executed by scrambling, but is arbitrarily converted using a logical / physical conversion table. When the logical-physical conversion process becomes complicated and the logical expression representing the logical-physical conversion becomes complicated, the arbitrary conversion using the logical-physical conversion table can be processed faster than the scramble. Therefore, the memory test apparatus 1 according to the present embodiment can shorten the logical-physical conversion processing time.

  Further, according to the present embodiment, when a page is stored in the fail bit memory 40, the row fail bit counter 50 stores the number of fail bits of the page, and the column fail bit counter 60 stores each fail bit of the page. An integrated value of the number of fail bits of IO data is stored. Therefore, it is not necessary to count the number of fail bits using an analysis server other than the memory test apparatus 1, and the failure analysis time is shortened.

  Furthermore, according to the present embodiment, the logical-physical conversion unit 10, the data mapping unit 15, the burst address generation unit 30, the row fail bit counter 50, and the column fail bit counter 60 are logic such as an FPGA (Field-Programmable Gate Array). It can be configured with a circuit.

  If a fail bit map is generated using a CPU and a program (software), the memory test apparatus and the analysis server operate as shown in FIG. That is, data (logical fail bit map) is fetched from the memory under test 2 (S1), and the CPU stores the logical fail bit map in an HDD (Hard Disk Drive) (S2). Next, the CPU reads the logical fail bitmap from the HDD, temporarily stores the logical fail bitmap in the memory, and expands it (S4). Next, the CPU converts the logical fail bitmap in the memory into a physical fail bitmap according to the logical-physical conversion table (S5). At this time, the CPU executes a logical-physical conversion process. Further, the CPU temporarily expands the converted physical fail bitmap in the memory (S6). The CPU counts the number of fail bits in each page, the fail bits in each column, and the like by scanning the physical fail bitmap in the memory. As described above, the CPU needs to execute the logical-physical conversion process and the fail bit count process while accessing the HDD and the memory many times, and takes a long time for the logical-physical conversion process and the failure analysis process. Note that the summation of fail bits without masking (S7) is a process of counting including fail bits that have already been analyzed. The totaling of fail bits with a mask (S8) is a process of counting excluding fail bits that have already been analyzed.

  In contrast, the memory test apparatus 1 according to the present embodiment, as described above, includes the logical-physical conversion unit 10 and the like as a logic circuit, and performs a fail bit count process in parallel (simultaneously) with the logical-physical conversion process. Is also executed. For example, the data output from the data mapping unit 15 shown in FIG. 1 is converted into a physical storage array in the memory under test 2 by the sort memory 20 and then stored in the fail bit memory 40. In parallel with this period, the row fail bit counter 50 and the column fail bit counter 60 count the number of fail bits.

  FIG. 10B is a flowchart showing an example of the operation of the memory test apparatus 1 according to the present embodiment. When data (logical fail bit map) is fetched from the memory under test 2 (S10), the memory testing device 1 performs logical-physical conversion processing on the logical address (S20). At this time, the data is temporarily stored in the sort memory 20 (S30) and then written to the fail bit memory 40. That is, the physical fail bit map is expanded in the fail bit memory 40 (S40). When data is temporarily stored in the sort memory 20, the row fail bit counter 50 counts the number of fail bits of the page. When data is written from the sort memory 20 to the fail bit memory 40, the column fail bit counter 60 counts the number of fail bits of each IO data. Thus, when the physical fail bit map is expanded in the fail bit memory 40, the row fail bit counter 50 and the column fail bit counter 60 already have the number of fail bits of each page and the number of fail bits of each IO data. Each result is complete.

  Therefore, the memory test apparatus 1 according to the present embodiment can perform processing faster than the processing executed by the CPU and software as in the prior art, and accordingly, the failure analysis time can be shortened. Further, the memory test apparatus 1 according to the present embodiment suffices to incorporate a logic circuit in the memory test apparatus 1, and it is not necessary to separately prepare a server for failure analysis.

(Modification)
FIG. 11 is a block diagram illustrating an example of the configuration of the logical-physical conversion unit 10 and the data mapping unit 15 according to a modification of the present embodiment. FIG. 12 is a block diagram showing an example of the internal configuration of the mapping circuit 16 according to a modification of the present embodiment.

  The memory inspection device 1 according to this modification further includes a plurality of mapping setting units 14 and a mapping selector 114. The plurality of mapping setting units 14 have different mapping settings. The mapping setting is a setting indicating the relationship between the bit arrangement in the column data output from the memory under test 2 and the physical bit arrangement of the column data in the memory under test 2. The mapping selector 114 can selectively output one of the plurality of mapping setting units 14 to the mapping circuit 16 using a part of the logical address from the address selector 11. Thereby, the mapping selector 114 can selectively output one of a plurality of mapping settings by using a part of the logical address, similarly to the selection of the logical-physical conversion table. In this way, a plurality of mapping setting units 14 may be provided.

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope and gist of the invention, and are also included in the invention described in the claims and the equivalents thereof.

DESCRIPTION OF SYMBOLS 1 ... Memory test apparatus, 2 ... Memory under test, 10 ... Logical-physical conversion part, 15 ... Data mapping part, 20 ... Sort memory, 30 ... Burst address generation part, 40 ... Fail bit memory, 50 ... Low fail bit counter, 60 ... Column fail bit counter

Claims (6)

A first conversion for storing a conversion table indicating a correspondence relationship between a logical address of data output from the device under test and a physical address of the device under test, and converting the logical address to the physical address based on the conversion table And
A second converter for converting and outputting data having the same physical address output from the device under test in the order of physical storage arrangement in the device under test;
A first memory for storing data from the second conversion unit at a position according to the physical address in the order of output from the second conversion unit, and storing the stored data in the first memory; A first memory that outputs in physical storage array order at
A memory test apparatus comprising: a second memory that stores data stored in the first memory in a physical storage arrangement order in the first memory. A first counter for counting fail bits of data from the first conversion unit for each writing unit or reading unit;
The memory test apparatus according to claim 1, further comprising: a first count memory that stores the number of fail bits counted by the first counter for each of the write unit or the read unit. An adder that adds the number of fail bits at each data storage position of the first memory each time data is stored in the first memory;
The memory test apparatus according to claim 1, further comprising a second count memory that stores an integrated value of the number of fail bits at each data storage position of the first memory. A burst address generation unit for generating a burst address composed of continuous numerical values;
4. The memory test according to claim 1, wherein the first memory outputs data to the second memory in accordance with a physical storage arrangement order in the first memory according to the burst address. 5. apparatus. The first memory includes a first sort memory and a second sort memory,
The second sort memory outputs data to the second memory during a period in which the data from the second conversion unit is stored in the first sort memory,
5. The data output device according to claim 1, wherein the first sort memory outputs data to the second memory during a period in which data from the second conversion unit is stored in the second sort memory. The memory test apparatus described in 1. The first memory includes a first sort memory and a second sort memory,
The second sort memory outputs data to the second memory during a period in which the data from the second conversion unit is stored in the first sort memory,
The first sort memory outputs data to the second memory during a period in which the data from the second conversion unit is stored in the second sort memory,
A plurality of second count memories are provided corresponding to the first and second sort memories;
In the period when the data from the second conversion unit is stored in the first sort memory, and the second sort memory is outputting the data to the second memory, the addition unit is configured so that each of the second sort memories Is added to the number of fail bits at each data storage position stored in one of the second count memories, and the number of fail bits obtained after the addition is added to the other second count memory. Stored in
The data from the second conversion unit is stored in the second sort memory, and the addition unit is configured so that each of the first sort memories is in a period during which the first sort memory outputs data to the second memory. Is added to the number of fail bits at each data storage position stored in the other second count memory, and the number of fail bits obtained after the addition is added to the one second count memory. The memory test apparatus according to claim 3 , wherein the memory test apparatus is stored in the memory test apparatus.

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