JP4929868B2 - Semiconductor memory test equipment - Google Patents

Description

 The present invention relates to a semiconductor memory test apparatus for generating a memory address by calculation in a tester apparatus for testing a memory device and a memory built in an LSI.

 Conventionally, a semiconductor memory test apparatus writes data into a memory under test, reads the write data into the memory, compares it with an expected value, and compares the comparison result between the read data and the expected value into a determination memory for failure analysis. Store. The memory under test is usually configured to have a certain amount of spare lines for each of the X and Y lines (or row lines and column lines) in order to relieve defective cells.

 The conventional defect determination memory has X and Y line defect memories separately, and is not defined for setting the number of XY lines, or is fixedly limited to a certain amount (for example, Patent Documents). 1).

 In addition, when the cell under test is captured with the two-dimensional coordinates of X and Y as shown in FIGS. 13 and 14, the (X, Y) cell whose comparison result with the expected value does not match is determined as a defective cell. . Here, in the process of comparing all the X and Y coordinates, the number of defective cells is counted for each line of X or Y, and when the number of defective cells exceeds a threshold value, the line is determined as a defective line. To do. Further, by comparing the expected values of the subsequent lines without counting the number of defects thereafter, it is possible to eliminate the need to compare the lines for which the defects have been determined, thereby realizing high-speed testing. At this time, the memory under test is relieved by replacing the entire line where the defect is determined with a spare line.

 On the other hand, various methods are actually conceivable for the semiconductor memory test as described above. For example, first, a search is made for the presence or absence of defective cells for each line in all X and Y regions, and only the X or Y line data for which the number of defective cells exceeds the threshold at that time is stored in the status memory (line (Determined memory). As shown in FIG. 14, a memory having an address corresponding to each line of the memory under test is prepared, and when a bit “1” is stored in each address of the memory, defective cells in the line are masked. Having a simple mask memory.

In the test method having such a configuration, the information of the confirmed fail line stored in the status memory is copied to the mask memory and used, so that a new defect is generated for the X and Y lines in which a certain number or more of defective cells exist. Even if there is a cell, it is possible to perform a high-speed operation such as counting the number of defective cells remaining in a state where the defective cells of the corresponding line are not counted by applying a mask and the line where the defect is confirmed is excluded. Alternatively, while storing the information of the determined fail line in the process of searching for a defective cell, it is possible to mask the search of the same line after the defective line of a certain line is determined by copying it to the mask memory in an efficient manner. A memory test can be performed.
JP 58-5681 A

 However, the configuration of the status memory and the mask memory as described above is prepared separately for the X and Y lines as shown in FIGS. 15 and 16, and is equally stored in the maximum number of X or Y lines. It has been considered to secure the address depth of the XY lines or to share the addresses of the XY lines with a capacity of 1/2 of one memory.

 On the other hand, the number of X and Y lines is desired to be set to an arbitrary number of lines as much as possible within a range where the total number of lines does not exceed the maximum value in terms of hardware constraints. Therefore, if memories and addresses are prepared for each of the X, Y status memory, mask memory (X), and mask memory (Y), memory addresses corresponding to the number of unused lines are wasted, or an arbitrary number of lines. When the memory area is to be secured, there is a possibility that the memory is insufficient due to a restriction by the maximum value of the number of one of X and Y lines.

 Also, when copying the status memory information to the mask memory at high speed or reading the X and Y line mask memory data and the status memory data at high speed, it is difficult to read the X and Y simultaneously. Was a problem. For example, in the configuration of FIG. 16, there is an advantage that the number of lines can be secured up to the maximum physical depth of the status memory / mask memory. When executing access, there is a problem that high speed operation cannot be performed because two accesses of X and Y are required for the same memory.

 The present invention has been made to solve such a problem, and relates to a status memory and a mask memory for storing fail information for a memory test apparatus, and assures design freedom of search areas for the number of X and Y fail lines, It is an object of the present invention to provide a semiconductor memory test apparatus capable of executing memory access, copying of information between a status memory and a mask memory, and reading of each memory at high speed and efficiently.

The present invention has been made to solve the above problems, and the invention according to claim 1 counts defective cells at the time of a memory test in two directions of a row line and a column line, and determines a defective line from the counting result. In the semiconductor memory testing apparatus that performs the determination, the first status area in which the defective line information for the row line is stored and the first mask area in which the information of the line that does not need to be counted for the column line are stored. A first storage means arranged so that the first status area is first and addresses are continuous; a second mask area in which information of lines not requiring counting for the row line is stored; and a column line Arranged so that the second mask area is first and the address is continuous with the second status area in which defective line information is stored Second storage means, first transfer means for inputting output data from a read terminal of the second storage means to a write terminal of the first storage means, and reading of the first storage means A semiconductor memory test apparatus comprising: second transfer means for inputting output data from a terminal to a write terminal of the second storage means .

 According to the present invention, access to each memory, copying of information between the status memory and the mask memory, and reading of each can be performed at high speed and efficiently.

 In addition, the contents of two types of memory such as a status memory and a mask memory can be cleared individually and collectively at high speed and easily by incrementing an address counter and a selector.

 Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a configuration diagram showing the configuration of the semiconductor memory test apparatus according to the present embodiment. The semiconductor memory test apparatus according to the present embodiment includes dual port memories M1 and M2, selectors DATSEL1, ADRSEL1, DATSEL2, ADRSEL2, and SEL, a NOR element R, and an AND element A. Signals WDATA1 and WDATA2 are write signals to the dual port memories M1 and M2. The signal LINE is a signal for designating line numbers of the dual port memories M1 and M2.

In FIG. 1, the description of the clock signal is omitted. This does not limit the asynchronous / synchronous memory. The semiconductor memory test apparatus according to the present embodiment determines a memory under test in line units in two directions of a row line (X direction) and a column line (Y direction) . The dual port memory M1 includes an X-direction mask memory (X) and a Y-direction status memory (Y). The dual port memory M2 includes a mask memory (Y) and a status memory (X). The dual port memories M1 and M2 can always write data. The dual port memories M1 and M2 can write data when a write request signal is input.

 In the dual port memory M1, mask memory (X) and status memory (Y) are arranged in this order. In the dual port memory M2, the status memory (X) and the mask memory (Y) are arranged in this order. The line number is the number of lines when the search result memory (mask memory and status memory in the dual port memory) in the X and Y directions is regarded as a series of lines. It is also possible to use a memory having a read request signal. Each selector can select a signal path to each or both of the dual port memories M1, M2.

 The signal XMADR is a read line address of the mask memory (X) of the dual port memory M1. The signal YMADR is a read line address of the mask memory (Y) of the dual port memory M2. Signals WDATA1 and WDATA2 are write data signals to the dual port memories M1 and M2, respectively.

 The signal XLNUM is a setting signal related to the number of X lines for designating the number of X and Y boundary lines. The signal WREQ is a memory write request signal for enabling writing of write data to each memory. The signal Status / Mask is a status memory / mask memory selection switching signal. When it is “H”, the status memory is selected, and when it is “L”, the mask memory is selected. The signal Copy / Normal is a signal for switching the copy operation / normal operation of the status memory. When it is “H”, the copy operation is selected, and when it is “L”, the normal operation is selected.

 Signals ASEL1 and ASEL2 are address select signals for the dual port memories M1 and M2, respectively. Signals DSEL1 and DSEL2 are data select signals for the dual port memories M1 and M2, respectively. Signals WREN1 and WREN2 are memory enable signals for the dual port memories M1 and M2, respectively.

 The dual port memory M1 includes a read address signal RADR1, a read data signal RDAT1, a write address signal WADR1, a write data signal WDAT1, a write enable signal WREN1, and a read address terminal RADRE1, a read data terminal RDATA1, and a write data signal. Each terminal has an address terminal WADRE1, a write data terminal WDATA1, and a write enable terminal WEN1.

 The dual port memory M2 has a read address signal RADR2, a read data signal RDAT2, a write address signal WADR2, a write data signal WDAT2, a read enable signal WREN2, and a read address terminal RADRE2, a read data terminal RDATA2, and a write data Each terminal has an address terminal WADRE2, a write data terminal WDATA2, and a write enable terminal WEN2.

 The signal WDATA1 is connected to the terminal A of the selector DATSEL1. The terminal B of the selector DATSEL1 is connected to the read data terminal RDATA2 of the dual port memory M2, and the terminal Y of the selector DATSEL1 is connected to the write data terminal WDATA1 of the dual port memory M1. The terminal S of the selector DATSEL1 is connected to the output terminal DSEL1 of the selector SEL.

The signal XMADR is input to the terminal A of the selector ADRSEL1. The signal WADR1 is input to the terminal B of the selector ADRSEL1, and the terminal is connected to the write address terminal WADRE1 of the dual port memory M1. The terminal Y of the selector ADRSEL1 is connected to the read address terminal RADRE1 of the dual port memory M1. The terminal S of the selector ADRSEL1 is connected to the output terminal ASEL1 of the selector SEL.

 The signal WDATA2 is connected to the terminal A of the selector DATSEL2. The terminal B of the selector DATSEL2 is connected to the read data terminal RDATA1 of the dual port memory M1, and the terminal Y of the selector DATSEL2 is connected to the write data terminal WDATA of the dual port memory M2. Further, the terminal S of the selector DATSEL2 is connected to the output terminal DSEL2 of the selector SEL.

The signal YMADR is input to the terminal A of the selector ADRSEL2. The signal WADR2 is input to the terminal B of the selector ADRSEL2, and the terminal is connected to the write address terminal WADRE2 of the dual port memory M2. The terminal Y of the selector ADRSEL2 is connected to the read address terminal RADRE2 of the dual port memory M2. The terminal S of the selector ADRSEL2 is connected to the output terminal ASEL2 of the selector SEL.

 The output terminal of the write enable signal WREN1 of the selector SEL is connected to the write enable terminal WEN1 of the dual port memory M1, and the output terminal of the write enable signal WREN2 is connected to the write enable terminal WEN1 of the dual port memory M2. The signals XMADR, YMADR, WADR1, WADR2, XLNUM, WREQ, Status / Mask, and Copy / Normal are input to the selector SEL.

The read data terminal RDATA1 of the dual port memory M1 and the read data terminal RDATA1 of the dual port memory M2 are input to the NOR element R, and the output signal of the NOR element R is input to the AND element A together with the signal FailData. The AND element A outputs X / Y mask data.

 FIG. 2 is a configuration diagram showing an example of the internal configuration of the dual port memories M1 and M2. As shown in FIG. 2, in the configuration of two memories, a mask memory (X) / status memory (Y) and a status memory (X) / mask memory (Y), respectively. As described above, the mask memory / status memory is nested in the dual port memory. The mask memory (X) / status memory (Y) includes a mask line (X) area and a status line (Y) area, and the status memory (X) / mask memory (Y) is a status line (X) area. And a mask line (Y) region.

 Each memory can be used to the maximum in the depth direction (vertical direction in FIG. 2), and in the example of FIG. 2, arbitrary values of m and n can be selected for up to (m + 1) + (n + 1) lines. The mask memory and status memory can be read simultaneously by two dual port memories.

 FIG. 3 is an example of a mask memory address conversion circuit arranged in the previous stage of the semiconductor memory test apparatus according to the present embodiment. FIG. 4 is a diagram showing the address correspondence relationship of this mask memory address. FIG. 5 is a graph showing the address correspondence between XY addresses and line numbers. The mask memory address conversion circuit shown in FIG. 3 receives the X and Y addresses XA and YA, the X area start address XSA, and the X and Y area end addresses XEA and YEA, respectively, and the X and Y line mask addresses. XMADR, YMADR, and the number of X lines XLNUM are output.

In FIG. 4, the start address XSA of the X area, the start address YSA of the Y area, the end address XEA of the X area, the end address YEA of the Y area, the X address XA, and the Y address YA are described. . Here, the mask addresses XMADR and YMADR for the X and Y lines are expressed by the following equations (1) and (2), respectively.
XMADR = XA-XSA (1)
YMADR = YA-YSA + (XEA-XSA + 1)
= YA-YSA + XLNUM (2)
FIG. 5 shows a mask memory (X) / status memory (Y) and a status memory (X) / mask memory (Y), respectively. Here, the line number XLNUM of X is used for determining each area of the mask memory (X) / status memory (Y) by line number or determining each area of the status memory (X) / mask memory (Y).

Next, the operation of the semiconductor memory test apparatus according to the embodiment of the present invention will be described. First, the operation contents at the time of reading data from the mask memory (X) and the mask memory (Y) are shown. Here, the input signals WREQ, Status / Mask, and Copy / Normal are all set to “L”. The read line addresses of the mask memory (X) and the mask memory (Y) are input by signals XMADR and YMADR, respectively, and input to the terminals A of the selectors ADRSEL1 and ADRSEL2, respectively. In the selectors ADRSEL1 and ADRSEL2, a path is selected for the terminal A , and the signal is input from the terminal Y to the read address terminals RADRE1 and RADRE2 of the dual port memories M1 and M2.

 In the dual port memories M1 and M2, the data in the mask memory at the corresponding address is read as signals RDAT1 and RDAT2 from the read data terminals RDATA1 and RDATA2, respectively. At this time, an AND output of the NOR outputs of the signals RDAT1 and RDAT2 and the signal FailData from the outside at the time of search is output as fail information after masking.

 FIG. 6 is a timing chart of signals at the time of reading data from the mask memory (X) and the mask memory (Y). The example of FIG. 6 is for the case where the latency of each dual port memory is 1. As shown in FIG. 6, the signals WREN1 and WREN2 remain “L”, read address signals RADR1 and RADR2 are input in synchronization with the clock signal CLK, and read data signals RDAT1 and RDAT2 are read one clock later. Has been issued.

 Next, operation contents at the time of writing data to the mask memory (X) and the mask memory (Y) will be described. Here, the input signals Status / Mask and Copy / Normal are set to “L”. The signal WREQ becomes “H” when data is written. In FIG. 1, the write enable signal WREN1 becomes active when writing to the mask memory (X), and the write enable signal WREN2 becomes active when writing to the mask memory (Y), and is input to the write enable terminals WEN1 and WEN2 of the dual port memories M1 and M2, respectively. Is done.

 From the signal LINE, the line numbers of the mask memory (X) and the mask memory (Y) are input and input to the write address terminals WADRE1 and WADRE2 of the dual port memories M1 and M2, respectively. The signals WDATA1 and WDATA2 are input to the terminals A of the selectors DATSEL1 and DATSEL2, and are routed to the terminal Y in the selectors DATSEL1 and DATSEL2. Here, the write data is input from the selectors DATSEL1 and DATSEL2 to the write data terminals WDATA1 and WDATA2 of the dual port memories M1 and M2, respectively. In the dual port memories M1 and M2, input data is written to the address of the corresponding line number. Also, when writing to the status memory, the same operation is performed except that the signal LINE, WREN1, WREN2 and the selector path setting are different.

 FIG. 7 is a timing chart of signals at the time of writing the mask memory (X) and mask memory (Y) data. The example of FIG. 7 is for the case where the latency of each dual port memory is 1. As shown in FIG. 7, the write address signals WADR1 and WADR2 and the write data signals WDAT1 and WDAT2 inputted at the timing when the signals WREN1 and WREN2 become “H” are respectively stored in the dual port memories M1 and M2 with a delay of one clock. The

Next, the operation contents of reading the status memory when copying data from the status memory to the mask memory are shown. Here, the input signals Status / Mask and Copy / Normal are set to “H”. The signal WREQ becomes “H” when data is written. In FIG. 1, the address of the status memory read by the signal LINE is input. When reading the status memory (X), the terminal B of the selector ADRSEL 2 is read. When reading the status memory (Y), the terminal B of the selector ADRSEL 1 is read. Is input.

Signal ASEL2, ASEL1 selector by becomes active ADRSEL2, ADRSEL1 is routed to terminal B, and terminal Y, the input read address to the read address terminal RADRE2, RADRE1 the dual port memory M1, M2. In the dual port memories M1 and M2, the data in the status memory at the corresponding addresses are read as signals RDAT1 and RDAT2 from the read data terminals RDATA1 and RDATA2, respectively.

Next, operation contents of mask memory writing at the time of copying data from the status memory to the mask memory will be described. When the signals DSEL2 and DSEL1 are activated, the selectors DATSEL2 and DATSEL1 are routed from the terminal A to the terminal B. The signals RDAT1 and RDAT2 read here are input to the write data terminals WDATA2 and WDATA1 of the dual port memories M2 and M1, respectively. Further, the write destination address is input from the signal LINE to the write address terminals WADRE2 and WADRE1 of the dual port memories M2 and M1. The signals WREN2 and WREN1 become active at the data write timing of the dual port memories M2 and M1, respectively.

 FIG. 8 is a timing chart of each signal when copying data from the status memory to the mask memory. The example of FIG. 8 is for the case where the latency of each dual port memory is 1. As shown in FIG. 8, the read data signals RDAT1 and RDAT2 are read one clock after the read address signals RADR1 and RADR2 are input, and the signals WREN1 and WREN2 are set to “H” at the same timing as the read data signals. After the write address signals WADR2 and WADR1 and the write data signals WDAT2 and WDAT1 are output, the write data signals WDAT2 and WDAT1 are stored in the mask memories of the dual port memories M2 and M1, respectively, one clock later.

 Further, as shown in FIGS. 9 to 11, regarding the erasure of the memory contents, the status memory and the mask memory are collectively set by incrementing the address while the write data is fixed at zero in the semiconductor memory test apparatus of the present embodiment. Or it can be cleared individually. As a result, the memory can be erased at high speed.

 Thus, the following effects can be obtained by nesting the status memory and mask memory in the dual port memory. By switching write data to multiple memories to be written by the selector and simultaneously enabling write request signals to the same memory, it becomes possible to simultaneously write to any of the mask memory and status memory. . Further, for example, when a cell in the X direction in the search area of the memory under test is expanded and a cell in the Y direction is reduced, the status memory / mask memory in the X direction is expanded, and the status memory / mask memory in the Y direction is reduced. The status memory / mask memory can be changed to an appropriate size in accordance with the situation of the XY search area. Thus, the XY search area at the time of the memory test is not limited, and the status mask memory can be used up to the maximum area of the memory.

 FIG. 12 is a configuration diagram showing a configuration of a modified example of the semiconductor memory test apparatus according to the present embodiment. The semiconductor memory test apparatus of FIG. 12 is an example when the write address is generalized. The changes from the semiconductor memory test apparatus shown in FIG. 1 are as follows. The signals WADR1 and XMADR are input to the selector SEL and the signal ASEL1 is output, and the signal WADR1 is input to the read address terminal RADR of the dual port memory M1 via the selector ADRSEL1. Separately, the signals WADR2 and YMADR are input to the selector SEL and the signal ASEL2 is output, and the signal WADR2 is input to the read address terminal RADR of the dual port memory M2 via the selector ADRSEL2.

 Therefore, the signal of the line number of the status / mask memory can be set for each of the dual port memories M1 and M2. The operation of the semiconductor memory test apparatus of FIG. 12 is the same as that of FIG. 1 except that the signals XMADR and YMADR which are read line addresses of the mask memory (X) and the mask memory (Y) of the dual port memories M1 and M2 are input, respectively. This is the same as the embodiment.

 In the case of having two-dimensional parameters such as X and Y addresses and storing and using two pieces of information in a memory, the relationship between the two-dimensional parameters and the function types is as shown in this configuration. By configuring the memory, it is possible to use the memory capacity without waste while maintaining the simultaneity and independence of access for the two parameters. Thereby, cost reduction and speeding-up can be achieved, and it is possible to apply a semiconductor test apparatus or the like with a similar configuration.

It is a block diagram which shows the structure of the semiconductor memory test apparatus concerning embodiment of this invention. It is a figure which shows an example of the memory structure in the dual memory of the semiconductor memory test apparatus concerning embodiment of this invention. It is an example of a mask memory address conversion circuit arranged in the previous stage of the semiconductor memory test apparatus according to the present embodiment. It is a figure which shows the address correspondence of a mask memory address. It is the figure which displayed the address correspondence of XY address and Line number as a graph. It is a timing chart of each signal at the time of reading of mask memory (X) and mask memory (Y) data. It is a timing chart of each signal at the time of writing of mask memory (X) and mask memory (Y) data. It is a timing chart of each signal at the time of data copy from a status memory to a mask memory. It is a figure which shows the operation | movement content at the time of the erasure | elimination of the memory content of a mask memory. It is a figure which shows the operation | movement content at the time of the erasure | elimination of the memory content of a status memory. It is a figure which shows the operation | movement content at the time of the batch erase of the memory content of a mask memory and a status memory. It is a block diagram which shows the structure of the modification of the semiconductor memory test apparatus concerning this embodiment. FIG. 3 is a diagram showing a correspondence relationship between a status memory and a memory search area of a memory under test. FIG. 4 is a diagram showing a correspondence relationship between a mask memory and a memory search area of a memory under test. It is the figure which showed an example which prepared the status memory and mask memory of the prior art separately for X and Y lines. It is a figure which shows the example which has arrange | positioned and secured the address of each XY line with the capacity | capacitance of 1/2, arrange | positioning the status memory and mask memory of a prior art.

Explanation of symbols

  M1, M2 ... dual port memory, DATSEL1, ADSSEL1, DATSEL2, ADSSEL2, SEL ... selector, A ... AND element, R ... NOR element

Claims (1)

In a semiconductor memory testing apparatus that counts defective cells at the time of a memory test in two directions of a row line and a column line and determines a defective line from the counting result.
A first status area in which defective line information for the row line is stored, a first mask area in which information on a line that does not need to be counted for the column line is stored , and the first status area is first. First storage means arranged so that addresses are continuous ;
A second mask area in which information of lines not requiring counting for the row line is stored, a second status area in which defective line information for the column line is stored , and the second mask area is first. Second storage means arranged so that the addresses are continuous ;
First transfer means for inputting output data from a read terminal of the second storage means to a write terminal of the first storage means;
2. A semiconductor memory test apparatus comprising: second transfer means for inputting output data from a read terminal of the first storage means to a write terminal of the second storage means .

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