JPS61223956A - Store buffer control system - Google Patents

Abstract

PURPOSE:To improve the throughput of write to a main storage by reading out a buffer to be written to the main storage and the next buffer at the same time, and completing an access to the main storage by once, when the higher ranks of main storage addresses of both said buffers have coincided with each other. CONSTITUTION:A data bus width for write to a main storage is set to two times of a data width of an internal buffer of a store buffer 10, and the internal buffer 2 is constituted of a 2 port RAM 21. A buffer to be written to the main storage and the next buffer are read out at the same time, and when the higher ranks of main storage addresses of both the buffers have coincided with each other, an access to the main storage is completed by once by a swap of both data. In this way, the throughput of write to the main storage of the internal buffer of the store buffer can be raised.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a store buffer control method for a processing device [Background of the Invention] First, an outline of the store buffer, which is the main focus of the present invention, will be explained.

FIG. 2 shows an example of a processing device. Basic processing mechanism (BP)
U) 1 decodes and executes programs, and a memory control unit (MCU) 2 supports access to a main memory (MS) 3 from a basic processing unit (BPU) 1 or an input/output path 8. Programs are stored in the main memory (MS>3).For example, the input/output path 8 includes a file control mechanism (FCP).
4 is connected, file (DISK) 5 and input/output path 8
supports data transfer between A store buffer is generally provided within the memory control unit (MCU) 2.

FIG. 3 shows the configuration of the memory control mechanism 2. As shown in FIG.

The cache memory 9 has a content coherer for a part of the main memory, and stores therein the corresponding content in response to a read request requested via the internal bus 14 from the interface 6 with the basic processing mechanism or the input/output bus 8. When this is the case, it is passed, and when it is not, the block containing the relevant part is read out from the main memory and newly stored internally, thereby speeding up the reading process. Similarly, in response to write requests requested via the internal bus 14, the store buffer 10 stores them in the internal buffer one after another, and speeds up writing by writing them to the main memory later. . but,
Regarding writing to main memory, the method of writing internal buffers to main memory one after another has the following drawbacks. Recent trends in programs are that programs are becoming more modular, the frequency of subroutine linking is increasing, system programs that use the stack to pass arguments for work and subroutine linking have become mainstream, and the execution of logical languages. As a high-speed execution method using multiple stacks has been proposed, the frequency of writing to stacks is increasing. In the past, the read/write ratio was about 9:1, but recently it has changed to about 7:3. Therefore, in a method in which the internal buffers of the store buffer are written one after another to the main memory, this part becomes a performance bottleneck.

In Japanese Unexamined Patent Publication No. 56-54558, "Main memory write control method", the store buffer is configured with a shift register, and the address being written is compared with the address in the last stage of the shift register. If both are write requests to the same access unit of the storage device, a method is described in which the data in the final stage of the shift register is merged with the write data being executed, and the process is completed in one write operation. . However, in this method, since the buffer is a shift register, it takes time for the input data to be output, and if there is a cache miss, reading from the storage device must wait until the contents of the shift register are flushed out, or write data cannot be read. The disadvantage of merging in the middle is that it cannot cope with improvements in the speed of the main memory, and that a special merging circuit must be provided.

[Purpose of the invention]

An object of the present invention is to provide a store buffer control method that can increase the throughput of main memory writing of the internal buffer of the store buffer by simply adding hardware.
[Summary of the Invention] The present invention makes the data bus width for writing to the main memory twice the data width of the internal buffer of the store buffer, configures the internal buffer with two ports R and AM, and writes to the main memory. The present invention is characterized in that the buffer to be read into the buffer and the next buffer are simultaneously read, and when the high order of the main memory addresses of both match, the main memory access is completed in one go by swapping both data.

[Embodiments of the invention]

Examples of the present invention will be described below.

FIG. 1X1 shows the internal configuration of the store buffer 10. The internal buffer (BUF) 21 is composed of a 2-bot RAM. Input data 46 and output data 49 correspond to the next buffer selected at address 47, and output data 50 corresponds to the buffer selected at address 48. address 47
When writing, the output of the write pointer 24 is
At the time of continuous reading, the output of the read pointer 25 is selected.

The continuous output pointer +1 is input to the address 48 by the +1 adder 26. Therefore, the contents of the buffer to be written to the main memory are stored in the output latch 22.
3, the contents of the next buffer are latched. The data part of both latches (4 bytes each) is selector 29.30
Otherwise, the data for main memory access is output to the upper 52 (4 bytes) and lower 53 (4 bytes) by direct through, or it is swapped and output to the lower 53 and upper 52.
is output to. Whether or not to swap is determined by the function control section 28 by referring to the function section and address section of both latches. The function control unit 28 also generates a main memory access function 36. The store controller 37 receives a write request from the internal bus and stores the access information (functions, addresses, data) in the internal buffer 21, while reading the access information one after another from the internal buffer 21 and writing it to the main memory. The internal configuration of the function control section 28 is shown in Figure N4.

The decoder 61 is the function section 31 of latch A.
It detects that it is a Byte Write and sets the signal 70 to 1 only in this case. The decoder 63 outputs that the lower three bits of the address section 32 of latch A = IXX (x is arbitrary), and sets the signal 72 to 1 only at this time. In the decoder 64, the function section 33 of latch B is 4 B
yte Write is detected, and the signal 73fcl is set only in this case. The decoder 66 detects that the lower three bits of the address section 34 of latch B==IXX, and sets the signal 75 to 1 only at this time. The comparator 69 reads the upper bit 6 of the address of latch A except for the lower 3 bits.
7 and the upper bits 68 of latch B excluding the lower 3 bits, and when they are equal, the signal 76 is set to 1. AND circuit 77 outputs signals 70, 73, 76″ft-human power and signal 78
Output. Therefore, signal 78 becomes 1 only when the upper bits of the addresses of both latch A and latch B, excluding the lower 3 bits, are the same and both latch A and latch B are 4-byte write.

EXCLU8IV OfL circuit 79ha (No. 1 72
,! : 75 is manually operated, and its output and signal 78 are A.
The signal is input to the ND circuit 80. Therefore, its output is the 3 bits of address F of latch A and the lower 3 bits of address of latch B.
One of the bits is 1XX and the other is oXX, and the lower 3 bits of the address of both latch A and latch B are equal except for the lower 3 bits t, and both latch A and latch B are 4.
When it is Byte Write, it becomes IK. Only when this signal is 1, the selector 84 selects 8 Byte W
rite pattern is selected, and if not, the function section of latch A is selected. The selection result is the main memory access function 36. On the other hand, the AND circuit 81 inputs the signal 78 and the negation of the signal 75, and
Circuit 82 receives the negation of signal 78 and signal 72 as inputs, and outputs O
The R circuit 83 receives the outputs of both AND circuits, and the output of the OR circuit 83 is the swap signal 35.

When this signal = 00, the data section to the launch is connected to the upper part of the main memory access data, and the data part of latch B is connected to the lower part of the main memory access data, and when the same signal = 1, the data part is connected to the upper part of the data for main memory access.

In FIG. 5, the main memory access function 36 is 8
The relationship between the conditions and data connection when the f3yte Write occurs and when the swap signal 35 becomes IK is shown. In the figure, the portions shown in parentheses in the MDU and MDL sections indicate that writing to the main memory is not performed. In addition, AI in the figure
, A2 is an 8-byte write, and the contents of the two buffers are written to the main memory once to achieve high speed.Furthermore, 43.44 is a 4-byte write, but since it is written to the same address, Speeding up is achieved by writing only what is written from the main memory into the main memory.

FIG. 6 shows the internal configuration of the store buffer control section 37. The main control section consists of a status register 91 that is updated every clock and a next pattern generation logic circuit 92. FIG. 7 shows a status transition diagram of the store buffer control section 37. Status 101 is the initial IDLE state, write pointer 55 (WP) and read pointer 56 (P
) is less than the maximum value, that is, when there is space in the internal buffer 21, a write request 38 (WR, E
Q) goes to status 102. In this status, internal buffer write signal 45 (WE) t-
Turn on. Then move on to the next status. Next tD
In the f-tas 103, the write pointer increment signal 41 (WPUP)t is turned on, and the response signal 39 (ACK) to the internal bus is turned on. Then, the process advances to status 104. In status 104, latch signal 5
1 (LA'l') is turned on, and in the next status 105, the main memory write request 43 <MWREQ) is turned on. Then it jumps to WAIT state 106. In this state,
When there is still space in the internal buffer and the write request 38 (WREQ) from the internal bus is turned on, the process advances to status 107. In this status, the internal buffer write signal 45 (WE) is turned on, and in the next status 108, the write pointer increment signal 41 (WPUP) is turned on, and the process returns to the WAIT state 106 again. Same < WA
When the response 44 from the main memory is turned on in the IT state 106, if the signal 78 (EQ) is turned on, the process goes to status 109, then goes to 110, and the read pointer increment signal 42 (RPUP) is incremented twice. Turn on. When signal 78 is off, proceed to 110, resulting in 4
2 (几PUP) turns on once.

After that, the internal buffer is free, i.e. the write pointer (
Step 10 when WP) = successive pointer (RP)
If not, proceed to Stella 7”104.

In this way, data enters the internal buffer one after another,
They are written to the main memory one after another, and in the case of writing to the main memory, the signal 78 (EQ) is on, that is, both latch A and latch B are 4 ByteWrite, and the lower 3 bits of both addresses are excluded. When the upper bits are equal, two internal buffer entries are processed in one main memory access, improving the write throughput. Including the case of the same address regardless of the address order,
When writing the store buffer to the main memory, the lc2 entry can be accessed only once to the main memory, and the stack operation, which is a bottleneck in the performance of the processing device, can be speeded up.

[Brief explanation of the drawing]

FIG. 1 is an internal configuration diagram of a store buffer lO according to an embodiment of the present invention, FIG. 2 is a diagram showing an example of a processing device that is the background of the present invention, and FIG. 3 is a diagram showing the memory control in FIG. Fig. 4 is a block diagram of the function control unit according to an embodiment of the present invention, Fig. 5 is a diagram showing the relationship between the conditions and output of the function control unit, and Fig. 6 is a diagram showing the relationship between the conditions and output of the function control unit. The internal configuration diagram, FIG. 7, shows a status transition diagram of the store buffer control section. lO...Store buffer, 21...2 Ho) R
, AM. Inspection Z mouth No. 30 No. 4-(!ll

Claims (1)

[Claims] 1. In the store buffer of the processing device, 1 of the buffer
The write data width of the storage device is twice the write data width of the entry for the upper data bus and the lower data bus, and the buffer is configured with a 2-port RAM. means for simultaneously reading the second entry of the first entry, and whether the write data of the first entry is on-bused to the upper data bus and the write data of the second entry is on-bused to the lower data bus or by swapping. and a means for comparing the addresses of both entries and detecting whether the accesses are to the same access unit of the storage device. A store buffer control characterized in that by controlling the swap according to whether it is a lower access, upper and lower accesses can be completed in one time, and that accesses between upper and lower levels or between lower levels are written only by those who will write later. method.