JPH10240525A - Information processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To extend a register set which has a different depth register value by substituting information of a memory line which is made to correspond by a depth register for a register file when the contents of the depth register are updated. SOLUTION: The information processor 1 has a data memory 102, the register file 103, and an arithmetic circuit 109 mounted on the same chip. A column pointer 104 stores information for discriminating line memory lines 101 and its numeric information is decoded by a column selecting circuit 105 into a select signal for the memory lines 101. When data of the memory lines 101 are transferred to the register file 103, the contents of the column pointer 104 are written in the depth register. In this case, when the contents of the depth register are updated, the information of the memory lines 101 which are made to correspond through the depth register is substituted for the register file 103.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus in which the processing content is controlled by a sequence of instructions, and more particularly to an information processing apparatus comprising an LSI or the like equipped with a large-capacity memory, and The present invention relates to an information processing apparatus having the same arithmetic processing function for data.

[0002]

[Prior Art] With the improvement of LSI process technology,
A large-capacity memory such as DRAM and a large-scale logic circuit such as a microprocessor, which are configured as separate components, can be realized on the same chip. In a device whose operation can be controlled by a program such as a microprocessor, it is necessary that data in a large-scale memory can be specified by a command word, and a specification method must be defined. A register window is known as a method of referring to a memory resource in a processor as a so-called architectural register (a register readable and writable by a user using an instruction word) (Reference 1: Kisaburo Nakazawa, Computer architecture and configuration method Asakura Shoten 1995)
374-378). A processor having a register window includes a memory having a capacity several times larger than that of the entire architectural register, and a base register for indicating a memory location currently used as a register. The register name (number) included in the instruction word is temporarily converted to a numerical value,
The result of addition with the base register becomes the address of the memory. Thus, by changing the contents of the base register, it is possible to actually read / write more registers than the logical number of registers. This mechanism allows the physical register and the logical register specified by the instruction word to be different from each other. For example, before the reference of a certain register is completed, the preceding load instruction starts loading the same register. Processing becomes possible. That is, if an instruction sequence is used in which data is loaded into register 1 with instruction 1, instruction 2 uses the contents of register 1, and instruction 3 loads data different from instruction 1 into register 1, In order to prevent the malfunction of the instruction 2 caused by overwriting the register 1, the execution of the instruction 3 must wait until the instruction 2 has finished referring to the contents of the register 1. However, each time a load instruction appears, the value of the base register is updated, the following instruction is associated with the base register to refer to the register, and if an instruction to load the same register appears in a subsequent instruction, If the base register is updated again and data is loaded to a physically different location, the above instructions 1 and 3 can be continuously executed.

On the other hand, multimedia including data, sound, still images, moving images, and the like is emerging as a new processing object such as a microprocessor. DSP (Digital) is used for encoding and signal processing, which is the core when processing this multimedia.
Signal Processor) and SIMD (Sing
le Instruction Mutiple Data) processing capacity is effective.
However, for devices where it is important to realize multiple functions with a smaller number of components, such as multimedia devices, avoid the introduction of dedicated processors such as DSPs and vector calculation mechanisms, and implement multimedia processing as an extended function of general-purpose processors. Strong tendency. Shinbo Jimbo: "Latest Microprocessor Technology", an instruction published in Nikkei BP, 1996, divides one data word length (for example, 32 bits) into multiple parts and attempts to realize multiple data processing with one instruction. .
However, since the numerical value that can be expressed when the length of one data word is divided becomes small, it is mainly used for image processing such as pixel data.

[0004]

As described above, in order to realize multimedia processing with a general-purpose microprocessor, it is desirable to introduce a SIMD processing mechanism found in a DSP or a vector processor. However, introducing a dedicated memory such as a data memory of a DSP or a vector register of a vector processor into the architecture involves a drastic change in the user architecture.

Although the register window can store a physical memory while retaining a logical architecture configuration such as a register number, it is not suitable for a large-capacity memory such as a DRAM or a ferroelectric memory. This is because, in the architecture register, a plurality of data can be read and written because a read request and a write request from a plurality of instructions (for example, an operation instruction and a load / store instruction) operating in the processor arrive. This is because the function required for the multiport memory is required. In other words, the physical memory for realizing the register window requires a multi-port memory function for all addresses, and the area is several times larger than that of a single-port memory having the same capacity.

From the above, the problems to be solved by the present invention are the following two points. The first is that without significant changes to the general-purpose processor architecture, such as vector processing,
A second challenge is to implement a SIMD process, and to introduce a large-capacity memory into the architecture without significant architectural changes.

[0007]

As means for solving the first problem, there is provided an operation circuit in which the same operation is performed on a plurality of registers in a register file by one instruction word. Specifically, an architecture register (for example, R0 to
R15, R16 to R31) are considered as vector registers, respectively.
A vector operation function for performing the same operation on the data elements is provided. However, if the vector registers are configured only with the existing architecture registers, the number of vector registers (two in the above-described method) is insufficient. This shortage problem and the second problem are solved by the same means. That is, a register file including a data cell storing one data unit, a memory line composed of data cells arranged in a column, a data memory composed of a plurality of memory lines, and a plurality of registers that can be specified by a command word And a depth register for storing a numerical value corresponding to the memory line, and when the content of the depth register is updated, the register file is replaced with information on the memory line associated with the depth register. As a result, it is possible to add a register set having the same apparent architectural register but different values of the depth register. In addition, since the data memory is not used directly as a register, a large-capacity single-port memory such as a DRAM or an SRAM can be used as the data memory portion.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described with reference to the drawings.

<Outline of Embodiment> FIG. 1 shows an example of the configuration of an information processing apparatus (CPU) for realizing the present invention. In FIG. 1, the inside of the dashed line indicated by the information processing device (CPU) 1 is a portion constituting a so-called one CPU package as a semiconductor chip. In the information processing device 1, the main configuration requirement of the information processing device according to the present invention is that the data memory 102, the register file 103, and the arithmetic circuit 109 are stored in the same chip.

In FIG. 1, a data cell 100 is a recording circuit for storing information of a data length (for example, 32 bits) as a processing unit in an information processing apparatus, and a memory line 101 is constituted by a plurality of data cells. Memory line is normal SRAM or D
Like the internal memory array of the RAM, reading and writing can be performed in line (column) units, and the data memory 102 is constituted by a plurality of memory lines. Register file 103
Are 32 registers identifiable by register names (numbers) R0 to R15 and R16 to R31 as architecture registers (hereinafter simply referred to as registers);
, And depth registers DR0 and DR1 for instructing the operation. Each register can store data length information as a processing unit in the information processing device,
There is a one-to-one correspondence with a data cell in a certain memory line. As will be described later, reading two register contents simultaneously identified by different register numbers from the register file 103 to the arithmetic circuit 109, writing to one load / store circuit 110 or writing from the arithmetic circuit 109, Writing to the data memory 102 is possible. In the present embodiment, writing to the data memory 102 and writing to the register file can be executed independently. Although the number of simultaneously readable and writable data does not particularly limit the content of the invention, the data memory 10
The relationship that the register file 103 is readable and writable in register units and that multiple read and write operations are possible at the same time is a prerequisite for the present invention, whereas the reading and writing of 2 are performed in units of the memory line 101. .

The relationship between the register file 103 and the data memory 102 is as follows.
01 is consistent with the registers (R0 to R15) or (R16 to R31) in the register file 103. However, in this embodiment, there are two depth registers DR0 and DR1, and DR0 is a register (R0 to R15) and DR1 is a register (R16 to R31).
Strictly speaking, one register file can hold half the data of two memory lines at a time. Which memory line matches is indicated in the depth register (DR0, DR1). In this embodiment, there are two depth registers, and DR0 indicates the corresponding memory line for the contents of R0 to R15 and DR1 indicates the corresponding memory line for the contents of R16 to R31. The specific memory line is selected by transferring the contents of the depth registers DR0 and DR1 to the corresponding column pointers 104 via the line 120. Information (for example, numerical information) for identifying the plurality of memory lines 101 is stored in the column pointer 104, and the numerical information is decoded by the column selection circuit 105 and becomes a memory line selection signal. Conversely, when data on the memory line 101 is transferred to the register file 103, the column pointer 1
04 is written to the depth register. That is, the depth registers DR0 and DR1 hold the identification information of the memory line that can be specified by the instruction word as the current register.

Next, prior to describing the vector processing operation of the present embodiment, an instruction format used in the present invention will be described with reference to FIG. There are two types of instruction formats, both of which have an instruction type 1101 indicating the type of instruction and a register specification unit OP0 (1102) for specifying a register. Since the instruction format 1 is mainly used for an operation instruction between registers, it has a register specification unit OP1 (1103) and OP2 (1104) for specifying a register in which an operation input value is stored. In the instruction format 1, the register specifying unit OP0
Is a register that stores the operation result. The instruction format 2 is a format for handling data embedded in an instruction word, that is, so-called immediate data. The register in which the immediate data is to be stored is specified by the register specifying unit OP0 (1102), and the immediate data itself is stored in the immediate data unit 1105. Is stored in As will be described later, this instruction format directly sets the value of each register, loads data of a location referred to as an immediate data in an external storage device as an address, and conversely, a register specifying unit OP0 (1102 ) Is used to store the contents of the register designated by ()) in the external storage device.

Next, an example of expression of an instruction word used in the information processing apparatus of the present invention as an assembler language will be described (FIG. 1).
2).

The instruction 1201 is an addition instruction, and the register 120 (R
0) stores the result of addition of the register 1 (R1) and the register 2 (R2). In the present invention, a vector operation can be performed as will be described later.
Just change to vector register names such as VR0 and VR1 like 1202.

The instruction 1202 is one instruction word, and R (i) = R (i) + R
The addition of (i + 15) is performed for all cases from i = 0 to i = 15. Here, R (i) means the register number i.

Next, an instruction 1203 is a numerical value moving instruction, which moves the contents of the register 1 (R1) to the register 0 (R0). FIG.
Using the instruction format 2 shown in (1), it is possible to directly handle numeric values.
You can enter 255. The above two examples of the MOVE instruction are the same as those of general information processing devices, but can operate the following registers unique to the information processing device of the present invention in the same format as these instructions.

An instruction 1205 is an instruction for setting a numerical value 8 in a vector length register (VL). As a result, a register to be subjected to a vector operation described later is determined.

An instruction 1206 is an instruction for setting a numerical value 128 in the depth register (DR0) shown in FIGS. As described above, since the depth register stores a numerical value indicating the position of the memory line 101, setting a specific numerical value in the depth register requires the value of a certain memory line in the data memory 102 to be stored in the register. This corresponds to the operation of reading. This operation will be described later with reference to FIG.

The next instruction 1207 is also an instruction for setting a numerical value 128 in the depth register. The instruction 1207 does not merely read data from the data memory as the instruction 1206, but also writes the value of the register file back to the memory line indicated by the depth register immediately before being changed, and then indicates by the new depth register. In the example, 128) Read the contents of the memory line into the register file. That is, this is an instruction for automatically exchanging the numerical value in the register file with the data memory 102. This operation will also be described later in detail with reference to FIG.

Finally, an instruction 1208 is an instruction to load data from the external storage device 113 to the data memory 102. In this embodiment, the column pointer 104 in FIG. 1 is not a register whose value can be directly changed by the user with an instruction word, but a register value (instruction 1208) designated by a register designation section of a load instruction.
In this case, the value of the register 0) or the depth register is used. In the instruction 1208, the data at the address 1420 in the external storage device is loaded into the memory line indicated by the register (R0). This operation will be described later with reference to FIG.

These instruction words are stored in the external storage device 113, read into the instruction buffer 106, decoded by the instruction decoder 115, and the register names included in the instruction words are temporarily stored in the register number pointer 107. You. Since the operation instruction usually takes the form of two inputs and one output, it must be possible to specify up to three registers.

The register name stored in the register number pointer 107 is decoded by the register selection circuit 108.
According to the decoding result, the register file outputs the contents of the register designated by the instruction word to the arithmetic circuit 109 or the load / store circuit 110.

In particular, when a vector register VR0 or VR1 to be described later is specified in the instruction word, consecutive registers are read by the number stored in the vector length register (VL) 111. That is, the register number pointer 107
Is automatically incremented by the number of times stored in the vector length register 111, and a plurality of registers are read by one instruction word. For example, when VR0 and VR1 are specified as operands of the addition instruction (add) and 4 is set in the vector length register 111 in advance,
Numerical values held in four sets of registers (R0, R16), (R1, R17), (R2, R18), and (R3, R19) are successively input to the arithmetic circuit 109 and an addition operation is performed. Writing to the register is executed in the same manner as reading.

In the present embodiment, as will be described later, since two register reading and one register writing to the entire register file can be executed at the same time, the same vector register is used to store the operation result in VR0 by the instruction to read VR0. Can be read and written. Also, during the above-described vector processing operation, the flow of data is limited between the register and the arithmetic unit, and there is no factor that limits the speed of other operations such as decoding of instructions. Therefore, it is possible to increase the operation clock by the time of reading / writing of the register and the critical operation speed of the arithmetic unit. Clock switching circuit 11 in the present embodiment
Reference numeral 2 denotes a switching circuit that supplies a clock having a shorter pitch to the arithmetic unit during the vector processing operation. As described above, since the clock speed can be increased to the limit of the arithmetic unit during vector processing, the clock switching circuit 112 switches the clock to a short pitch by executing the instruction specified by the vector register. Vector processing, that is, returning to the original clock by an instruction that specifies a register other than the vector register.

FIG. 2 summarizes the registers that can be updated by the instruction word of the information processing apparatus according to the present embodiment. General registers R0 to R31 for input / output of operation instructions
Is the vector register V for R0-R15 and R16-R31 respectively.
It can also be referred to as R0, VR1. The vector length register (VL) 111 described above exists independently of a general register,
It can be changed by a separate command. The depth registers DR0 and DR1 store numerical values indicating which columns of the data memory correspond to the registers R0 to R15 and R16 to R31, respectively.

<Register File> FIG. 3 shows the configuration of the register file 103. FIG. 3 illustrates the register R0 and the depth registers DR0 and DR1 in the register file, and omits the registers R1 to R15 and R16 to R31. The circuit diagram is for one bit of a register, and the same circuit having a data bit length per register (32 bits in this embodiment) exists in the depth direction of the drawing. MemRead (MemorRead) that instructs data reading from the data memory 102
y Read), MemWrite (Memory Write) for instructing data writing to the data memory 102, and ReadLatch 200 (Rea
RegBack (Register Back) for instructing data transfer between dLatch) and WriteLatch 201 (Write Latch) is generated by the control circuit 114 shown in FIG.

From the data memory 102 to the register file 103
MemRead becomes valid (High level) when reading data into the memory, and MemWrite becomes valid when writing data in the register file 103 to the data memory 102. In addition, ReadLatch200 and WriteLat200
The ch201 is formed as a circuit, and when the contents of the ReadLatch 200 are transferred to the WriteLatch 201, the RegBack becomes valid.

ReadReg1 (Read Register1), ReadReg2 (Read
Register 2) is a signal generated by the register selection circuit 108 to select a register holding data necessary for use in the arithmetic circuit 109 and to generate a data read path. In this embodiment, since there are a total of 32 registers R0 to R31, the register selection circuit 108 generates 32 ReadReg1 and ReadReg2 for each register. In FIG. 3, r indicates the register number as in ReadReg1 (r), and r corresponds to the register number, and ReadReg1 and ReadReg2 can select two registers at a time, forming a so-called two-port memory for reading. doing. WriteReg is a register selection signal related to register writing, and the correspondence with the register is the same as ReadReg1 and ReadReg2. The data of the register selected by ReadReg1 is read from ReadRegData1 (Read RegisterData1).
The data of the register selected by Reg2 (Read Register Data2) is output from ReadRegData2, and WriteRegData (Write
Register Data) is written to the register selected by WriteReg. Since there are 32 bits of data with respect to the selected register, in order to identify the bit, the bit is represented by i as in ReadRegData1 (i) in the figure.
MemLoad (Memory Load), MemLoadData (Memory Load Data)
Is connected to the load / store circuit 110. As described later, in the present embodiment, bidirectional data transfer between the external storage device 113 and the register file 103 is possible. When MemLoad is enabled, the contents of MemLoadDdata are written to WriteLatch201. The contents of MemLoadData are values read from the external storage device 113 by the load / store circuit 110. The data in the register file 103 is stored in the external storage device 113
When data is written to the external storage device 113, the data appearing in ReadRegData1 or ReadRegData2 by the register reading means is loaded by the load / store circuit 110.
Write to

The detailed operation function will be described.

In FIG. 3, MemBit is a data memory 102
This is a signal line for transmitting one bit of data read out of the device. This signal line connects the data memory 102 to the DRAM
And SRAM using SRAM, DRAM and SRAM
It is configured to be connected to a bit line for reading data from a memory cell constituting a RAM. That is, the configuration is such that each bit of each register of the register file corresponds to a memory cell that stores information in a bit unit in the data memory. In other words, the information processing apparatus includes a plurality of data cells for storing one data unit, a memory line including a plurality of the data cells arranged in a column, and a plurality of the memory lines configured in a row. , A register file including a plurality of registers including a plurality of bits, and a signal line connecting the plurality of data cells and the bits arranged in a row. The sense amplifier 202 has a function of amplifying and determining the MemBit electric signal to a logical high level or low level. ReadLatch
The loop formed by the inverter surrounded by 200 has a so-called latch function, and holds the output logic value of the sense amplifier 202. When WriteReg is valid,
It can be replaced by the value of WriteRegData.

The WriteLatch 201 is composed of an inverter connected in a loop like the ReadLatch 200, and holds the same contents as the ReadLatch 200 when RegBack is valid and MemLoadData when MemLoad is valid. That is, data to be written to the data memory 102 through MemBit (Memory Bit) is temporarily held.

FIG. 4 is a circuit diagram of the depth register. FIG. 4 shows the depth register DR1. DR0 can be realized by a similar configuration, but DR0 is different only in that signal lines such as ReadRegData, RegBack, MemLoad and the like are penetrated to the left and right, as can be seen from FIG. The contents of the depth register are basically the same as those of the register shown in FIG. 3, but the contents of the depth register are transferred to and from the column pointer 104, so that the RowBit signal 120 is used instead of the MemBit.

<Description of Operation of the Present Embodiment> Next, FIGS.
The operation of the information processing apparatus according to the present embodiment will be described with reference to FIG. As can be seen from the above description, the registers R0 to R0
Since R15 and DR0 have the same functions as R16 to R31 and DR1, respectively, the description will be given for R0 to R15 and DR0.

Next, an operation of exchanging the contents of the data memory 102 and the register file 103 like the instruction 1207 shown in FIG. 12 will be described. The present invention provides a DRAM without significantly changing the architecture seen by the user such as the number of registers.
The purpose is to introduce a large-capacity memory such as a memory and an SRAM.
For this purpose, it is convenient that the contents of another register can be physically read and written only by changing the value of a certain control register as in the conventional register window. However,
In order to be able to simultaneously read or write two data for all registers like a register window, an enormous memory circuit having two or more ports is required. Therefore, in the present invention, ordinary DRAM, S
A large-capacity memory of one port similar to the RAM is provided, and a normal register file is connected to the position of the data port, thereby achieving both large-capacity and multi-port characteristics. However, just like updating the control window and the register window, it is necessary to update the contents of the register and the large-capacity memory (this implementation) in order to make it appear as if a certain part of the large-capacity memory functions as a register. In the embodiment, it is preferable that the contents of the data memory 102) are automatically replaced with the update of the control register.

FIG. 5 shows registers R0 to R15 and memory line 1.
It is a flowchart about the replacement operation of 01. This operation is a hardware operation started by an instruction to update the depth register such as MOVE DR0,128. First, if the contents of DR0 are to be changed, DR0
RegBack is enabled before R is actually changed, and R
The contents of eadLatch are copied to WriteLatch (500). Next, the contents of the new DR0 to be changed are
Is set to (501). As a result, a memory line in the data memory is selected. Subsequently, by enabling MemRead, the contents of the memory line specified by the column pointer 104 are read into the ReadLatch (50
2). At this time, the contents of the column pointer 104 are the ReadLatch of DR0.
Is stored in With the above operation, the contents of the new register file are set. In this replacement operation, WriteL
Writing back the contents of the atch to the memory line is also executed as a series of operations. That is, the value stored in WriteLatch of DR0 is set in column pointer 104 (503).
This specifies to which memory line the old register file values should be written back. Finally
MemWrite becomes valid, and the contents of WriteLatch of all registers are stored in the memory line (504).

This register exchange operation is performed by, for example, MOVE
DR0,255 (insert a value of 255 into DR0) corresponds to the executed instruction. In this case, 255 of immediate data is data memory 1.
It corresponds to the address in the column direction of 02 and the depth register
Updating DR0 means allocating the in-use register to a physically different memory, as when updating the base register in a prior art register window. That is, registers can be totally replaced by one instruction operation, and subroutine jumps, returns, and switching of processes and tasks can be executed at high speed. In addition, in a vector operation described later, an operation having a substantially large number of vector registers can be realized with a small number of logical vector registers.

FIG. 6 omits the operation of writing the old register contents back to the memory line in the register replacement operation shown in FIG. For example, MOVE
This instruction is written as DR0, (255). When this instruction is executed, the contents of the memory line specified by the numerical value 255 are read into the register without saving the old register contents. This is an operation corresponding to data loading from an external memory in a general information processing apparatus. In an information processing device in which a data memory is formed on the same substrate, high-speed data transfer is possible. Therefore, this function is used as a realization method that enables memory access as an operation related to registers instead of positioning the data memory as an external memory. Is positioned.

FIG. 7 is a flowchart showing an operation of reading data in the external storage device 113 into the data memory, that is, an operation of a function of loading data into the data memory 102. First, the data read from the external storage device 113 determines MemLoadData in FIG. Next, the memory line specified by the load instruction is set to the column pointer 104
(701). When MemLoad is enabled, the contents of MemLoadData are read into WriteLatch 201 (702). Finally MemWri
By enabling te, the contents of WriteLatch are stored in the memory line.

In the information processing apparatus of the present embodiment, it is a precondition that data can be loaded into the register and data can be stored from the register as data transfer means between the register and the external storage device. The load function is additional.

FIGS. 8 and 9 are flowcharts showing the basic operation of reading and writing data from the register file. The register number r to be read is the register selection circuit 1.
Decoded at 08 and connected to any register
ReadReg is enabled. Read data is ReadRegDa
output to ta and used by the arithmetic circuit 109. Similarly, at the time of register writing, WriteReg of the corresponding register becomes valid based on the decoding result by the register selection circuit 108, and the contents of WriteRegData are stored in the ReadLatch 200.

FIG. 10 is a flowchart for explaining a vector operation which is a characteristic operation of the present invention. First,
The vector operation shown here is an operation when a vector register name of VR0 or VR1 is specified in the operation instruction word, as described later. Prior to that, MOVE VL, 8 (stores a numerical value 8 in the vector length register) A setting operation of the vector length register 111 is necessary (1000).
In the operation instruction in which the vector register is specified, first, numerical values corresponding to R0 and R16 are stored in the three register number pointers 107 (1001). Two correspond to the first element of the input vector register, and the other corresponds to the first element of the write destination. From this state, the subsequent processing is repeated until the value in the vector length register becomes 0 (1005). At the beginning of the repetitive operation, data is read from the two input registers pointed to by the register number pointers by the register read operation described with reference to FIG.
002). The operation result is stored by the register write operation shown in FIG. 9 based on the register number pointer indicating the output register (1003). At this time, it seems at first glance that the reading and writing of the register conflict with each other. However, after reading the register of the register number r, the writing operation to the same number is started, so that there is no collision. Finally, the vector length register is subtracted, and the register number pointer is incremented by 1 as a register number.

[0042]

According to the present invention, a register set in a register file can be used as a vector register, and a vector operation suitable for code processing and signal processing frequently occurring in multimedia processing can be executed. Further, the large-capacity memory is positioned as a data memory, and further provided in an information processing device (CPU). Since the memory line in the data memory specified by the depth register can be replaced with a register file, a large number of registers and vector registers can be implemented with practically no change in the register configuration seen from the user.

[Brief description of the drawings]

FIG. 1 is a configuration example of an information processing device (CPU) that realizes the present invention.

FIG. 2 is a register that can be updated by an instruction word.

FIG. 3 is a register circuit diagram according to the embodiment of the present invention.

FIG. 4 is a circuit diagram of a depth register according to the embodiment of the present invention.

FIG. 5 is a flowchart illustrating a register swap operation according to the embodiment of the present invention.

FIG. 6 is a flowchart illustrating an operation of reading a register from a data memory.

FIG. 7 is a flowchart illustrating a loading operation from a memory to a data memory.

FIG. 8 is a flowchart illustrating a register read operation from a register to an arithmetic unit.

FIG. 9 is a flowchart illustrating a register write operation from an arithmetic unit to a register.

FIG. 10 is a flowchart illustrating a vector operation.

FIG. 11 is a diagram illustrating a format of a command word.

FIG. 12 is an assembler language example of a command word.

[Description of Signs] 100: data cell, 101: memory line, 102: data memory, 103: register file, 104: column pointer, 105:
Column selection circuit, 106: instruction buffer, 107: register number pointer, 108: register selection circuit, 109: arithmetic circuit, 110
... Load / store circuit, 111 ... Vector length register, 112
... Clock switching circuit, 113 ... External storage device, 114 ... Control circuit, 115 ... Instruction decoder, 120 ... RowBit.

Claims (6)

[Claims] 1. An information processing apparatus for designating a register for storing an input value and an output value of an operation by a command word, comprising: a data cell for storing one data unit; and a memory comprising data cells arranged in columns. Line, a data memory composed of a plurality of memory lines, a register file including a plurality of registers that can be specified by an instruction word, and a depth register storing a numerical value corresponding to the memory line. When updated,
An information processing apparatus, wherein a register file is replaced with information of a memory line associated with a depth register. 2. An information processing apparatus for designating a register for storing an input value and an output value of an operation by a command word, wherein the memory comprises a data cell for storing one data unit and a data cell arranged in a column. A register file containing a plurality of registers that can be specified by a command word, and a depth register storing a numerical value corresponding to the memory line. The depth register is a register file. And immediately before the depth register is updated,
Information storing the contents of the register file in the memory line indicated by the depth register, updating the depth register with a new value, and then storing the memory line indicated by the depth register in the register file Processing equipment. 3. An information processing apparatus for designating a register for storing an input value and an output value of an operation by a command word, wherein the memory comprises a data cell for storing one data unit and a data cell arranged in a column. A line, a data memory composed of a plurality of memory lines, a register file including a plurality of registers that can be specified by an instruction word, and a depth register storing a numerical value corresponding to the memory line,
An operation circuit for performing the same operation on a plurality of registers in the register file by one instruction word, and when the depth register is updated, a memory line indicated by the depth register is stored in the register file. An information processing apparatus characterized by the following. 4. A data memory comprising a plurality of data cells for storing one data unit, a memory line comprising a plurality of said data cells arranged in a column, and a data memory comprising a plurality of said memory lines constituted in a row. An information processing device comprising: a register file including a plurality of registers each including a plurality of bits; and a signal line connecting the plurality of data cells and the bits arranged in a row. 5. A decoder for interpreting the instruction word instructing to write the contents of a memory line specified by the instruction word to the register file, and specifying a memory line to be written to the register file according to the interpretation result. The information processing apparatus according to claim 4, further comprising a circuit. 6. The information processing apparatus according to claim 4, wherein said register file has means connected to said signal line for holding data to be written to a memory line and data read from said memory line, respectively.