JPH0635844A - Direct memory access device - Google Patents

Abstract

PURPOSE:To attain the high speed working of a direct memory access device by performing the transfer of data with sorting through the hardware. CONSTITUTION:Key word registers 1a and 1b store two different types of data given from a source memory, and a comparator 3 compares the contents of both registers 1a and 1b with each other. Then, the selectors SL1 and SL2 output the data stored in one of both registers 1a and 1b based on the comparison result of the comparator 3. Furthermore, the AND gates AG1 and AG2 update the contents of both registers 1a and 1b based on the comparison result of the comparator 3.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a direct memory access device, and more particularly to an input / output device in an information processing device,
The present invention relates to a direct memory access device that transfers data between main storage devices.

[0002]

2. Description of the Related Art A direct memory access device increases the data transfer rate when input / output devices such as magnetic disk devices, communication devices, and display devices are connected to a common data transfer path (hereinafter referred to as a system bus). , A device for performing high-speed data transfer between the input / output device and the main storage device instead of the central processing unit (hereinafter referred to as CPU).

Conventionally, direct memory access devices have been
It is mainly used for data transfer, but recently it has been announced that it has a search function (see i82258 Cousers Manual). This search function is a function that becomes necessary for database operation. The sorting function is also an important function in database operations. Conventionally, this sort function has been realized by software as shown in FIG.

[0004]

In the above-mentioned conventional direct memory access device, the sorting function is realized by software by the CPU. Therefore, in order to execute this sorting function, instruction fetch, decoding, and data reading are executed. There is a drawback that it takes time for writing.

It is an object of the present invention to provide a direct memory access device capable of performing DMA data transfer with sort in a short time.

[0006]

A direct memory access device of the present invention includes first and second registers which respectively store two data from a source memory in a corresponding manner.
A comparator for comparing the data stored in the first and second registers and outputting a comparison result, and a comparator for storing the data stored in the first and second registers according to the comparison result by the comparator. A selection output unit that selects one of the two and sends it to a destination memory; a stored data updating unit that updates the data stored in the first and second registers according to the comparison result by the comparator; And an address designation unit for designating addresses of the source memory and the destination memory.

[0007]

Embodiments of the present invention will now be described with reference to the drawings.

FIGS. 1 and 2 are a circuit diagram showing an embodiment of the present invention and a data format of data handled by this embodiment and a memory map of a source memory of its storage location, respectively.

The format of the data to be sorted at the same time as the transfer is such that one data field DF of the lower 32 bits and one keyword field KF of the upper 32 bits make a pair to form one unit of data. It is stored in one source address. The sorting process is performed by the information in this keyword field KF.

In this embodiment, a first keyword for storing a keyword field KF and a data field DF of two data from the source memory (100) transmitted to the address input terminal AI and the data input terminal DI respectively correspondingly. The register 1a, the data register 2a, the second keyword register 1b, and the data register 2b are compared with the data (A and B, respectively) stored in the first and second keyword registers 1a and 1b, and A ≧ When it is B, the comparator 3 which outputs a comparison result of "1", the comparison result by the comparator 3 and the second last signal SC
A first keyword register 1a, a data register 2a, and a second keyword register 1b in accordance with D / LST,
EXCLUSIVE OR of the selection output section which selects one of the data registers 2b and sends it to the destination memory from the address output terminal AO and the data output terminal DO.
The gate EG1, the selectors SL1, SL2 and the three-state buffers TSB1 and TSB2, and the first result depending on the comparison result by the comparator 3 and the second / last signal SCD / LST.
And an inverter IV1 and an AND gate AG of the stored data update unit for updating the data stored in the second keyword registers 1a and 1b and the data registers 2a and 2b.
1, AG2, a sort address on the sort memory side of data to be subjected to data transfer and sort processing, a destination address of the destination memory, and a source address incrementer 4 for sending out from the address output terminal AO. Interlimator 5 and 3-state buffers TSB3, TSB4
And an order control circuit 6 and AND gates AG3 to AG5 that control the operations of the above-described units according to the clock signal CK.
It is configured to have and.

Next, the operation of this embodiment will be described. FIG. 3 is a timing chart of signals of respective parts for explaining the operation of this embodiment.

In this embodiment, data is transferred between memories in two bus cycles (4 clock cycles).

First, the head source address As1 and the destination address Ad1 to be sorted and transferred are initialized to the source address incrementer 4 and the destination address incrementer 5, respectively. The keyword register 1b is reset to "0" before starting the data transfer with sorting. As a result, the comparator 3
Will output the comparison result of "1". The comparator 3 outputs a comparison result of "1" when A≥B and "0" otherwise. In FIG. 3, the number of data to be sorted is “5”.

When data transfer with sorting is started, the sequence control circuit 6 reads the read signal Reod, the write signal WRITE, and the second last signal SCD.L as shown in FIG.
ST, 1 clock diagram bus cycle signal T1, 2 clock diagram bus cycle signal T2 is output. The second / last signal SCD / LST is a signal which becomes active in the second bus cycle and the last bus cycle. The first clock bus cycle signal T1 is a signal indicating that it is the first clock of the bus cycle, and the second clock bus cycle signal T2 is a signal indicating that it is the second clock of the bus cycle.

In the first bus cycle, the source address As1 is sent to the address output terminal AO in the T1 active state.
Output to. SCD • LST is initially “0”, the output of the comparator 3 is “1”, and Reod = “1”. In the T2 active state, the first keyword field is read from the address input terminal AI and the keyword register 1 is read.
Store in a. At the same time, the first data field from the data input terminal DI is read and stored in the data register 2a.

In the second bus cycle, the source address As2 incremented by the source address incrementer 4 in the T1 active state (hereinafter referred to as T1 state) is output to the address output terminal AO. SCD
Since LST is "1" at this time and the output of the comparator 3 is also "1", the EXCLUSIVE OR gate EG
The output GE of 1 becomes "0". Therefore, in the second bus cycle, GE = "0" and Reod = "1", and T2
In the active state (hereinafter referred to as T2 state), the second keyword field from the address input terminal AI is stored in the read address register 1b. At the same time, the second data from the data input terminal DI is read and stored in the data register 2b. In the third bus cycle, the values (A, B) of the keyword registers 1a and 1b are compared by the comparator 3, and when A ≧ B, a comparison result of “1” is output, and when A <B, “1” is output. The comparison result of 0 "is output.

SCD.L after the third bus cycle
Since ST is "0", the GE 12 outputs the comparison result as it is. "1" in this bus cycle
And In the T1 state of the third bus cycle, first, the destination address Ad1 is set to the address output terminal A.
Output to O. In the T2 state of the third bus cycle, since GE = "1", the selector SL1 selects the output of the keyword register 1b and the address output terminal AO.
Is output to. At the same time, the output of the data register 2b is selected by the selector SL2 and output to the data output terminal DO. Then, the destination address incrementer 5 increments the destination address to Ad2.

In the fourth bus cycle, the source address As3 incremented by the source address incrementer 4 in the T1 state is output to the address output terminal AO. In the T2 state, if the GE value determined in the immediately preceding third bus cycle is "1", the address input terminal A
The third keyword field from I is read and stored in the keyword register 1a. At the same time, the third data from the data input terminal DI is read and stored in the data register 2a.

The fifth, seventh and ninth bus cycles are the same as the third bus cycle. The sixth and eighth bus cycles are the same as the fourth bus cycle.

In the last bus cycle (10th in this embodiment), the destination address Ad5 incremented by the destination address incrementer 5 is output in the T1 state. In the last bus cycle, the SCD.LST signal becomes "1". Therefore E
The XCLUSIVE OR gate EG1 outputs a comparison result negation signal. For this reason, the remaining register that is not output in the previous bus cycle is selected and output.
If GE = "1", the value of the keyword register 1a is output to the address output terminal AO, and the value of the data register 2a is output to the data output terminal DO. If GE = "0", the value of the keyword register 1b and the value of the data register 2b are output.

Thus, the data transfer with sorting is performed, and if the number of records of the information to be sorted is n, the data transfer with sorting is repeated n times to complete the sorting.

[0022]

As described above, according to the present invention, since the hardware for realizing the sorting function is provided inside, fetching and decoding of instructions are eliminated as compared with the conventional data transfer with sort by software by the CPU. Therefore, there is an effect that the data transfer with sorting can be speeded up.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention.

FIG. 2 is a memory map of a data format and its storage memory applied to the embodiment shown in FIG.

FIG. 3 is a timing chart of signals of respective parts for explaining the operation of the embodiment shown in FIG.

FIG. 4 is a diagram showing a program for realizing sort processing of data transferred by a conventional direct memory access device.

[Description of Reference Signs] 1a, 1b Keyword Register 2a, 2b Data Register 3 Comparator 4 Source Address Incrementer 5 Destination Address Incrementer 6 Sequence Control Circuit 100 Source Memory AG1 to AG5 AND Gate EG1 EXCLUSIVE OR Gate IV1 Inverter SL1, SE2 Selector TSB1 to TSB2 32 Tate buffer

Claims (1)

[Claims] 1. A first register and a second register, which respectively store two data from a source memory, respectively, are compared with data stored in the first and second registers, and a comparison result is output. A comparator, a selection output section for selecting one of the data stored in the first and second registers according to a comparison result by the comparator and transmitting the selected data to the destination memory, and a comparison by the comparator A storage data updating unit that updates data stored in the first and second registers according to a result; and an addressing unit that specifies addresses of the source memory and the destination memory. Direct memory access device.