JPH0358240A - Register access recording circuit - Google Patents

Abstract

PURPOSE:To check an access pattern to each control register by providing an OR circuit of a data write clock signal, and a memory brought to address selection by a code constituted of a data signal and a select signal, and storing an access of every data pattern in the memory. CONSTITUTION:The subject circuit is provided with an OR circuit for calculating OR of data write clock signals 021 - 051 supplied to plural control registers 20 - 50, and a memory 10 to which an address selection is executed by a code constituted of a data signal inputted to plural control registers and a selector signal for selecting the control register. In this state, an access of every data pattern to each control register 20 - 50 is stored in the memory 10. In such a way, by what kind of data pattern the access is executed to each control register, or what kind of pattern the data pattern which is not brought to access yet is can be checked.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an information processing device, and more particularly to a register access recording circuit for recording register accesses.

[Conventional technology]

Conventionally, access records of registers in this type of information processing device are often performed using address trace memory, etc.
It was possible to know which register was accessed.

[Problem to be solved by the invention]

In the above-mentioned conventional register access recording circuit, when investigating what data has been written to which register, a certain range of data can be checked by stopping the operating device and tracing the address of its firmware. Although it is possible to know only one access, it has the disadvantage that it is not possible to know what data patterns are used to access all registers.

[Means to solve the problem]

The register access recording circuit of the present invention comprises <A) an OR circuit that calculates the OR of data write clock signals supplied to a plurality of control registers whose accesses are to be recorded; A data bus for transmitting input data signals and a data bus for transmitting select signals for selecting the plurality of control registers are connected to an address/data input terminal, and the output signal of the OR circuit is connected to a clock input terminal. has memory supplied to .

〔Example〕

Next, the present invention will be explained with reference to the drawings. FIG. 1 is a block diagram of one embodiment of the present invention.

In FIG. 1, 10 is a memory, 20 to 50 are control registers, 001 is a data bus, 002 is a data line for the memory 10, 021, 031, 041, 051 is a data write clock for control registers 20 to 50, and 011 is a data line for the memory 10. is the data write clock of the memory 10, which is the logical sum of the data write clocks 021 to 051.

003 is a 2-bit I select signal representing the control registers 20 to 50 in code.

The operation when writing data to the control register 20 will be described below.

At this time, control registers 20 to 50 and select signal 00
3 is assumed to have a relationship as shown in FIG. Also, a case will be explained in which each of the control registers 20 to 50 and the data bus 001 has 4 bits.

Bit bang 1010.2 against control register 20
is written as data, data bus 001
Data 1 0 1 0 +2+ is placed on the control register 20, and data 1010.2 is written into the control register 20 by the write clock 021. The select signal 003 at this time is O O (21) from the relationship shown in FIG.
Since 01 is 1 0 1 0 + 2, the address of the memory 10 is set to 001010,2, and is written to the memory 10 from the data line 002 as a logic value "1" by the memory data write clock 011.

Similar operations occur when data is written to other control registers.

In this way, an elliptical circuit is used to calculate the logical sum of the data write clock signals supplied to multiple control registers, and the select signal for selecting the data signal and control register input to the multiple control registers. By providing a memory in which address selection is performed by a certain code, and storing accesses for each data pattern to each control register in the memory, it is possible to determine which data pattern is used to access each control register. However, it is also possible to check what kind of data buttons have not been accessed yet.

〔Effect of the invention〕

As explained above, the present invention includes an OR circuit for calculating the logical sum of data write clock signals supplied to a plurality of control registers, and a logical sum circuit for calculating a logical sum of data write clock signals supplied to a plurality of control registers, and a circuit for selecting a data signal and a control register to be input to a plurality of control registers. By providing a memory in which address selection is performed by a code consisting of a select signal and a code, and storing accesses for each data pattern to each control register in the memory, it is possible to determine which data pattern is used to access each control register. This has the effect of being able to check whether a data button has been accessed, or if there is a data button that has not been accessed yet.

[Brief explanation of drawings]

FIG. 1 is a block diagram of the present invention, and FIG. 2 is an explanatory diagram showing the correspondence between control registers and select signals. 10...Memory, 20,30,40.50...Control register, 001...Data bus, 002...Data line, 003...Select signal, O'll...
Memory data write clock, 021,031.041
051...Data write clock.

Claims (1)

[Scope of Claims] (A) an OR circuit that calculates the OR of data write clock signals supplied to a plurality of control registers whose accesses are to be recorded; A data bus for transmitting data signals and a data bus for transmitting select signals for selecting the plurality of control registers are connected to an address data input terminal, and an output signal of the OR circuit is supplied to a clock input terminal. A register access recording circuit comprising a memory.