JPS6411977B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to information processing devices, and particularly to improvements in performance measurement methods for hardware characteristics and software characteristics.

(Prior art) Conventionally, in information processing devices that have a built-in performance measurement function for hardware and software characteristics, a system has been adopted in which counters are provided in accordance with the number of items to be measured, with a bit width corresponding to the required accuracy. Ta. However, in order to maintain measurement accuracy, one counter requires a large bit width. For example, if the average instruction execution time is 20 ns, and we are trying to measure the number of instructions executed per minute in a certain program, 50 million instructions are executed per second, so 3 billion instructions are executed per minute. sell. In order to be able to measure this, a 32-bit counter is required, and as the performance of the information processing device becomes higher, the increase in the amount of metal becomes significantly larger.

(Objective of the Invention) An object of the present invention is to solve the above-mentioned problems by using a built-in hardware tracer, which has a function to trace the operation of an information processing device, not as a trace function but as a counter function when measuring performance. However, it is an object of the present invention to provide an information processing device in which the increase in bit width of a performance measurement counter is reduced.

(Structure of the Invention) In order to achieve the above object, an information processing apparatus according to the present invention includes a built-in trace memory for tracing the operation of the information processing apparatus, and the information processing apparatus selects the source of the signal under measurement based on measurement control information. a plurality of counters each counting the signals under test selected by the first selection means; an overflow detection circuit detecting an overflow of each of the plurality of counters; a second selection means for switching from the trace data to the overflow detection circuit output based on control information; and when the overflow detection circuit detects an overflow in one or more counters among the plurality of counters before and after, the overflow is detected at a specified address; The trace memory for setting a bit, and the measurement data collection means for reading the counter values of the plurality of counters and the contents of the trace memory by detecting the storage of the last word in the trace memory, and collecting measurement results. ing.

(Example) Next, the present invention will be described in detail with reference to the drawings.

FIG. 1 shows an embodiment of an information processing apparatus according to the present invention. In FIG. 1, 1 is a performance measurement control unit, 2 is a signal source to be measured, 3 is a measurement mode register, 4 is a signal to be measured register, 5, 8, and 13 are first to third selection circuits, and 6 is a signal source to be measured. counter group,
7 is an overflow detection circuit, 9 is a trace memory write flip-flop, 10 is an overflow register, 11 is a trace signal source, 12 is a trace data register, 14 is an address counter, 15
1 is a trace memory, 16 is a trace memory final word storage detection circuit, and 17 is a measurement data collection control section.

In FIG. 1, measurement control information specified by the performance measurement control unit 1 is held in the mode register 3, and the held measurement control information selects the signal under test register 4 and transfers the trace memory 15 to the performance measurement memory. It is declared to be used as . The signal under test from the signal source 2 under test is
It is temporarily held in the signal under test register 4, classified into each measurement item group, and connected to the signal lines 105,
The signals are input to the first selection circuit 5 from 106 and 107. In the first selection circuit 5, signal lines 105, 106, 107 are
Select one of them and input it onto the signal line 108 in one-to-one correspondence with the signal group to be measured. The number of times the signal under test is in the ON state is counted using the machine clock of the information processing device as a sampling timing, and the contents of the counter group 6 are updated. The overflow detection circuit 7 is connected to the counter group 6,
Next, when the signal under test turns ON, a state in which the counter overflows, that is, a state in which the logic value of all bits of the contents of the counter is generally 1 is detected. An overflow detection circuit 7 is configured for each counter in the counter group 6, and its output is sent out from a signal line 110 and held in an overflow register 10. When overflow detection circuit 7 detects an overflow condition in any counter, trace memory write flip-flop 9 is set to instruct writing of overflow data to trace memory 15. Trace memory write flip-flop 9
At the same timing as when the counter group 6 is set, the overflow detection information of the counter group 6 is sent from the overflow detection circuit 7 to the overflow register 10, and is set in the overflow register 10. Therefore, the third selection circuit 13 determines whether the data in the overflow register 10 or the data in the trace data register 12 for holding the trace signal source 11 is sent from the mode register 3 via the signal line 103. Select by measurement selection mode signal. The output is stored in the trace memory 15 at the address specified by the address counter 14, and the address of the address counter 14 is updated according to an instruction from the signal line 112.

The contents of the address counter 14 are updated every time an overflow is detected in the counter group 6, and when storage into all words of the trace memory 15 is completed, the trace memory final word storage detection circuit 16
The end of the storage is detected, and the detection is reported from the signal line 115 to the counter group 6, and updating of the counter is suppressed. Further, the measurement data collection control unit 17 is instructed to collect measurement data. Upon receiving the above instruction, the measurement data collection control section 17 sends a selection signal to the second selection circuit 8 via the signal line 102. Therefore, the second line connected to the counter output line 109 from the counter group 6
A selection circuit 8 selects a counter to be collected. As a result, the second selection circuit 8 reads the counter value from the signal line 114. At the same time, the address counter 14 is initialized by the signal line 104 (generally address 0), and the trace memory 14 is updated while the contents of the address counter 14 are updated.
5 are read from signal line 113. The sum of overflow bits for all words read from the trace memory 15 is the number of overflows of the corresponding counter, and the measurement result can be obtained as follows. For example, if the counter is made up of 4 bits and the trace memory 15 is made up of 256 words, overflows of this counter can be stored in the trace memory 15 up to 256 times. Therefore,
The measurement result at this time can be calculated by [256×2〓]+counter value. At this time, there appear to be 12 bits in the counter.

(Effects of the Invention) As explained above, the present invention improves the accuracy of the counter without increasing the amount of hardware by using the built-in trace memory instead of the counter without increasing the bit width of the counter group. It has the effect of being able to

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of a portion of an information processing apparatus according to the present invention. 1... Performance measurement control unit, 2, 11... Signal source,
3, 4, 10, 12... register, 5, 8, 13
...selection circuit, 6 ... counter group, 7 ... overflow detection circuit, 9 ... flip-flop, 14
. . . address counter, 15 . . . trace memory, 16 . . . trace memory final word storage detection circuit, 17 . . . measurement data collection control section.

Claims (1)

[Claims] 1. In an information processing device having a built-in trace memory for tracing its own operation, a first selection means selectively connects to a signal under test source of a signal under test based on measurement control information; a plurality of counters each counting a selected signal under test; an overflow detection circuit detecting an overflow of each of the plurality of counters; and a second selection means switching from trace data to the output of the overflow detection circuit based on the measurement control information. and the trace memory which sets an overflow detection bit at a designated address when the overflow detection circuit detects an overflow in one or more counters among the plurality of counters before and after, and detects storage of the last word of the trace memory. An information processing apparatus comprising: a measurement data collection means for reading counter values of the plurality of counters and contents of the trace memory, and collecting measurement results.