JPS6010357A - Data collecting device for measuring performance of computer - Google Patents

Abstract

PURPOSE:To attain collection of lots of phenomena with simple circuit constitution. CONSTITUTION:A data collecting device for measuring the performance of a computer has an RAM5 as a storage means storing sequentially the signal state of each part of the computer, an address counter being a means storing the addresses of the RAM5 updating the addresses, and a detecting means 7 detecting the end of storage to all addresses of the RAM5 and generating an interruption signal to a micro program. Further, the micro program 8 controls, e.g., a device to be measured normally and consists of a collecting means 9 reading and accumulating information stored in the RAM5 in the ascending order of addresses at any time and an initial set means 10 keeping an address counter 6 to the initial state after the logging is finished.

Description

Detailed Description of the Invention (1) Technical Field of the Invention The present invention relates to a data aggregation device for measuring the performance of a computer, and in particular to a data aggregation device for measuring the performance of a computer, and in particular to a data aggregation device for a computer that is capable of aggregating a large amount of data with a compact circuit configuration. The present invention relates to a data aggregation device for performance measurement.

(2) Background of the technology Performance analyzers are used to measure the performance of computers. This device measures various items and phenomena that determine the performance of a computer, such as the number of times a signal in the computer is activated and the amount of time it is active, and aggregates this data with a data aggregation device. was used to measure computer performance.

(3) Prior Art and Problems FIG. 1 is a diagram showing a conventional data aggregation device for measuring computer performance. A counter 3 consisting of a storage section 1 and an incrementer 2 connected to the storage section 1 is connected to each measurement point of the computer 4, and when counting the number of times, each time a predetermined phenomenon is input. Callan 1- of storage unit 1
The totalization is carried out by reading the data, incrementing the data by 1 using the incrementer 2, and writing the result into the storage unit 1. When measuring the dead time, a predetermined time is ticked by a machine clock, and the number of occurrences of a predetermined phenomenon is written in the storage unit 1 based on whether a predetermined phenomenon occurs at the ticked time.

However, in such a computer performance measurement aggregation device, one 7J is calculated for one measurement point.
Since the counter 3 is required, many counters 3 are required for measurement at a large number of locations, which is normally required, and there is a problem that a complicated circuit is required and the cost is increased.

(4) Purpose of the Invention The present invention has been made by focusing on such conventional problems, and its purpose is to provide a simple circuit configuration and low cost.
The object of the present invention is to solve the above problems by providing a data aggregation device for computer performance measurement that can perform aggregation for a large number of phenomena.

(5) Structure of the Invention In order to achieve the above object, the present invention provides a storage means for sequentially storing the signal states of each part of the computer, and means for holding the address of the storage means and updating this address. and a detection means for detecting that storage has been completed in all addresses of the storage means and generating an interrupt signal to the microprogram, and a totalizing means and address for controlling the contents of the storage means by the microprogram. The gist of the present invention is to configure an initial setting means for initializing the holding means.

(6) Embodiment of the Invention FIG. 2 is a diagram showing a computer performance measurement aggregation device according to an embodiment of the invention.

In this embodiment, the data aggregation device for measuring the performance of a computer includes a RAM (random access memory) 5 as a storage means for sequentially storing the signal states of each part of the computer, and means for holding the address of this RAM 5 and updating this address. address counter 6 and this RAM
The microprogram has detection means 7 for detecting that storage has been completed at all addresses 5 and generating an interrupt signal to the microprogram. In addition, the microprogram 8 normally controls, for example, a device under test, but the microprogram 8 internally stores the information stored in the RAM 5 at any time in response to an interrupt signal generated by the detection means 7. It consists of a totalizing means 9 that reads and totals addresses in ascending order of addresses, and an initial setting means 10 that maintains the address counter 6 in its initial state after completing this totaling.

Next, the operation of the computer performance measurement data aggregation device according to this embodiment will be explained.

When this device starts operating, information 11, 11, etc. on the signal status of each internal part of the computer is stored in the memory of the pin i corresponding to each measurement point of the first address held by the address counter 6 of the RAM 5. will be written to. Then the machine clock is set for a predetermined time (e.g. 1 m3
ec (hereinafter referred to as a clock), the address counter 6 updates the address in the RAM one by one, and the signal state of each part of the computer at each clock is determined by a predetermined bit of the address held by the address counter 6. write to the memory of. This operation
This is done every time the machine clock ticks, and the RA
The process continues until the final address of IV+5.

When the detection means 7 detects that the address counter 6 holds the last address in the RAM 5, it generates an interrupt signal to the microprogram 8. When the microprogram 8 receives an interrupt signal from the detector 7,
RAM 5 according to the procedure set in micro program 8.
The content written in is read out sequentially from the /h address, the data of each part of the computer being measured is totaled, and the data is written to another storage device 12. Reading from each address of the RAM 5 does not necessarily have to be carried out continuously, but the collection s1 means 9 operates according to the procedure set in the microprogram 8.

When this counting means 9 has finished reading the data written to all addresses of the RAM 5, the initial setting means 1o configured in the microprogram for resetting the address counter 6 resets Mla of the address counter 6 to the first one. Set to street address.

Then, the signal status of each internal part of the computer is written into the RAM 5 again, and the same operation as described above is performed.
The data is old up to the final address of AM5, the detection means 7 operates in the same way as before, and the microprogram 8
generates an interrupt signal. The microprogram 8 performs the same operation as the previous time, writes the total data into the other storage device 12 mentioned above, and initializes the address counter 6.

By repeating this operation a predetermined number of times, necessary data for measuring computer performance can be compiled.

For example, to calculate the amount of time that a specific part was in the on state, it is sufficient to multiply the number of times the collected data was in the on state by the clock length. In addition, in order to total the number of times the light was in the on state, it is sufficient to measure the number of times the brightness changed from the off state to the on state in the collected data η1.

(7) As described in detail, according to the present invention, a simple circuit includes a storage means, a means for holding and updating the address of the storage means, and a detection means for generating an interrupt signal to a microprogram. Since the data aggregation device for computer performance measurement is constructed by processing in a microprogram, it is possible to use memory that can be highly integrated, and it does not require a large number of counters, so the circuit can be simplified and made smaller. Moreover, it is possible to perform aggregation for a large number of phenomena with a compact configuration, and it is possible to obtain various effects such as being able to significantly reduce costs.

[Brief explanation of drawings]

FIG. 1 is a diagram showing a conventional data aggregation device for measuring computer performance, and FIG. 2 is a diagram showing a data aggregation device for measuring computer performance according to an embodiment of the present invention. 5...Storage means (RAM) 6...Address holding and updating means (address counter) 7...Detection means 8...Micro program 9...Tallying means 10...Initial setting means Patent applicant Fujitsu Limited 1st RGJ

Claims (1)

[Claims] storage means for sequentially storing the signal states of each part of the computer; means for holding and updating addresses to be stored in the storage means; detecting that storage has been completed in all addresses in the storage means; A computer comprising: a detection means for generating an interrupt signal in a microprogram; and a totalization means for totalizing the contents of the storage means by the microprogram; and an initialization means for initializing the address holding means. Data aggregation device for performance measurement.