JPH04232547A - Data processing circuit - Google Patents

Abstract

PURPOSE:To obtain a data processing circuit which surely synchronizes a write/ read signal inputted to a memory and an address signal inputted to the memory with each other. CONSTITUTION:An actual write signal the inverse of MCW of a memory A is generated by a flip flop 8 and gates 9 and 17, and a write reference signal the inverse of W, a task signal TSK, and the output of the gate 9 are inputted to the gate 17 to generate the write signal the inverse of MCW. A count-down enable signal CDE of an address down counter 10 is generated by a flip flop 11 and an AND gate 12, and the write signal the inverse of MCW of the memory A is inputted to a clock terminal CK of the flip flop 11 to synchronize the count down enable signal CDE with the write signal the inverse of MCW.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing circuit that uses an address counter to specify a memory address, and more particularly to timing alignment between a signal that drives an address counter and a signal that drives a memory.

0002

2. Description of the Related Art Counters such as down counters and up counters are often used as circuits for specifying memory addresses. FIG. 12 shows the conventional configuration. In this conventional device, an oscillation signal OSC at a crystal frequency generated by an oscillation circuit 100 is applied to a system clock generation counter 101, a control signal generation counter 102, and a control signal generation circuit 103. The system clock generation counter 101 performs a counting operation in synchronization with the oscillation signal OSC, and outputs its second output bit as a clock signal CK that drives the down counter drive signal generation circuit 104. Control signal generation counter 102 also performs a counting operation in synchronization with oscillation signal OSC, outputs its second output bit as clock signal CLK of address down counter 105, and inputs its count output to control signal generation circuit 103. Control signal generation circuit 10
3 forms a write signal for the memory 107 based on the oscillation signal OSC and the count output of the control signal generation counter 102, and applies this to the memory 107. The down counter drive signal generation circuit 104 generates drive signals for the address down counter 105 (countdown enable signal CDE, initial value load signal PE, A reset signal R of the control signal counter 102, etc.) is generated and outputted to each circuit. Address initial value setting circuit 1
06 is used to load the initial countdown value of the address down counter 105. The address down counter 105 performs a predetermined down counting operation according to the signals input from each circuit, and outputs the count output to the memory 107 as an address signal. signal BRW
is a borrow signal generated when the counter counts up. The memory 107 receives the input write signal W.
Write operation is performed according to the address signal and the address signal.

In this configuration, when the down counter drive signal generation circuit 104 receives the task start signal TSKST, it generates the countdown enable signal CDE,
The initial value load signal PE is appropriately output to drive the address down counter 105, and the reset signal R is canceled to output the write signal W. Further, the down counter drive signal generation circuit 104 generates a borrow signal BRW indicating that the counting operation of the down counter 105 has been completed to the end.
When inputted, the output of the countdown enable signal CDE is stopped, the reset signal R is restored, and the output of the write signal W is stopped. Furthermore, when the interrupt signal INT is input, writing to the memory 107 is stopped at the same time as the interrupt signal INT is input, and writing to the memory 107 is resumed when the interrupt ends.

[0004].

In such a conventional device, there is a down counter drive signal generation circuit 104 that generates a signal for the address down counter 105 that generates the address of the memory 107, and a write signal W of the memory 107.
The control signal generation circuit 103 forming the counter 1 is operated by the outputs from the separate counters 101 and
Instead of operating 02 all the time, the down counter driving signal generating circuit 104 was used to reset and release the reset signal to cause it to repeatedly stop and operate. There were times when the timing of the signal (CDE or PE) and the write signal W did not match. The situation is shown in the left half of FIG.

Furthermore, in this conventional device, when an interrupt INT occurs due to the above-mentioned causes, the down counter driving signal (CDE or PE) is
There were cases where the timing of the write signal W and the write signal W did not match. The situation is shown in the right half of FIG. Furthermore, when an interrupt occurs, the write operation to the memory is stopped midway by this interrupt, so even if the write operation is resumed after the interrupt ends, data written to the memory 107 may be missing depending on when the interrupt occurs. There was a possibility that double writing would occur.

The present invention was made in view of the above circumstances, and an object thereof is to provide a data processing circuit that reliably synchronizes the timing of a write/read signal input to a memory and an address signal input to the memory. do.

Further, in the present invention, when an interrupt occurs, even after the interrupt ends, the timing of the write/read signal input to the memory and the address signal input to the memory are reliably synchronized, and the data accessed to the memory is The purpose of the present invention is to provide a data processing circuit that provides reliable guarantees.

[0008]

[Means for Solving the Problems] According to a first aspect of the invention, in a data processing circuit that specifies a memory address using an address counter that performs a counting operation from an initial value set in synchronization with an input clock signal, an oscillation circuit that generates a signal of a predetermined frequency; a counter circuit that performs a counting operation in synchronization with the output of the oscillation circuit and uses one bit of the count output as a clock signal for driving the address counter; and an output of the counter circuit. a memory drive basic signal forming circuit that uses the clock signal and the memory basic signal to form a memory drive basic signal that is a source of a signal that drives the memory; and an address counter that controls the address counter using the clock signal and the memory basic signal. and a logic circuit for forming a control signal and a memory control signal for driving the memory. In a second invention, in a data processing circuit that specifies a memory address using an address counter that performs a counting operation from an initial value set in synchronization with an input clock signal, an oscillation circuit that generates a signal of a predetermined frequency. a counter circuit that performs a counting operation in synchronization with the output of this oscillation circuit and uses one bit of the count output as a clock signal for driving the address counter; and a signal that uses the output of the counter circuit to drive the memory. a memory drive basic signal forming circuit that forms a memory drive basic signal that is the basis of the memory drive signal, and a memory drive basic signal forming circuit that controls the address counter based on the clock signal and the memory basic signal, and stops the address counter by starting an interrupt signal. a first logic circuit for forming an address counter control signal for re-driving the address counter after initializing the address counter and re-driving the address counter after the end of an interrupt; and a second logic circuit that generates a memory control signal for driving the address counter, and makes the memory control signal valid after initialization of the address counter is completed in the event of an interrupt.

In the third invention, a plurality of nodes and a controller are connected in a loop, data given from the controller to the plurality of nodes is unidirectionally serially transmitted at a predetermined period, and data from the nodes is serially received at a predetermined period. In the system, a reception data memory stores reception data from the node, a serial-parallel conversion circuit converts the serial output of the first memory into parallel data, and transmits the parallel reception data from the serial-parallel conversion circuit to the node. a transmitting/receiving data shared memory for storing transmission data to be transmitted, a transmitting circuit for forming a transmitting data frame signal to be transmitted to the node based on the transmitting data stored in the transmitting/receiving data shared memory; an address counter that commonly specifies the address of the receive data memory and transmits data from the receive data memory to the transmit/receive data shared memory via the serial/parallel conversion circuit every count cycle; and an oscillation unit that generates a signal of a predetermined frequency. a counter circuit that performs a counting operation in synchronization with the output of the oscillation circuit and uses one bit of the count output as a clock signal for driving the address counter; and a counter circuit that uses the output of the counter circuit to drive the received data memory and a memory drive basic signal forming circuit that forms a memory drive basic signal that is a source of a signal that drives the transmission/reception data shared memory; and a memory drive basic signal forming circuit that controls the address counter based on the clock signal and the memory basic signal. , a first logic for forming a control signal for the address counter that stops the address counter upon the initiation of an interrupt signal from the transmitting circuit and initializes the address counter after the termination of this interrupt and then re-drives the address counter; and forming memory control signals for driving the reception data memory and the transmission/reception data shared memory based on the clock signal and the memory basic signal, respectively, and when there is an interrupt from the transmission circuit. The controller includes a second logic circuit that outputs the memory control signal as valid after completion of the initial setting of the address counter.

In the fourth invention, a signal of a predetermined frequency is generated in a data processing circuit that specifies a memory address using an address counter that performs a counting operation from an initial value set in synchronization with an input clock signal. a counter circuit that performs a counting operation in synchronization with the output of the oscillation circuit and uses one bit of the count output as a clock signal for driving the address counter; and a counter circuit that uses the output of the counter circuit to drive the memory. a memory drive basic signal forming circuit that forms a memory drive basic signal that is the source of a drive signal; a latch circuit that latches an interrupt signal using the memory drive basic signal; Based on the output of the latch circuit, the address counter is controlled, the address counter is stopped by the start of an interrupt signal, and after the interrupt ends, the address counter is restarted from the address next to the output address stopped by the interrupt. A first logic circuit that forms a control signal for an address counter to be driven, and a memory control signal that drives the memory based on the clock signal and the basic memory signal, and when an interrupt occurs. and a second logic circuit that inhibits output of the memory control signal based on the output of the latch circuit.

[0011]

[Operation] In the first invention, the counter circuit is constantly driven, and from the output of the counter circuit, an address counter control signal that drives and controls the address counter and a memory that drives the memory are output. a clock signal for forming a control signal for the
A basic signal for driving the memory, which is the source of the signal for driving the memory, is formed. Further, the address counter control signal that controls the address counter is
It is input to the address counter in synchronization not with the clock signal but with a memory drive basic signal that ultimately becomes the source of the signal that drives the memory. Therefore, the timing of the memory control signal input to the memory and the address input to the memory are completely synchronized.

In the second invention, the timing of the memory control signal input to the memory and the address input to the memory are completely synchronized using the same configuration as the first invention. Furthermore, in the second invention, when an interrupt occurs for accessing the memory, the address counter control signal and the memory control signal are stopped at the same time as the interrupt starts, thereby stopping the access to the memory. After the interrupt ends, the address counter is first initialized, and then the address counter is driven again. The memory control signal is made valid after the initial setting of the address counter is completed.

[0013] In a third invention, a plurality of nodes and a controller are connected in a loop, and data given from the controller to the plurality of nodes is unidirectionally serially transmitted at a predetermined period, and data from the nodes is This is applied to the configuration in the controller of a local area network that receives data serially at a predetermined period, and a shared memory for transmission data and reception data is provided in the controller. Data received from a node is serial-parallel converted and stored in the shared memory. Transmission data is read from the shared memory, converted into a predetermined data frame signal, and transmitted to the node. Transmission control is prioritized over reception control in case of a conflict in access to the shared memory.

In the fourth invention, the timing of the memory control signal input to the memory and the timing of the address input to the memory are completely synchronized using the same configuration as the first and second inventions. Furthermore, in the fourth invention, when an interrupt occurs for accessing the memory, the address counter control signal and the memory control signal are stopped at the same time as the interrupt starts, thereby stopping the access to the memory. After the interrupt ends, the address counter is re-driven from the address next to the output address stopped by the interrupt. The memory control signal is made valid upon completion of the interrupt. At this time, by determining the start and end of the interrupt based on the write control signal to the memory, it is possible to avoid a situation where one address is skipped before or after the interrupt or the write data becomes unstable.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 shows a first embodiment of the present invention, and this FIG. 1 shows a configuration for inputting the count output of an address down counter as address signals A0 to An of memory A. FIG. 2 is a time chart of each signal.

The oscillation circuit 1 generates an oscillation signal OSC at a crystal frequency.
This signal OSC is output to the control signal counter 2 and the write signal generation circuit 3. Control signal counter 2
performs a counting operation synchronized with the oscillation signal OSC, and its second output bit Q1 is used as the clock signal C of this system.
K (see FIG. 2(a)). This clock signal CK is logically inverted by the inverter 4 and then inputted to the address down counter 10 as the clock signal CLK of the address counter 10. The write reference signal generation circuit 3 outputs count outputs Q0 to Q4 of the control signal counter 2.
Based on the above, a write reference signal W, which is the source of a write signal (write signal) MCW for the memory A, is formed, and this write reference signal W (see FIG. 2(b)) is input to the gate 17. Note that in this specification, the signal MCW
The symbol after the signal name, such as signal W or signal W, indicates logical inversion (bar), and the signal marked with is valid at L. Another write reference signal WSD output from the write reference signal generation circuit 3 is:
This will be used in the embodiment shown in FIG. 3 later, and is not related to the embodiment shown in FIG.

Task start signal TSKST (see FIG. 2(c)) is input when a task starts, that is, when the address down counter 10 starts counting (when writing to memory A starts).
is input to the OR gate 5. In the configuration consisting of the OR gate 5, the gate 6, and the flip-flop 7, the gate 6 receives the borrow signal B of the address down counter 10.
Since the logical inversion signal of RW (see FIG. 2(g)) is input, the task signal TSK (see FIG. 2(h)) output from the flip-flop 7 is input to the address down counter 10 after the task is started. The output becomes all 0 and remains high until the borrow signal BRW is output, indicating that the task is being executed. This task signal T
After SK is logically inverted by the inverter 13, the memory A
It is input to memory A as the chip select signal CS. Further, the task start signal TSKST is inputted to the address down counter 10 as the initial value load signal PE, and therefore the task start signal T
When SKST is input, the address initial value set in the address initial value setting circuit 14 is first loaded into the address down counter 10.

The actual write signal MCW (
(see FIG. 2(d)) is created by a flip-flop 8, a gate 9, and a gate 17, and by inputting the write reference signal W, the task signal TSK, and the output of the gate 9 to the gate 17, the write signal MCW
is formed.

Further, the countdown enable signal CDE of the address down counter 10 (see FIG. 2(e)) is
It is formed by a flip-flop 11 and an AND gate 12. In particular, by inputting the write signal MCW of the memory A to the clock terminal CK of the flip-flop 11, the countdown enable signal CDE is synchronized with the write signal MCW. As a result, address A0 of memory A output from address counter 10
The timing of ~An and the write signal MCW can be perfectly matched.

With the above configuration, the address down counter 10 is first loaded with an initial value by the PE signal at the start of a task, and then performs a countdown operation from the initial value in synchronization with the clock signal CLK by the input CDE signal.

As described above, in this embodiment, the write reference signal W, which is the source of the write signal MCW of the memory A, and the system clock signal CK are formed by the same counter 2, and furthermore, they are synchronized with the write signal MCW. Since the countdown enable signal CDE of the address down counter 10 is formed by the address down counter 10, the timing of the addresses A0 to An of the memory A outputted from the address counter 10 and the write signal MCW can be perfectly matched.

In this embodiment, when an up counter is used as the address counter 10, the initial value setting is performed by resetting the address counter 10.

FIG. 3 shows a second embodiment of the present invention. In FIG. 3, the oscillation circuit 1, control signal generation counter 2, and write reference signal generation circuit 3 of FIG. 1 are omitted. The write reference signal WSD in FIG.
is output from the write reference signal generation circuit 3 in FIG. 1, and the clock signal is output from the control signal generation counter 2 in FIG. In this Figure 3,
It is assumed that data is transferred from memory B to memory C via the serial/parallel conversion circuit 20, where memory B is a memory with a data width of 1 bit and memory C is a memory with a data width of 8 bits. Addressing of both memories is done by one address counter 10. Therefore, all bits of the output data of the address counter 10 are input to the memory B address, but the lower three bits of the output data of the address counter 10 are deleted and input to the memory C address. There is.

A time chart of the configuration shown in FIG. 3 is shown in FIG.
6 to 6, FIG. 4 shows the state when there is no interrupt, and FIGS. 5 and 6 show the state when an interrupt occurs.

In FIG. 3, the task start signal TSK
ST (see FIG. 4(l)) is input to the OR gate 21. The logically inverted signal obtained by latching the borrow signal BRW of the address down counter 10 by the flip-flop 41 is input to the gate 22 in the configuration consisting of the OR gate 21, the gate 22, and the flip-flop 23. The task signal TSK output from the step 23 (FIG. 4(c), FIG. 5(c), FIG. 6(a)
), after the task is started, the output of the address down counter 10 becomes all 0, and the borrow signal BR is generated.
It remains H until W is output.

It should be noted that, as will become clear later in the explanation, when the interrupt signal INT is input, the counting operation of the address counter is stopped midway, so that the borrow signal BRW is no longer output. Therefore, the task signal TSK does not fall to L even after the counting operation of the address counter is stopped. That is, this task signal TSK does not accurately indicate the actual task period, but is used to determine whether the task has been completed.

Interrupt signal INT (FIG. 5(d), FIG. 6(
c)) is the clock signal CK in the flip-flop 29.
(See FIGS. 4(a) and 5(a)). The configuration consisting of a flip-flop 30 and a gate 31 captures the falling edge of the interrupt signal INT (interrupt end), and outputs the interrupt end signal INTED (FIG. 5(g)) which becomes H for a short time when the interrupt signal INT falls. ) and outputs it to the OR gate 25. As will be explained later, this interrupt end signal INTED is used to automatically restart from the beginning the counting operation of the address down counter 10, which was halted due to the interrupt, after the interrupt ends.

The configuration of the OR gate 25, the gate 26, and the flip-flop 27 generates a task execution signal TSKE (FIG. 4(d), FIG. 5(e),
(see FIG. 6(b)), outputs TSKE which becomes L during an interrupt period and when a task is not being executed, and becomes H only when there is no interrupt and a task is actually executed. This task execution signal TSKE is logically inverted by the inverter 28 and then input to the memory B as the memory B chip select signal CS. Further, this task execution signal TSKE is used to form each drive signal PE and CDE of the address down counter 10 and the write signal WEL of the memory C (see FIG. 4(g)). Further, the clock signal CK generated by the control signal generation counter 2 shown in FIG.
The signal is input to the address counter 10 as the clock signal CLK of the address counter 10 via the address counter 10.

Write reference signal WSD (FIG. 4(b), FIG. 5(b)) generated by write reference signal generation circuit 3 of FIG.
) is latched by the flip-flop 33 using the clock signal CK, and is output from the flip-flop 33 as the WSD1 signal (see FIG. 4(j)). In addition,
One pulse of this WSD signal is output every time the least significant bit A0 of the address counter 10 changes from L to H or from H to L eight times (four cycles).

The structure of the flip-flops 34 and 35 forms the initial value load signal PE and countdown enable signal CDE of the address down counter 10 by latching the task execution signal TSKE twice at the timing of the inverted signal of the WSD1 signal. TSK for
An E1 signal (see FIG. 4(k)) is formed. That is, the output of the flip-flop 34 is such that the task execution signal is H.
After the task execution signal becomes H, the TSKE1 signal outputs a signal that becomes H when the first write reference signal WSD signal is input, and the TSKE1 signal becomes H when the second write reference signal WSD signal is input after the task execution signal becomes H. . Gate 37 is
The output of the flip-flop 34 is ANDed with the logically inverted signal of the TSKE1 signal, and the output is sent to the flip-flop 3.
9 to the initial value load signal PE (FIG. 4(e), FIG. 5(
h)). That is, gate 37
An initial value load signal PE that maintains H only during the period corresponding to the first write reference signal WSD signal after the TSKE signal becomes H is formed, and this initial value load signal PE is used to control the address initial value setting circuit 14. The set value is loaded into the address down counter 10.

The gate 38 also receives a task execution signal TS.
The KE and TSKE1 signals are ANDed and this is used as the countdown enable signal CDE ((Fig. 4(f), Fig. 5(
f)) is input to the address down counter 10, so that the write reference signal WSD signal is inputted for the second time until the countdown ends, or after the second write reference signal WSD signal is inputted. A CDE signal is formed that maintains H until the interrupt signal INT is input.

The flip-flop 36, gate 40 and OR gate 42 are connected to the task execution signals TSKE, TSK.
A write signal WEL to memory C is generated by the E1 signal and the write reference signal WSD ((Fig. 4(g))
With these configurations, the third and subsequent write reference signals WSD after the task start signal is input are input to the memory C as the write signal WEL. In such a configuration, when the interrupt signal INT is input during task execution,
The task execution signal TSK falls to L, which causes the countdown enable signal CDE to fall to L. As a result, the counting operation of the address down counter 10 is stopped, and thereby writing to the memory 10 is stopped midway. When the interrupt ends, the interrupt signal INT falls to L, so the interrupt end signal I
NTED stands up to H. This interrupt end signal IN
Using the TED, the write operation to the memory 10, which was interrupted due to the interrupt, is automatically re-executed from the beginning. That is, this interrupt end signal INTE
D, the task execution signal TSK rises to H again, and as a result, the initial value load signal PE is first output to the address down counter 10 and the address initial value setting circuit 1
The set value of 4 is loaded into the address down counter 10. Thereafter, the countdown enable signal CDE is output to the address down counter 10, and the clock signal CDE is output to the address down counter 10.
The address down counter 10 starts counting down based on LK. When all bits of the output of the address down counter 10 become 0, a borrow signal BRW is output, thereby ending the current task.

According to the embodiment shown in FIG. 3, as in the previous embodiment, the write reference signal WSD, which is the source of the write signal WEL of the memory C, and the system clock signal CK
are formed by the same counter 2, and are synchronized with the write reference signal WSD (more precisely, with the WSD1 signal) to form the countdown enable signal CDE of the address down counter 10. address A0~ of memory A
The timing of An and the write signal WEL can be perfectly matched.

Furthermore, in this embodiment, if an interrupt occurs while writing to the memory, the write operation to the memory is automatically restarted from the beginning after the interrupt ends, so even if an interrupt occurs, accurate writing can be performed. can perform actions.

FIG. 7 shows a third embodiment of the present invention, and shows a system to which the embodiment shown in FIG. 3 is applied.

The system shown in FIG. 7 is a local area network system in which a controller 52 and a plurality of nodes are connected in a loop.

The controller 52 controls the transmission and reception of data frame signals that are periodically sent to the plurality of nodes, and in this case, the controller 52 has a memory that stores the transmitted data frame signals and a memory that stores the received data frame signals. is shared by the transmitting and receiving data memory C. The transmitter 50 forms a transmit data frame signal according to the transmit data stored in the transmit/receive data memory C and outputs the signal to the node. The receiving device 51 temporarily stores the received frame signal from the node in the memory B within the receiving device 51, and stores it in the transmitting/receiving memory C via the S/P conversion circuit 20. That is, each memory B in FIG.
, C, and S/P conversion circuit 20 completely correspond to the memory B, C, and S/P conversion circuit 20 in FIG. 3, and the memory control circuit 52 corresponds to each circuit configuration including the address down counter 10 in FIG. ing.

Therefore, in this case, if the processing on the transmitting side is given priority over the S/P conversion processing on the receiving side, and the interrupt signal INT shown in FIG. 3 is inputted from the transmitting side to the memory control device 52, The circuit configuration of FIG. 3 can be applied as is.

FIG. 8 is based on the assumption that an interrupt signal is input to the configuration shown in FIG. 1, and only the portion indicated by the broken line is added, and the rest is the same as that shown in FIG. 1. The configuration is basically the same, and redundant explanation will be omitted. FIG. 9 is a time chart of each signal in the configuration of FIG. 8.

In other words, in this case, when the interrupt INT occurs, writing to memory A is interrupted in the middle, as in the embodiment shown in FIG. Rather than restarting the process from the beginning as in the embodiment of FIG. 3, the process is restarted from the address next to the address where it was interrupted.

In FIG. 8, the interrupt signal INT (FIG. 9
(c)) is input to the flip-flop 70, and the write reference signal W
is latched at the timing of , and the MSK signal (Fig. 9(d)
reference). The logical inversion signal of this MSK signal is used as the countdown enable signal CDE (FIG. 9(f)).
(see) by inputting it to the AND gate 12 that forms
The counting operation of the address down counter 10 is stopped when the interrupt starts, and the counting operation of the address down counter 10 is restarted from the middle when the interrupt ends. In addition, the chip select signal CS of the memory 10
A gate 71 is inserted before the inverter 13 forming the chip select signal CS, and by inputting a logical inversion signal of the MSK signal to the gate 71, interruption and restart due to an interrupt of the chip select signal CS is controlled. The same applies to the write signal MCW to the memory 10 (see FIG. 9(d)), and by inserting a gate 72 and inputting a logical inversion signal of the MSK signal to the gate 72, the write signal MCW can be generated by the above-mentioned interrupt. Control suspension and resumption.

That is, the interrupt signal INT is latched by the write reference signal W which is the source of the write signal for the memory A, and this latch signal MSK causes the address down counter 10 to stop and restart and the chip select signals CS and C to the memory 10 to be stopped and restarted. Light signal MCW
Even if an interrupt is started in the middle of actually writing to memory A, the counting operation of the address down counter 10 will stop midway after this writing is completed. At the same time, after the interrupt ends, the address down counter 10 will output a count from the next count value of the previously stopped count value, and the count value of the address down counter 10 will be skipped by one. This eliminates the possibility of duplicate count values.

Incidentally, FIG. 10 shows a time chart when the interrupt signal INT is latched at the falling edge of the clock signal CK which is out of phase with the write reference signal W, and FIG. A time chart is shown when latching occurs at the rising edge of . When the interrupt signal INT is latched at the falling edge of the clock signal CK as shown in FIG. 10, the countdown enable signal CDE changes at the falling edge of the clock signal CK, so the address down counter 10 output
0 (in this case only the least significant bit A0 is shown) is shown in FIG.
In this case, the first write signal MCW generated after the interrupt ends
When , one address is skipped and input to memory A.

Furthermore, as shown in FIG. 11, the interrupt signal INT
If the write signal MCW is latched at the rising edge of the clock signal CK, the pulse width of the write signal MCW may be halved and output as shown in (g) in Figure 11. There is no guarantee that you can write to A.

On the other hand, as shown in FIG.
If NT is determined based on the rising edge of the write reference signal W 1 , the problems shown in FIGS. 10 and 11 can be reliably prevented.

It should be noted that the above-described embodiments of the present invention can be modified as appropriate; for example, the circuit configuration of each embodiment can be modified as long as the same function can be achieved. Further, an up counter may be used for specifying addresses to the memory. Further, in the embodiment, the present invention is mainly used for controlling writing to the memory, but the present invention may be used for controlling reading from the memory.

[0048]

[Effects of the Invention] As explained above, according to the present invention,
A constantly driven counter circuit is used to form a clock signal for driving an address counter and a memory driving basic signal which is the source of a memory driving signal, and the clock signal and the memory basic signal are used to form the memory driving basic signal. An address counter control signal that controls the address counter and a memory control signal that drives the memory are formed, and the address counter control signal that controls the address counter is a memory drive signal that is the source of the signal that drives the memory. Since the input to the address counter is synchronized with the basic signal, the timing of the memory control signal input to the memory and the address input to the memory are completely synchronized, thereby ensuring accurate memory access operations. obtain.

Further, in the present invention, when an interrupt occurs, the address counter control signal and the memory control signal are stopped at the same time as the interrupt starts, thereby stopping access to the memory, and after the interrupt ends, the address counter is first The address counter is initialized and then the address counter is re-driven, and the memory control signal is enabled after the address counter initialization is completed, so even if an interrupt occurs, accurate memory access is possible. can be done.

Further, according to the present invention, the main controller is provided with a memory for sharing transmission and reception data, and access to this transmission and reception memory is given priority to the transmitting side, so that the transmission and reception memory can be shared without changing the sending cycle of transmission frames.

Furthermore, in the present invention, when the address counter is re-driven from the address next to the output address stopped by the interrupt after the interrupt ends, the start and end of the interrupt is determined by the write control signal to the memory. This makes it possible to avoid situations where one address is skipped before or after an interrupt or where write data becomes unstable.

[Brief explanation of the drawing]

FIG. 1 is a logic circuit diagram showing a first embodiment of the present invention.

FIG. 2 is a time chart explaining the operation of the first embodiment.

FIG. 3 is a logic circuit diagram showing a second embodiment of the invention.

FIG. 4 is a time chart illustrating the operation of the second embodiment when there is no interrupt.

FIG. 5 is a time chart illustrating the operation of the second embodiment when there is an interrupt.

FIG. 6 is a time chart illustrating the operation of the second embodiment when there is an interrupt.

FIG. 7 is a diagram showing a third embodiment of the invention.

FIG. 8 is a logic circuit diagram showing a fourth embodiment of the invention.

FIG. 9 is a time chart explaining the operation of the fourth embodiment.

FIG. 10 is a diagram showing a conventional technique corresponding to the fourth embodiment.

FIG. 11 is a diagram showing another conventional technique corresponding to the fourth embodiment.

FIG. 12 is a diagram showing a prior art.

FIG. 13 is a time chart illustrating the operation of the prior art.

[Explanation of symbols]

1...Oscillation circuit 10...Address down counter 20...S/P conversion circuit A, B, C...Memory

Claims (4)

[Claims] 1. An oscillation circuit that generates a signal of a predetermined frequency in a data processing circuit that specifies a memory address using an address counter that performs a counting operation from an initial value set in synchronization with an input clock signal. a counter circuit that performs a counting operation in synchronization with the output of this oscillation circuit and uses one bit of the count output as a clock signal for driving the address counter; and a signal that uses the output of the counter circuit to drive the memory. a memory drive basic signal forming circuit that forms a memory drive basic signal that is the basis of the memory drive signal, an address counter control signal that controls the address counter using the clock signal and the memory basic signal, and a memory that drives the memory. a logic circuit for forming control signals for the data processing circuit. 2. An oscillation circuit that generates a signal at a predetermined frequency in a data processing circuit that specifies a memory address using an address counter that performs a counting operation from an initial value set in synchronization with an input clock signal. a counter circuit that performs a counting operation in synchronization with the output of this oscillation circuit and uses one bit of the count output as a clock signal for driving the address counter; and a signal that uses the output of the counter circuit to drive the memory. a memory drive basic signal forming circuit that forms a memory drive basic signal that is the basis of the memory drive signal, and a memory drive basic signal forming circuit that controls the address counter based on the clock signal and the memory basic signal, and stops the address counter by starting an interrupt signal. a first logic circuit for forming an address counter control signal for re-driving the address counter after initializing the address counter and re-driving the address counter after the end of an interrupt; a second logic circuit that forms a memory control signal that drives the memory control signal, and makes the memory control signal valid after initialization of the address counter is completed in the event of an interrupt. 3. A system in which a plurality of nodes and a controller are connected in a loop, data given from the controller to the plurality of nodes is unidirectionally serially transmitted at a predetermined period, and data from the nodes is serially received at a predetermined period, The controller includes a reception data memory that stores reception data from the node, a serial-to-parallel conversion circuit that converts the serial output of the first memory into parallel data, and a connection between the parallel reception data from the serial-to-parallel conversion circuit and the node. a transmission/reception data shared memory that stores transmission data to be transmitted; a transmission circuit that forms a transmission data frame signal to be transmitted to the node based on the transmission data stored in the transmission/reception data shared memory;
an address counter that commonly specifies addresses of the transmission/reception data shared memory and the reception data memory, and transmits data from the reception data memory to the transmission/reception data shared memory via the serial/parallel conversion circuit at each count cycle; an oscillation circuit that generates a frequency signal, a counter circuit that performs a counting operation in synchronization with the output of this oscillation circuit, and uses one bit of the count output as a clock signal for driving the address counter; a memory driving basic signal forming circuit that uses the memory driving basic signal to form a memory driving basic signal that is a source of a signal for driving the received data memory and the transmitted/received data shared memory, and based on the clock signal and the memory basic signal, an address counter control signal that controls the address counter, stops the address counter in response to the start of an interrupt signal from the transmitting circuit, initializes the address counter after the interrupt ends, and then re-drives the address counter; ,
a first logic circuit to be formed, and a memory control signal for driving the reception data memory and the transmission/reception data shared memory based on the clock signal and the memory basic signal, and a second logic circuit that outputs the memory control signal as valid after completion of the initial setting of the address counter when there is an interrupt. 4. An oscillation circuit that generates a signal of a predetermined frequency in a data processing circuit that specifies a memory address using an address counter that performs a counting operation from an initial value set in synchronization with an input clock signal. a counter circuit that performs a counting operation in synchronization with the output of this oscillation circuit and uses one bit of the count output as a clock signal for driving the address counter; and a signal that uses the output of the counter circuit to drive the memory. a memory drive basic signal forming circuit that forms a memory drive basic signal that is the source of the memory drive basic signal, a latch circuit that latches an interrupt signal using the memory drive basic signal, and a memory drive basic signal forming circuit that forms the memory drive basic signal that is the basis of the memory drive basic signal, and a latch circuit that latches the interrupt signal using the memory drive basic signal; an address that controls the address counter based on the output, stops the address counter with the onset of an interrupt signal, and re-drives the address counter after the end of the interrupt from an address next to the output address stopped by the interrupt; a first logic circuit that forms a counter control signal; and a memory control signal that drives the memory based on the clock signal and the memory basic signal; a second logic circuit that inhibits output of the memory control signal by an output of the circuit.