JPH06290586A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To use the memory without a dummy cycle by generating a signal corresponding to a dummy cycle through a ring oscillator based on a reset signal supplied to an internal circuit by a power on reset(POR) circuit after turning on a power supply. CONSTITUTION:A reset signal in which POR 1 is a POR signal of a L level until power supply Vcc varies from a L level to a H level after turning on a power supply is outputted to an internal circuit 3. Receiving this reset signal, a ring oscillator 4 continues to output a pulse phi2 during an initial pause period, supplies it to a row access strobe(RAS) buffer 2, and a pulse phi1 obtained by ORing the pulse phi2 and an external RAS is given to a circuit 3. Thereby, the circuit 3 performs operation internally corresponding to a dummy cycle by the pulse phi2 during an initial pause period, and a device can be immediately and normally used without giving externally the dummy cycle, after finish of the initial pause period.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device such as DRAM. In particular, the present invention relates to a semiconductor memory device that can be used without a dummy cycle after power is turned on.

[0002]

2. Description of the Related Art In recent years, semiconductor memory devices have been required to have lower power consumption and higher speed. Therefore, it is desired that the power supply be turned on to be in a standby state as soon as possible so that it can be used as soon as possible.

FIG. 7 shows the structure of a conventional semiconductor memory device.
Will be described with reference to. FIG. 7 is a diagram showing a conventional semiconductor memory device.

In FIG. 7, reference numeral 1 denotes a reset signal (//) supplied to a predetermined internal circuit of the semiconductor memory device in response to a power-on signal.
Power-on reset circuit (PO)
R), 2 receives internal / RAS signal from external / RAS signal
A / RAS buffer 3 for generating a signal (φ1 signal) is an internal circuit.

Next, the operation of the conventional semiconductor memory device will be described with reference to FIG. FIG. 8 is a timing chart showing the operation of the conventional semiconductor memory device. Figure 8
, (A) is the power supply voltage Vcc, (b) is / RAS
Signal, (c) shows a φ1 signal, and (d) shows a / POR signal.

The power-on reset circuit 1 receives a Vcc power source supplied from an external power source, and the power source voltage Vc
It is a circuit for applying a one-shot pulse to a predetermined internal circuit 3 of the semiconductor memory device upon the rise of c to reset the predetermined internal circuit 3. At this time, the signal given to the predetermined internal circuit 3 is called a / POR signal.

As shown in FIG. 8A, first, when the power is turned on, the power supply voltage Vcc rises from "L" to "H". Then, the / POR signal remains "L" when the power is turned on, and the predetermined internal circuit 3 of the semiconductor memory device is reset. And
As shown in FIG. 8D, the / POR signal is switched to "H" by itself within the initial pause period, and the reset of the predetermined internal circuit 3 is completed.

In order to use the semiconductor memory device after the user has turned on the power and the initial pause period has passed, / RAS
There is a rule (specification) that dummy cycles by signals must be inserted a specified number of times. Therefore, in FIG.
As shown in (b) and (c), after the dummy cycle by the / RAS signal is inserted a specified number of times, it can be normally used as a normal cycle.

[0009]

In the conventional semiconductor memory device as described above, it is necessary to insert the dummy cycle after the initial pause period a prescribed number of times before the user starts normal use. There is a problem that the normal use start time is delayed by the amount of the existing period.

The present invention has been made to solve the above-mentioned problems, and provides a semiconductor memory device which can immediately enter a normal cycle without turning on the power and inserting a dummy cycle after the initial pause period. The purpose is to get.

[0011]

A semiconductor memory device according to claim 1 of the present invention comprises the following means. [1] A power-on reset circuit that sends a reset signal to the internal circuit when the power is turned on. [2] A ring oscillator that outputs a pulse of a constant cycle during an initial pause period based on the reset signal. [3] A logical sum means for calculating the logical sum of the pulse having the constant period and the external / RAS signal and sending the logical sum to the internal circuit.

A semiconductor memory device according to claim 2 of the present invention comprises the following means. [1] A power-on reset circuit that sends a reset signal to the internal circuit when the power is turned on. [2] A ring oscillator that outputs a pulse of a constant cycle during an initial pause period based on the reset signal. [3] A counter that controls the operation period of the ring oscillator by counting the pulses of the constant cycle. [4] A logical sum means for calculating a logical sum of the pulse having the constant period and the external / RAS signal and sending the logical sum to the internal circuit.

[0013]

In the semiconductor memory device according to the first aspect of the present invention, the power-on reset circuit sends the reset signal to the internal circuit when the power is turned on. Further, the ring oscillator outputs a pulse having a constant cycle during the initial pause period based on the reset signal. Further, the logical sum means calculates the logical sum of the pulse having the constant period and the external / RAS signal and sends the logical sum to the internal circuit.

In the semiconductor memory device according to the second aspect of the present invention, the power-on reset circuit sends the reset signal to the internal circuit when the power is turned on. Further, the ring oscillator outputs a pulse having a constant cycle during the initial pause period based on the reset signal. Further, the counter counts the pulses of the constant cycle to control the operation period of the ring oscillator. Then, the logical sum means calculates the logical sum of the pulse having the constant period and the external / RAS signal and sends the logical sum to the internal circuit.

[0015]

【Example】

Example 1. Hereinafter, the configuration of the first embodiment of the present invention will be described with reference to FIG. 1 is a block diagram showing a configuration of a first embodiment of the present invention, and power-on reset circuit 1 to internal circuit 3 are the same as those of the conventional device described above. In the drawings, the same reference numerals indicate the same or corresponding parts.

In FIG. 1, reference numeral 4 is a ring oscillator, the operation of which is controlled by the / POR signal.

By the way, the logical sum means of the present invention corresponds to the / RAS buffer 2 in the first embodiment.

Next, the operation of the first embodiment of the present invention will be described with reference to FIG. FIG. 2 is a timing chart showing the operation of the first embodiment of the present invention. In FIG. 2, (a) shows the power supply voltage Vcc, (b) shows the / RAS signal, (c) shows the pulse φ1, (d) shows the pulse φ2, and (e) shows the / POR signal, respectively.

When the power is turned on, the power supply voltage Vcc rises from "L" to "H" as shown in FIG. 2 (a). / POR
The signal remains "L" when the power is turned on, and the predetermined internal circuit 3 of the semiconductor memory device is reset. In the first embodiment of the present invention, the / POR signal is also input to the ring oscillator 4.

Upon receipt of the / POR signal, the ring oscillator 4 continues to send a periodic pulse φ2 to the / RAS buffer 2 during the initial pause period until the / POR signal changes to "H". Since / RAS buffer 2 is operatively formed with an OR logic with an external / RAS signal, pulse φ1 is applied to internal circuit 3 in response to pulse φ2.

As a result, during the initial pause period, the pulse φ2 internally causes the internal circuit 3 to perform an operation corresponding to a dummy cycle. Therefore, after the initial pause period, the user can immediately start normal use without giving a dummy cycle from the outside.

The first embodiment of the present invention, as described above,
Power-on reset circuit 1 which sends a reset signal (/ POR signal) to internal circuit 3 in response to the input of power supply voltage Vcc
And a ring oscillator 4 that operates using the reset signal as a control signal. By using the output signal (φ2) of the ring oscillator 4, a signal (φ1) for internally performing an operation corresponding to a dummy cycle is supplied to the internal circuit 3 for a while after the power is turned on. As a result, since the operation corresponding to the dummy cycle is internally performed within the initial pause period, after the initial pause period, the user can immediately perform normal use without performing the dummy cycle from the outside.

Example 2. The configuration of the second embodiment of the present invention will be described with reference to FIG. FIG. 3 is a block diagram showing the configuration of the second embodiment of the present invention.

In FIG. 3, the same reference numerals as those of the conventional device indicate the same or corresponding parts. Reference numeral 4 is a ring oscillator, the operation of which is controlled by the / POR signal. Reference numeral 5 is a counter, which receives the operation of the ring oscillator 4 to count the pulses φ2, and controls the operation period of the ring oscillator 4 by the output (/ φ3) of the counter 5.

Next, the operation of the second embodiment of the present invention will be described with reference to FIG. FIG. 4 is a timing chart showing the operation of the second embodiment of the present invention. In FIG. 4, (a) is the power supply voltage Vcc, (b) is the / RAS signal, (c) is the pulse φ2, (d) is the pulse φ1, (e) is the / φ3 signal, and (f) is the / POR signal. Are shown respectively.

When the power is turned on, the power supply voltage Vcc rises from "L" to "H" as shown in FIG. 4 (a). As shown in FIG. 6F, the / POR signal remains "L" when the power is turned on, and the predetermined internal circuit 3 of the semiconductor memory device is reset.

In the second embodiment of the present invention, the pulse φ
2 is input to the counter 5. The counter 5 outputs / φ3, which controls the operation of the ring oscillator 4. Ring oscillator 4 is / POR
During the initial pause period in response to the signal, a periodic pulse φ2 is transmitted to the / RAS buffer 2. At the same time, the counter 5 receives the pulse φ2 and counts the number of φ2 pulses.

When the pulse number of the pulse φ2 reaches the predetermined count number, the counter 5 changes the output / φ3 from "L" to "H" as shown in FIG. 4 (e) to operate the ring oscillator 4. To stop. The predetermined count number may be enough to generate the pulse number of the pulse φ1 defined as the dummy cycle.

As a result, during the initial pause period, the operation corresponding to the dummy cycle is internally performed by the pulse φ2 in the internal circuit 3. Therefore, after the initial pause period, the user can immediately start normal use without giving a dummy cycle from the outside.

Example 3. In the above two Examples 1 and 2, the pulse φ2 of the ring oscillator 4 is /
Although input to the RAS buffer 2, as shown in FIG. 5, an OR logic of the pulse φ1 and the pulse φ2 of the / RAS buffer 2 may be configured by the OR gate 6 and supplied to the internal circuit 3.

Example 4. Further, as shown in FIG. 6, even if the AND gate 8 takes the / POR signal and the AND logic from the power-on reset circuit by the AND gate 8 and ignores the / RAS signal and prioritizes the pulse φ2, as shown in FIG. The purpose of causing the circuit 3 to perform the operation corresponding to the dummy cycle is achieved.

[0032]

As described above, the semiconductor memory device according to the first aspect of the present invention has a power-on reset circuit which sends a reset signal to an internal circuit when power is turned on, and an initial pause based on the reset signal. Since the ring oscillator for outputting a pulse of a constant cycle during the period and the logical sum means for taking the logical sum of the pulse of the constant cycle and the external / RAS signal and sending it to the internal circuit are provided, the user can make a dummy after the initial pause period. There is an effect that a normal use can be immediately performed without inserting a cycle from the outside and losing time.

As described above, in the semiconductor memory device according to the second aspect of the present invention, the power-on reset circuit that sends a reset signal to the internal circuit when the power is turned on, and the initial pause period based on the reset signal. A ring oscillator that outputs a pulse of a fixed cycle, a counter that counts the pulse of the fixed cycle and controls the operation period of the ring oscillator, and the internal circuit that ORs the pulse of the fixed cycle and an external / RAS signal Since it is provided with a logical sum means for sending the data to the user, after the initial pause period, the user can put the dummy cycle into the dummy cycle from the outside and immediately use the dummy cycle without any time loss.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a first embodiment of the present invention.

FIG. 2 is a timing chart showing the operation of the first embodiment of the present invention.

FIG. 3 is a block diagram showing a configuration of a second embodiment of the present invention.

FIG. 4 is a timing chart showing the operation of the second embodiment of the present invention.

FIG. 5 is a diagram showing a configuration of a third embodiment of the present invention.

FIG. 6 is a diagram showing a configuration of a fourth embodiment of the present invention.

FIG. 7 is a block diagram showing a configuration of a conventional semiconductor memory device.

FIG. 8 is a timing chart showing an operation of a conventional semiconductor memory device.

[Explanation of symbols]

 1 Power-on reset circuit 2 / RAS buffer 3 Internal circuit 4 Ring oscillator 5 Counter

Claims (2)

[Claims] 1. A power-on reset circuit which sends a reset signal to an internal circuit when power is turned on, a ring oscillator which outputs a pulse of a constant cycle in an initial pause period based on the reset signal, and a pulse of the constant cycle. A semiconductor memory device comprising a logical sum means for calculating a logical sum of external / RAS signals and sending the logical sum to the internal circuit. 2. A power-on reset circuit that sends a reset signal to an internal circuit when power is turned on, a ring oscillator that outputs a pulse of a constant cycle during an initial pause period based on the reset signal, and a pulse of the constant cycle. A semiconductor memory device comprising: a counter for controlling an operation period of the ring oscillator; and a logical sum means for calculating a logical sum of the pulse of the constant cycle and an external / RAS signal and sending the logical sum to the internal circuit.