JP2552388B2 - Semiconductor memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial field of application] The present invention can be obtained by taking in input data and a synchronization signal indicating the timing of a definite period of the input data, and applying a plurality of types of logical operations to the input data. The present invention relates to a semiconductor memory device that stores a plurality of logical operation results.

[Conventional technology]

FIG. 6 is a block diagram showing the inside of a conventional command register. As shown in the figure, a predetermined number of bits of input data DT given from the normal CPU and a synchronization signal S0 for instructing the timing of the definite period of the input data DT are taken in.

The input data DT is taken in common to each combination circuit 1a to 1c, each combination circuit 1a to 1c performs a predetermined logical operation based on the input data DT, and the logical operation results L1 to L3 are given to the delay circuits 2a to 2c. Output. At this time, the combinational circuits 1a, 1b and 1c each have a logical operation delay time of lt1, lt2, lt3 (lt1 <lt1 < lt2 <lt3). Then, the delay circuits 2a, 2b and 2c change the logical operation result L
1, L2 and L3 are timed dt1, dt2, dt3 (dt1>dt2> dt
3) Delay and output the delay logic operation results L1 'to L3' to the D inputs of the D flip-flops 3a to 3c, respectively.

Further, the synchronizing signal S0 is taken in by the synchronizing signal delay circuit 4, and the synchronizing signal delay circuit 4 delays the synchronizing signal by the time dt4 so that the delayed synchronizing signal S0 'is input to the C (clock) inputs of the D flip-flops 3a to 3c. Output in common. These D flip-flops 3a to 3c are delayed synchronizing signals S obtained from the C input.
Using the rising edge of 0'as a trigger, the delay logic operation results (L1 'to L3') obtained from the D input are latched, and the Q outputs Q1 to Q3 are latched.
And output to the outside.

FIG. 7 is a timing chart showing the operation of the command register shown in FIG. It should be noted that in FIG. 7, the defined period of the input data DT and the (delayed) logical operation results L1 (') to L3 (') is indicated by diagonal lines.

Referring to the figure, when the input data DT is determined at time t1, the combinational circuits 1a to 1c respectively perform a logical operation based on the determined input data DT, and the logical operation results L1, L2 and L
3 is the logical operation delay time lt1, lt2 and lt from time t1
Output starts at time t3, t4, and t5 after 3 lapses. In this way, the logical operation delay time is different from that of the combinational circuits 1a to 1c.
This is because the contents of each logical operation are different. On the other hand, the synchronization signal S0 rises at time t7 during the fixed period of the input data DT.

Note that the fixed period of the input data DT is the period T1 (time t1 ~
t2), therefore, the final period of each logical operation result L1 to L3 depends on the content of the respective logical operation processing, and the time t3, t
It becomes a little shorter than the period T1 from 4 and t5. The decision period T1 of the input data DT tends to be shortened to about 10 ns as the CPU speed increases, and the deviation of the decision period of each logical operation result L1 to L3 cannot be included, and the logical operation results L1 and L3 in FIG. 7 cannot be included. As shown in, the cases where the fixed periods do not match are likely to occur.

These logical operation results L1 to L3, which are deviated in the fixed period, start output of the delayed logical operation results L1 'to L3' at the same time t6 by passing through the delay circuits 2a to 2c having different delay times. Will be corrected. As a result, the definite period of the delay logic operation results L1 'to L3' starts at time t6.

On the other hand, the synchronization signal delay circuit 4 outputs the synchronization signal S0 at time dt4.
With a delay, the delay synchronization signal S0 'is raised at time t8 during the period in which the delay logical operation results L1' to L3 'are established. As a result, at time t8, the delay logic operation results L1 'to L3' are accurately stored in the flip-flops 3a to 3c, respectively.

As described above, the conventional command register is provided with the delay circuits 2a to 2c and 4 therein, so that the command can be accurately latched even when the fixed period T1 of the input data DT is shortened due to the speeding up of the CPU. Is configured.

 The delay times dt1 to dt3 of the delay circuits 2a to 2c are set to be lt1 + dt1 = lt2 + dt2 = lt3 + dt3 (1).

[Problems to be Solved by the Invention]

The conventional command register corresponding to the high-speed CPU is configured as described above, and there is a problem that the circuit configuration becomes complicated due to the provision of the delay circuit for the output of each logical operation result.
Further, in each delay circuit, it is necessary to strictly set different delay times in order to accurately correct the deviation of the decision period of each logical operation result, so that there is a problem that timing control is difficult.

The present invention has been made to solve the above problems, and to obtain a semiconductor memory device capable of supporting a high-speed CPU, simplifying the circuit configuration, and performing timing control relatively easily. With the goal.

[Means for solving the problem]

A semiconductor memory device according to the present invention stores input data and a plurality of logical operation results obtained by performing a plurality of types of logical operations on the input data by taking in a synchronization signal that indicates the timing of a definite period of the input data. And a first storage means for storing the input data as latch data during the fixed period of the input data based on the timing of the synchronization signal, and the first storage means provided in parallel with the first storage means. A plurality of combinational circuits that logically operate the latched data of the first storage means and output the plurality of logical operation results, and a delay circuit that delays the synchronization signal for a predetermined period and outputs a delayed synchronization signal, A plurality of combination circuits are provided corresponding to the plurality of combination circuits and store the plurality of logical operation results at timings based on the delay synchronization signal. It is constituted by a second storage means.

[Action]

In the present invention, the first storage means stores the input data as latch data during the fixed period of the input data based on the timing of the synchronizing signal, and the plurality of combination circuits logically operate the latch data. Output the logical operation result.

Therefore, the fixed period of the logical operation result of the plurality of combinational circuits becomes longer in proportion to the storage period of the latch data in the first storage means.

〔Example〕

FIG. 1 is a diagram showing a command register which is a first embodiment of the present invention. As shown in the figure, the input data DT and the input data DT of a predetermined number of bits normally given from the CPU
The sync signal S0 for instructing the timing of the definite period is taken into the internal latch 5. When the synchronizing signal S0 is L, the latch 5 retains the input data DT as it is and latches the output data S5.
, And input data at the rising edge of the sync signal S0.
DT is stored as latch data, and thereafter, the synchronization signal S0 goes high.
During the period of, the stored latched data is
Output as

Then, the latch output data S5 is commonly fetched by the combinational circuits 1a to 1c. Each combinational circuit 1a to 1c performs a predetermined logical operation based on the latch output data S5, and outputs the logical operation result L1 to L3 to the D inputs of the D flip-flops 3a to 3c. At this time, the logical operation delay circuits of the combinational circuits 1a, 1b and 1c are lt1, lt2 and lt3 (lt1 <lt2 <lt
3).

Further, the synchronization signal S0 is taken in by the synchronization signal delay circuit 4, and the synchronization signal delay circuit 4 delays the synchronization signal S0 by the time dt5 and outputs the delayed synchronization signal S0 'to the D flip-flops 3a to 3c.
It is commonly output to the C (clock) input of. These flip-flops 3a to 3c are delayed synchronization signals S obtained from the C input.
The logical operation result (L1 to L3) obtained from the D input is stored by using the rising edge of 0'as a trigger and is output to the outside as Q outputs Q1 to Q3.

FIG. 2 is a timing chart showing the operation of the command register shown in FIG. Note that, in FIG. 2, the definite period of the input data DT, the latch output data S5, and the logical operation results L1 to L3 is indicated by diagonal lines.

With reference to the figure, when the input data DT is confirmed at time t1, since the synchronization signal S0 is L, the confirmed input data DT passes through the latch 5 and is given to the combinational circuits 1a to 1c as it is.

Then, the combinational circuits 1a to 1c receive the confirmed input data DT
Based on each of the logical operation, the logical operation result L
1, L2 and L3 are respectively the logical operation delay time lt1, from time t1
Output at time t3, t4, t5 after lt2 and lt3. The reason why the logical operation delay time is different is that the contents of the respective logical operations are different.

On the other hand, at the time t7 during the fixed period of the input data DT, the synchronization signal
S0 stands up. As a result, the latch 5 latches the input data DT during the fixed period (hereinafter, simply referred to as “fixed input data DT”). After that, at time t2, input data DT
However, since the synchronization signal S0 maintains H, the latch output data S5 of the latch 5 remains unchanged from the value of the confirmed input data DT latched at the time t7 even after the time t2.

Therefore, the fixed period of the input data DT is from time t1 to t2.
Even in the period T1 of, the period during which the latch output signal S5 maintains the fixed input data DT is extended from the time t1 to the time when the synchronizing signal S0 falls. Along with this, the logical operation result
The definite period of L1 to L3 is also extended from the times t3, t4, and t5 in synchronization with the falling time of the synchronizing signal S0.

Then, at the time t9 during the finalization period of the logical operation results L1 to L3.
Then, the synchronizing signal delay circuit 4 raises the delayed synchronizing signal S0 'obtained by delaying the synchronizing signal S0 by time dt5. As a result, the time
At t9, the respective logical operation results L1 ′ to L3 ′ are flip-flop 3a.
Stored correctly in ~ 3c respectively.

As described above, the command register of the first embodiment is provided with the latch 5 between the input data DT and the synchronization signal SO and the combinational circuits 2a to 2c, and the input during the fixed period is performed based on the timing of the synchronization signal S0. Data DT is latched. Therefore, even if the fixed period of the input data DT becomes shorter, the output period of the fixed input data DT output from the latch 5 can be set longer, so that the fixed period of the input data can be shortened as the CPU becomes faster. Even if it is changed, the storage operation can be accurately performed.

Moreover, since it is not necessary to provide a delay circuit in each of the combinational circuits 1a to 1c as in the conventional case, the circuit configuration is simplified. The latch period of the latch 5 is the combinational circuits 1a to 1c.
If the delay time dt5 of the delay circuit 4 is set so that the delay synchronizing signal S0 'rises after the latest operation result output time, it may be set appropriately within a range that can include the deviation of the operation result output period between them. Since it is good, the timing control is easy.

In the command register of the first embodiment, the input data DT
It is premised that the synchronizing signal S0 rises during the fixing period of, and as shown in FIG. 4A, when the synchronizing signal S0 rises before the fixing period of the input data DT, or as shown in FIG. 4B. , Sync signal S0 after the fixed period of input data DT
The input data at the timing when the sync signal S0 does not rise during the fixed period of the input data DT, such as when
When DT and the synchronizing signal S0 are given, the definite input data DT is not latched in the latch 5, so that the latch 5 does not operate correctly.

FIG. 3 is a block diagram showing a command register which is a second embodiment of the present invention for solving the problem in the first embodiment. As shown in the figure, a delay circuit 6 is inserted between the input data DT and the latch 5, and the synchronization signal
A delay circuit 7 is inserted between S0 and the synchronization signal delay circuit 4 and the latch 5. The other structure is the same as that of the embodiment shown in FIG.

With such a configuration, in addition to the effect of the first embodiment, the input data DT and the synchronization at the timing when the synchronization signal S0 does not rise during the fixed period of the input data DT as shown in FIGS. 4A and 4B are provided. Even if the signal S0 is given, the delay circuit 6
By appropriately delaying the input data DT and the synchronizing signal S0 by means of 7 and 7, the timing can be corrected so that the delayed synchronizing signal S02 rises during the fixed period of the delayed input data DT2, as shown in FIG. .

Note that in these embodiments, the latch is shown as the storage means of the fixed input data DT, but other storage means such as a flip-flop may be used.

〔The invention's effect〕

As described above, according to the present invention, the first storage means stores the input data as latch data during the fixed period of the input data based on the timing of the synchronization signal, and the latch data is combined into a plurality of combinations. Each circuit performs a logical operation in parallel and outputs a logical operation result.

Therefore, the fixed period of the logical operation result of the plurality of combinational circuits becomes longer in proportion to the storage period of the latch data in the first storage means. As a result, even if the fixed period of the input data is shortened, by sufficiently lengthening the storage period of the latch data in the first storage means, the logical operation result can be included to the extent that the deviation of the logical operation delay time of each combinational circuit can be included. Since the fixed period can be set long, the storage operation can be performed accurately even when input data is fetched from the high-speed CPU.

In addition, since it is not necessary to provide a delay circuit for each combinational circuit as in the conventional case, the circuit configuration can be simplified. Further, the latch data storage period of the first storage means may be set so as to include the deviation of the logical operation delay time of each combinational circuit, and the delay time of the delay circuit is the slowest. Rises (falls)
Therefore, it is not necessary to perform strict timing setting, and timing control can be performed relatively easily.

[Brief description of drawings]

FIG. 1 is a block diagram showing a command register which is a first embodiment of the present invention, FIG. 2 is a timing diagram showing its operation, and FIG. 3 is a block showing a command register which is a second embodiment of the present invention. FIGS. 4A and 4B are timing charts showing the problems of the first embodiment, FIG. 5 is a timing chart showing the effects of the second embodiment, and FIG. 6 is a conventional command register. The block diagram shown in FIG. 7 is a timing chart showing the operation. In the figure, 1a to 1c are combinational circuits, 3a to 3c are flip-flops, 4 is a synchronizing signal delay circuit, 5 is a latch, and 6 and 7 are delay circuits. In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (1)

(57) [Claims] 1. A semiconductor memory device for storing a plurality of logical operation results obtained by fetching input data and a synchronization signal indicating a timing of a definite period of the input data and performing a plurality of types of logical operations on the input data. A first storage unit that stores the input data as latch data during a fixed period of the input data based on the timing of the synchronization signal, and is provided in parallel to the first storage unit. The first
A plurality of combination circuits that logically operate the latched data of the storage means and output the plurality of logical operation results, a delay circuit that delays the synchronization signal for a predetermined period and outputs a delayed synchronization signal, and the plurality of combinations A semiconductor memory device comprising: a plurality of second storage means provided corresponding to a circuit, and respectively storing the plurality of logical operation results at a timing based on the delay synchronization signal.