JPH06197009A - Counter with output latch function - Google Patents

Abstract

PURPOSE:To obtain a secured and warranted counted value regardless of timing by inputting a counter clock via a delay circuit to the counter with output latch function and allowing the latch to hold the counted value of the counter in the timing of a leading or trailing of the clock before delay. CONSTITUTION:The counter 100 with output latch function is provided with a delay circuit receiving a counter clock and delaying it by a prescribed time such as 6nsec and with a latch control circuit 15 for receiving the clock before delay and the latch signal received so far and outputting them to a latch 13. Thus, when an external counter clock C-CLK-0 is inputted to the circuit 14 asynchronous with a system clock S-CLK, the clock C-CLK-1 delayed by a prescribed time from the circuit 14 is inputted to a counter 12, which updates the count in each trailing timing. Thus, the circuit 15 outputs a prescribed latch signal LATCH 1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention counts the number of pulses of an input counter clock, latches and outputs the count value at that time according to a predetermined control signal input from the outside, and outputs the counter clock. Counting relates to a counter with an output latch function of the type that continues counting thereafter.

[0002]

2. Description of the Related Art FIG. 4 is a schematic diagram showing an example of a conventional counter with an output latch function. The output latch function counter 10 is used, for example, as a peripheral component of a CPU (central processing unit) of a computer, and operates in synchronization with a system clock used for the output latch function counter, the CPU, or the like. It is something to do.

First, an initial value is written in the initial value register 11 from a CPU (not shown), and the initial value is stored in the counter 1.
Loaded to 2. After that, a counter clock asynchronous with the system clock is input to the counter 12, and in this example, the count value of the counter 12 is updated at each falling timing of the counter clock. Further, the counter 10 with the output latch function is provided with a latch 13 that holds the count value of the counter 12.
Holds the count value of the counter 12 at the time of falling of a predetermined latch signal synchronized with the system clock. The count value held in the latch 13 is read by the CPU. Even while the count value is held in the latch 13, the counter 12 continues counting the counter clock.

When a plurality of counters are provided and each counter clock is independently input to each counter,
If these counters also do not have a latch function, and the CPU reads the count values of the counters, the counters are accessed in sequence and the count values are read in order. It is not possible to know the count value at the same time. On the other hand, since the output latch function counter 10 has a latch function, the same latch signal is input to the plurality of latch function counters to temporarily latch the count value at a predetermined same time. Then, by sequentially reading the latched count values, the count value at the same time can be known. Further, even in the case where it is necessary to know the count value of only one counter with the output latch function as described above,
For example, when the counter with the output latch function is a 16-bit counter system and the CPU connected thereto has an 8-bit specification, the upper byte of the count value,
The lower bytes have to be read sequentially, so that again only by using the latch function can the correct reading of the count value be guaranteed.

[0005]

As in the counter with the output latch function, the internal operation and the exchange of signals with the CPU are performed in synchronization with the system clock.
When the counter clock counted by the internal counter is asynchronous with the system clock, latch may occur at the moment when the counter clock pulse is input and the count value inside the counter is changed. In that case,
There is no guarantee that the latched count value is a correct count value, and there is a possibility that a completely random value may be latched.

The present invention solves this problem, and in a counter with an output latch function for inputting and counting a counter clock that is asynchronous with the system clock, no matter what timing the system clock occurs with respect to the counter clock. The purpose is to have the function of always latching the correct count value.

[0007]

A counter with an output latch function of the present invention which achieves the above-mentioned object is a counter for inputting a counter clock asynchronous with a system clock and counting the number of pulses of the counter clock. In a counter with an output latch function, which includes a latch that receives a predetermined control signal that is input and that holds the count value of the counter, the counter is arranged on the preceding stage side of the counter and delays the counter clock for a predetermined time to input the counter clock A delay circuit,
Latch that holds the count value of the counter in the latch at the timing of updating the count value of the counter of the counter clock before being input to the delay circuit after the predetermined timing in synchronization with the system clock and in response to the control signal. And a control circuit.

Here, the control signal is a concept including a predetermined command from the CPU when the counter with output latch function is configured as a peripheral component of the CPU, for example. Further, the "timing of updating the count value of the counter of the counter clock" means the timing of each rising edge of the counter clock if the counter captures and counts each rising edge of the counter clock. If it counts falling and counts, it means the timing of each falling.

[0009]

In the counter with output latch function of the present invention, the counter clock is input to the counter via the delay circuit,
The latch has a counter at the rising or falling timing of the counter clock before the delay depending on whether the counter updates the counting value at the rising edge of the counter clock or the falling edge. Since the count value is held, the guaranteed count value which is always fixed is latched regardless of the timing of the counter clock.

[0010]

EXAMPLES Examples of the present invention will be described below. FIG. 1 is a schematic configuration diagram of an embodiment of a counter with an output latch function of the present invention. The elements corresponding to the elements of the conventional example shown in FIG. 4 are given the same numbers as the numbers given in FIG. 4, and only the differences will be described.

A counter 10 with an output latch function shown in FIG.
To 0, the counter circuit is inputted, the delay circuit 14 for delaying the counter clock by a predetermined time such as 6 nsec, the counter clock before the delay and the latch signal as in the conventional example (FIG. 4) are inputted. A latch control circuit 15 for outputting the latch signal according to the present embodiment for storing the count value of 12 to the latch 13 is provided. The delay circuit 14 and the latch control circuit 15 will be described later.

FIG. 2 is a timing chart showing the operation of an embodiment of the counter with the output latch function. Predetermined write section WR synchronized with system clock S_CLK
The CPU issues a command to the output latch function counter to latch the count value of the counter, and then the CPU reads the latched count value in a predetermined read section RD sandwiching the idle section idle. And

At this time, inside the counter with the output latch function, a command latch signal C_LCH signal indicating that the command of the latch instruction from the CPU has been recognized is internally output after a delay from the predetermined write section WR, and the command is output. At the trailing end of the latch signal C_LCH, when the system clock S_CLK rises, the latch signal LATCH_0 instructing to latch the count value of the counter falls. This latch signal LATCH_0 is a conventional example (see FIG. 4).
In the present embodiment, the latch signal LATCH_0 is not used directly to latch the count value of the counter. Further, after a lapse of a predetermined reading section RD, a recognition signal R_AKN indicating that the reading of the latched count value is completed is internally output, and the system clock S_ at the rear end of the recognition signal R_AKN is output.
Latch signal LATCH_0 at the rising edge of CLK
Rises and the count value is unlatched.

On the other hand, the counter clock C_CL is externally supplied.
K_0 is input to the delay circuit 14 asynchronously with the system clock S_CLK, and the delay circuit 14 outputs the counter clock C_CLK_1 delayed by a predetermined delay time D. This delayed counter clock C_CL
K_1 is input to the counter 12, and the count value C is obtained at each falling timing of the counter clock C_CLK_1.
OUNT is updated. In addition, the conventional latch signal LAT
CH_0 and the counter clock C_CLK_0 before delay are input to the latch control circuit 15, and the latch control circuit 15 outputs a predetermined latch signal LATCH-1.

FIG. 3 is a circuit diagram showing the delay circuit 14 and the latch control circuit 15. The counter clock C_CLK_0 before the delay and the latch signal LATCH_0 are flip-flops 151 that constitute the latch control circuit 15.
Are input to the clock input terminal and the data input terminal, respectively. The latch signal LATCH_0 and the output signal of the flip-flop 151 are input to the OR gate 152. Therefore, the output signal LATCH of the OR gate 152
_1, the latch signal LATCH_0 is at the L level,
Further, it becomes a signal that falls at the time of the fall of the clock signal C_CLK_0 before delay. This OR gate 152
By inputting the output signal LATCH_1 (output signal of the latch control circuit 15) of the
The count value L_OUT stored in the counter represents the count value COUNT of the counter 12 that is guaranteed at that time.

[0016]

As described above, in the counter with the output latch function of the present invention, the counter clock is input to the counter via the delay circuit, and the counter updates the count value at the rising edge of the counter clock in the latch. The counter clock holds the count value of the counter at the rising or falling timing of the counter clock before the delay depending on whether the counter clock is updated or the count value is updated at the falling edge. The correct count value is always latched regardless of the timing with respect to the clock.

[Brief description of drawings]

FIG. 1 is a schematic configuration diagram of an embodiment of a counter with an output latch function of the present invention.

FIG. 2 is a timing chart showing the operation of an embodiment of the counter with an output latch function.

FIG. 3 is a circuit diagram showing a delay circuit and a latch control circuit.

FIG. 4 is a schematic configuration diagram showing an example of a conventional counter with an output latch function.

[Explanation of symbols]

 12 counter 13 latch 14 delay circuit 15 latch control circuit 151 flip-flop 152 or gate

Claims (1)

[Claims] 1. A counter for inputting a counter clock asynchronous with a system clock to count the number of pulses of the counter clock, and a latch for holding a count value of the counter by receiving a predetermined control signal input from the outside. In a counter with an output latch function comprising: a delay circuit arranged in front of the counter for delaying the counter clock by a predetermined time and inputting the counter clock to the counter; and a delay circuit synchronized with the system clock and responding to the control signal. A latch control circuit for holding the count value of the counter in the latch at the timing of updating the count value of the counter of the counter clock before being input to the delay circuit after a predetermined timing. A counter with an output latch function.