JPH0720142B2 - Serial interface circuit - Google Patents

Description

The present invention relates to a serial interface circuit, and more particularly to a clock synchronous serial interface circuit incorporated in a microcomputer.

[Conventional technology]

A typical block diagram of a conventional serial interface circuit of this type is shown in FIG. 3, and a timing chart during operation is shown in FIG.

As shown in FIG. 3, the conventional clock-synchronized serial interface circuit performs writing and reading of serial data input terminal 11 for inputting serial data from the outside, for example, transmission data and reception data of 8 bits, respectively. Shift register 12, serial data output latch circuit 13 that latches serial transmission data bit by bit, serial data output terminal 14 that outputs serial data to the outside, serial clock input / output terminal 15 that is an input / output terminal for transmission and reception clocks. , 3-bit serial clock counter 16 that counts the received serial clock, serial clock counter 16 counts 8 serial clocks, generates an interrupt signal 1a when it detects that it has overflowed, internal clock 1b Or external clock Serial clock control circuit 19 performs serial clock output of the clock selection circuit 18,8 shots for selecting a serial clock 1c and the internal bus,
Composed of 20.

The operation during serial data reception and transmission will be described with reference to FIG. Serial clock input / output pin during reception
Serial data from the serial data input terminal 11 in synchronization with the serial clock input from 15 (Fig. 4c)
DI ₀ to ₇ (1f in FIG. 4) are shifted bit by bit and loaded into the shift register 12. At the same time, when the serial clock counter 16 counts up to eight serial clocks, an overflow signal 1d is generated. Upon detecting this, the interrupt signal generation circuit 17 generates the interrupt signal 1a. When sending,
Serial data DO ₀ to ₇ written in the shifter register 12
(1g in FIG. 4) is output from the serial data output terminal 14 by shifting bit by bit in synchronization with the serial clock 1c output from the serial clock control circuit 19. When the serial clock counter 16 counts up to eight serial clocks 1c as in the reception, an overflow signal 1d is generated. Upon detecting this, the interrupt signal generation circuit 17 generates the interrupt signal 1a.

Central processing unit (hereinafter referred to as CPU) by interrupt signal 1a
Enters an interrupt processing routine, the CPU performs software processing such as reading the value of the shift register 12 via the internal bus 20 or writing data to the shift register 12, and then returns to the original instruction routine.

The above is a series of operations at the time of receiving and transmitting one frame of serial data in the microcomputer incorporating the conventional clock-synchronous serial interface.

[Problems to be Solved by the Invention]

Since the conventional clock-synchronous serial interface circuit described above has only one shift register as a register for storing serial data, when receiving serial data, it shifts before receiving the next serial data. The data in the register must be written to another register or memory. Further, when transmitting serial data, the data must be written in the shift register every time one frame of serial data is transmitted. Therefore,
An interrupt signal is generated each time reception or transmission of one frame of serial data is completed, and the CPU repeats the operation of entering write processing, performing predetermined software processing, and returning to the original instruction routine. Therefore, if the serial data is frequently transferred, there is a problem that the load on the CPU becomes large.

[Means for Solving the Problems]

The serial interface circuit of the present invention is a clock-synchronous serial interface circuit that transfers serial data in synchronization with a clock. In the serial interface circuit, a shift register that stores or transfers serial data in synchronization with the previous period clock and one period of the previous period clock are used. A first counter for counting and generating an overflow signal, a second counter for counting overflow of the first counter, a mode register for switching modes of receiving and transmitting serial data, and the second counter. Is used as an address to store the contents of the shift register at each overflow of the first counter at the time of reception, and at the time of transmission, the serial transmission data to be transferred from the shift register at each overflow of the first counter. Serial data storage cash register Data group, a register for setting the number of frames for transmitting or receiving serial data, the contents of this register and the count value of the second counter are compared, and a match signal is output when both numbers match. It comprises a circuit and an interrupt signal generating circuit which outputs an interrupt signal for notifying the central processing unit of completion of serial data transmission or reception of the number of frames set by the coincidence signal.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention. The clock synchronous serial interface circuit shown in FIG. 1 has a serial data input terminal 11, a shift register 12, a serial data output latch 13, a serial data output terminal 14, a serial clock input / output terminal 15, and a serial clock counter 1.
6, the interrupt signal generation circuit 17, the clock selection circuit 18, and the serial clock control circuit 19, in addition to the block configuration having the same functions as the components of the conventional clock synchronous serial interface circuit, Overflow counter 21, which counts the overflow signal generated each time the counting is completed, AND gate 2
2. It has a transfer frame number register 24 for storing the specified number of received or transmitted frames, a comparator 25 for comparing the contents of the overflow counter 21 and the transfer frame number register 24, and a serial data storage register group 23. This serial data storage register group 23 is read from the CPU via the internal bus 20 like a normal memory.
Light is also possible. In addition, the receive / transmit mode register 26 that switches between receive and transmit modes, transfers the contents of the shift register 12 to the serial data storage register group 23 at each overflow of the serial clock counter 16 at the time of reception, and overflows the serial clock counter 16 at the time of transmission. Control for transferring the serial data of the serial data storage register group 23 to the shift register 12 for each
It has a transmission control circuit 27.

Next, the operation at the time of receiving serial data in the above configuration will be described. Set the receive / transmit mode register 26 to receive mode and set the transfer frame number register 24 to "1" as an example.
Is written. The serial clock counter 16 counts eight serial clocks, and when the shift register 12 receives one frame of serial data, an overflow signal 1d is generated. Upon receiving this signal, the overflow counter 21 counts up and outputs the count value 1. The data taken into the shift register 12 is transferred to the addressed register of the serial data storage register group 23 using the count value of the overflow counter 21 as an address signal. Further, the comparator 25 compares the content of the received frame number register 24 with the count value of the overflow 21, and outputs a coincidence signal 2c when both numerical values match. The match signal 2c is input to the AND gate 22. Since the overflow signal 1d from the serial clock counter 16 is at high level, the AND gate 22 outputs high level, and the interrupt signal generating circuit 17 detects this and outputs the write signal 1aa. Therefore, when "1" is written in the transfer frame number register 24, this operation is repeated to generate an interrupt signal 1a each time one frame of serial data is received.
generate a. That is, in this case, the same operation as that of the conventional clock-synchronous serial interface circuit is performed to receive the serial data. The overflow counter 21 is cleared after the interrupt signal is generated.

Next, when a numerical value of 2 to n is written in the transfer frame number register 24, the comparator 25 compares the contents of the transfer frame number register 24 with the count value of the overflow counter 21 every time the overflow counter 21 counts, and overflows. The count value of the counter 21 is the transfer frame number register
When the numerical value of 24 is matched, a matching signal 2c is generated. Accordingly, the interrupt signal 1aa is output when the reception of the serial data of the number of frames equal to the content of the transfer frame number register 24 is completed. In addition, the serial reception data input to the shift register 12 is the serial clock counter.
The count value of 21 is used as an address signal and sequentially written into the addressed register of the serial data storage register group 23 at each overflow of the serial clock counter 16.

Similarly, the operation during serial data transmission in FIG. 1 will be described. In the serial data storage register group 23,
The transmission data of the number of frames designated in advance is written via the internal bus 20 by the write operation from the CPU. When the reception / transmission mode register 26 is set to the transmission mode, the transmission data written in the serial data storage register group 23 is controlled by the reception / transmission control register 27.
Addresses are specified by the contents of the overflow counter 21 and transferred from the serial data storage group 23 to the shift register 12. The serial data written in the shift register 12 is shifted bit by bit in synchronization with the serial clock, latched in the serial data output latch circuit 13, and output from the serial data output terminal 14 as transmission data. The serial clock counter 16 counts eight serial clocks as at the time of reception, and when the overflow signal 1d is generated upon completion of serial data transmission for one frame, the overflow counter 21 counts up and outputs the count value "1". . The comparator 25 compares the contents of the transfer frame number register 24 with the count value of the overflow counter 21, and when "1" is written in the transfer frame number register 24, both numbers match and the match signal 2c is output. Output. The coincidence signal 2c is input to the AND gate 22 together with the high level of the overflow signal 1d of the serial clock counter 16. This allows the interrupt signal generation circuit 17
Outputs interrupt signal 1aa. Therefore, when "1" is written in the transfer frame number register 24, the above operation is repeated to generate the interrupt signal 1aa each time one frame of serial data is received. That is, the same operation as the conventional clock-synchronized serial interface circuit is performed to transmit the serial data. On the other hand, when a numerical value of 2 to n is written in the transfer frame number register 24, the counter value of the overflow counter 21 and the transfer frame number register
When the value written in 24 matches, the comparator 25
Since the match signal 2c is output from the interrupt signal 1a, the interrupt signal 1aa is output when the transmission data of the serial data of the number of frames equal to the content of the transfer frame number register 24 is completed.

FIG. 2 is a timing chart in which the operation of the conventional clock-synchronous serial interface and the operation of the embodiment of FIG. 1 are compared. 2 (a) is a serial clock, FIG. 2 (b) is serial reception or transmission data,
2 (c) and 2 (d) are conventional interrupt signals, respectively.
1a and the operation of the CPU, FIGS. 2 (e) and (f) show the timing of the interrupt signal 1aa and the operation of the CPU of the embodiment of FIG. 1, respectively, and FIG. 2 (d) shows the reception of one frame. Alternatively, the CPU operates for each transmission, and the second
In the figure (f), the CPU operates once for receiving or transmitting n frames.

〔The invention's effect〕

As described above, the clock-synchronous serial interface circuit of the present invention sequentially stores the serial data of the number of frames equal to the set value of the register of the number of transfer frames in the serial data storage register at the time of reception and the serial data at the time of transmission. Since it has a circuit that can sequentially transfer the serial data written in the data storage register to the shift register, interrupt processing is performed on the CPU when the storage of the set number of received data or the transmission of the transmitted data is completed, The operation of reading the value of each serial data storage register or writing the data to the serial data storage register can be performed. Therefore, since it is possible to process a preset number of frames of serial data in one interrupt process, pre-processing and post-processing for interrupt processing are reduced, and it is possible to reduce the load on the CPU. is there.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a timing chart comparing a conventional serial interface circuit with an embodiment of the present invention, and FIG. 3 is a typical conventional serial interface circuit. FIG. 4 is a timing chart of the operation of the block diagram of FIG. 11 …… Serial data input terminal, 12 …… Shift register, 13 …… Serial data output latch circuit, 14 …… Serial data output terminal, 15 …… Serial clock input / output terminal, 16 …… Serial clock counter, 17 …… Interrupt signal generation circuit, 18 ... Clock selection circuit, 19 ... Serial clock control circuit, 20 ... Internal bus, 21 ... Overflow counter, 22 ... AND gate, 23 ... Serial data storage register group, 24 ... Transfer Frame number register, 25 ……
Comparator, 26 ...... Reception / transmission mode register, 27 ...
... Reception / transmission control circuit.

Claims (1)

[Claims] 1. A clock-synchronous serial interface circuit for transferring serial data in synchronization with a clock, wherein a shift register for storing or transferring serial data in synchronization with the previous clock and a previous clock for one frame are counted. A first counter that generates an overflow signal, a second counter that counts the overflow of the first counter, a mode register that switches the mode of serial data reception and transmission, and a count value of the second counter. Is used as an address, the content of the shift register is stored at each overflow of the first counter at the time of reception, and the serial transmission data to be transferred from the shift register at the time of overflow of the first counter is stored at the time of transmission. Data storage register group,
A register for setting the number of frames for transmitting or receiving serial data, a comparator circuit for comparing the contents of this register with the count value of the second counter and outputting a match signal when both numbers match, A serial interface circuit, comprising: an interrupt signal generation circuit that outputs an interrupt signal that notifies the central processing unit of completion of serial data transmission or reception of the number of frames set by the coincidence signal.