JPH01232420A - Stack device for data - Google Patents

Abstract

PURPOSE:To output immediate data which is inputted first and to simplify the constitution of a circuit by composing the stack device of a stack part which is provided with latch devices in plural stages and stacks plural data and a stack control part. CONSTITUTION:The stack part 10 consists of the latch devices 11-1-11-n provided in the plural stages, and the stack control part 12 latches data so that the data are held in order from the final stage of the latch device 11-1 to front stages and places latch devices before the latch device in a passing stage. First data, i.e. data No.1 is passed through the latches 11-n-11-2 and held by the latch 11-1, data No.2 which is inputted next is held by the latch 11-2, and data No.3 is held by the latch 11-3. Then when the latch 11-1 outputs the data No.1, the data No.2 is held by the latch 11-1 and the data No.3 is held by the latch 11-2. Consequently, the data which is inputted first is outputted immediately and the circuit constitution is simplified.

Description

[Detailed Description of the Invention] [Summary] It relates to a data stacking device, in particular a FIFO method (FIFO method).
Regarding the data stacking device that adopts rst In First 0ut), the purpose of the data stacking device is to be able to output the first input data immediately and to simplify the circuit configuration. Latch devices that can select between a holding state that holds data consisting of multiple bits and a passing state that allows data to pass are installed in multiple stages.There is a stack section that stacks multiple pieces of data, and the data is sequentially transferred from the last stage latch device to the previous stage. and a stack control unit that puts a latch device at a stage preceding a latch device that latches data so that it is held in a passing state.

[Industrial application field]

The present invention relates to a data stacking device, and particularly to a FIFO stacking device.
The present invention relates to a data stacking device that adopts a first-in-first-out method.

[Conventional technology]

-a The data stacking device described above is used when rewriting the cache memory, etc., as shown in Figure 6, and it stacks input data and outputs the data in the order in which it was input. It is something. In the same figure,
1 is a stack device for stacking addresses; 2 is a microprocessor; 3 is a cache memory consisting of a TAG unit 4 and 5-RAM 5; 6 is a DMA control unit; 7 is a memory;
8 is a DV/RV section.

As shown in FIG. 7, such a data stacking device has conventionally constructed a -stage flip-flop array with a number of flip-flops (FF1t to FF□8) that corresponds to the number of required data bits. , this solve flop array is provided with n stages necessary for a stack.

In this example, the data to be stacked is 8 bits, and is stacked over n stages as described above. The input data is shifted one stage at a time according to the input clock signal, and the data shifted to the nth stage is output from the data stack device.

[Problems to be Solved by the Invention] In the data stacking device as described above, the data input to the stacking device is shifted one after another, and is output from the stacking device after passing through the n-th stage. That is, there is a problem in that the signal is not output until n+1 clock cycles after input.

Further, in the conventional data stacking device described above, there is a problem in that when the data bit width increases or the number of stack stages increases, the number of required flip-flops becomes enormous.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a data stacking device that can immediately output data that is first input and that can simplify the circuit configuration.

[Means to solve the problem]

In the present invention, means for solving the above problems are as follows:
As shown in FIG. 1, latch devices 11-1 to 11 can select a data stacking device between a holding state in which data consisting of a plurality of bits is held and a passing state in which data is passed.
-n in multiple stages and stacks a plurality of data, and a latch device in the previous stage from the latch device that latches data so that the data is sequentially held from the final stage latch device 11-□ to the previous stage. It is composed of a stack control unit 12 which sets the passage state.

(Function) According to the present invention, since the stack section is constituted by latch devices provided in multiple stages, the structure of the device can be simplified, and as shown in FIG. Since the latch devices at the previous stage are put into a passing state from the latch device that latches the data so that the data is held sequentially from the last stage latch device to the previous stage, the input data is quickly output. For example, if we input four data, the first data is data N001.
passes from the latch device 11-n which is in the passing state to the latch device 11-2, and is held by the latch 11-1 (1). Thereafter, input data No. 2 is held in the latch device 11-2, and similarly, data No. 3 is held in the latch device 11-3 (2).

Then, when the latch device 11-1 outputs data N001, data No. 2 from the latch device 11-2 is held in the latch device 11-1, and similarly, when the latch device 11-2 outputs data No. 2, the latch device 11-2 holds data No. 2 from the latch device 11-2. Data No. 3 from the device 11-3 is held in the latch device 11-2 (3), and the same processing continues (4).

(Embodiment) Hereinafter, an embodiment of a data stacking device according to the present invention will be described based on the drawings.

3 to 5 show an embodiment of a data stacking device according to the present invention. In this embodiment, the input data consists of 8 bits DO to D7.

The stack section that holds this data has four stages of latch devices (latch devices A to latch devices D) 21, 22, 2.
It is set at 3.24.

These latching devices then receive an input request signal (IN-RE
Q) and output completion signal (OUT-END) to generate four types of clock signals (clock A to clock D) that control the operation of the four stack devices described above. . These clock signals are logically summed with the system clock (SCLK) by respective OR gates 25, 26, 27.degree. 28 and inputted.

In this embodiment, the stack control section 29 has a structure as shown in FIG. In the same figure, 31, 32,
33.34 is JK that generates clock A to clock D
Flip-flops 35, 36, and 37 are used to logically AND the outputs of the Q terminals of the JK flip-flops 31, 32, and 33 in the upper stage and the Q terminals of the JK flip-flops 32, 33, and 34 in their own stage. 32°33.3
4, an AND gate 38 inputs the input request signal (IN-REQ) and the output of the Q terminal of the JK flip-flop 31 in the first stage to the J terminal of the JK flip-flop 31 in the first stage. OR gate to output, 39, 40
．． 41 is the input request signal and the upper stage JK flip-flop 3
1° 32.33 is an AND gate that generates the AND of the Q terminal output, 42.43 is the above AND gate 39.40
and the output of the Q terminal of the JK flip-flop 33, 34 in the next stage are logically summed.
This is an OR gate that outputs to the J terminal of 33. and each J
A system clock signal is input to the K flip-flops 31, 3233, and 34.

Next, the operation of the data stacking device according to the present embodiment will be explained. FIG. 5 is a time chart showing the operation of the embodiment of the data stacking device according to the present invention. In this example, there is a request to write 4 bytes of data to the stack device, and 2 bytes of data are output during that time.

First, there is a first input request signal (■), and clock A rises for latch device A (■). At this time,
The clock signal does not rise to the other latch devices, and the latch device B, latch device C, and latch device A are in a passing state, and the first data passes through these latch devices and is sent to latch device A. Retained. When the second input request signal is received in this state (■), the clock B for the latch device B rises (■). As a result, the second data passes through the latch device C and the device 1 and is held in the latch device B. Similarly, when there is a third write request (■), clock C rises (
0) The third data is held in latch device C.

When the output of the first data is completed, a read completion signal (OUT-END) is input to the stack control unit (
@), clock A is reset. As a result, the latch device A enters the passing state, and at this time, the second data is held and the clock B is in the rising state, so the clock A rises (■), and the JK flip-flop is set again, and the latch device A holds the second data. Then, clock B is reset and latch device B
is in a passing state, but since the third data is held in the latch device C and the clock C is in a rising state, the clock B rises again (■) and the third data is held. At this time, the latch device C enters the pass state again, and after that, when the second data is output from the latch circuit A, an output completion signal is input to the stack control section (@
), the clock A is similarly reset, the third data is shifted from the latch device B and held in the latch device A, and the third data output operation begins. During this time, when the input request signal is input again (■), the fourth data is held in the latch device B because only the latch device A is in the holding state at that time. Thereafter, data is held or output in the same manner, and the data stacking device operates.

Therefore, according to this embodiment, since the first input data is held in the final stage latch device A at the first timing, this data can be output quickly and the bit width of the data can be increased. Even if the number of data holding stages is increased, the number of flip-flops used will not increase significantly and the configuration will not become complicated.

〔Effect of the invention〕

As explained above, according to the present invention, a data stacking device is provided with latch devices in multiple stages capable of selecting a holding state in which data consisting of a plurality of bits is held and a passing state in which data is passed, and a plurality of data is stacked. Since it is composed of a stack unit and a stack control unit that puts the latch device in the previous stage to the passing state from the latch device that latches data so that the data is held sequentially from the last stage latch device to the previous stage, the first Since the input data is held in the final stage latch device at the first timing, the first input data can be output immediately, and even if the data bit width is increased, the number of data retention stages can also be increased. Even if this is done, the number of flip-flops used does not increase much, so the effect is that the circuit configuration can be simplified.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the principle of the present invention, FIG. 2 is a diagram showing the operating state of the present invention, FIG. 3 is a diagram showing an embodiment of the data stacking device according to the present invention, and FIG. 5 is a diagram showing the configuration of the stack control unit of the data stacking device shown in FIG. 3; FIG. 5 is a diagram showing the operation of the data stacking device shown in FIG. 3;
Fig. 6 is a diagram showing a system using a stack device, Fig. 7
The figure shows a conventional data stacking device. 10... Latch unit 11-8 to 11-n... Latch device 12... Stack control unit

Claims (1)

[Claims] A latch device (11
_-_1 to 11_-_n) are provided in multiple stages to stack a plurality of data. A data stacking device characterized by comprising a stacking control unit (12) that sets a latch device at a stage preceding a latch device to be latched to a passing state.