JP2561308B2 - Data stacking device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Outline] The present invention relates to a data stack device, and particularly to a FIFO system (First
Regarding the data stacking device that employs (In First Out), the first data input can be output immediately and the circuit configuration can be simplified so that the data stacking device has multiple bits. A latch unit that can select a holding state for holding data and a passing state for passing data is provided in a plurality of stages, and a stack unit for stacking a plurality of data, and data is sequentially held from the final stage latch device toward the front stage. As described above, a stack control unit that puts the latch device in the preceding stage into the passing state of the latch device that latches the data.

[Industrial applications]

The present invention relates to a data stack device, and more particularly to a data stack device that employs a FIFO method (First In First Out).

[Conventional technology]

Generally, the data stacking device as described above is used when rewriting the cache memory as shown in FIG. 6, and stacks input data and outputs the data in the order in which they are input. is there. In the figure, 1 is a stack device for stacking addresses, 2 is a microprocessor, 3 is a cache memory consisting of a TAG unit 4 and S-RAM 5, 6 is a DMA control unit, 7 is memory, and 8 is D.
It is the V / RV section.

Conventionally, such a data stacking device, as shown in FIG. 7, comprises a single-stage flip-flop array with a number of flip-flops (FF _{11 to} FF ₁₈ ) matching the required number of bits of data. This flip-flop array is provided with the necessary n stages in the stack.

In this example, the data to be stacked is 8 bits, and this is stacked over n stages as described above. The data input by the input clock signal is shifted one stage at a time, and the data shifted to the nth stage is output from the data stack device.

[Problems to be Solved by the Invention]

By the way, in the data stacking apparatus as described above, the data input to the stacking apparatus is shifted one after another, and is output from the stacking apparatus after the nth stage.
That is, there is a problem that the data is not output until after n + 1 clock cycles from the input.

Further, in the above-described conventional data stack device, if the data bit width is increased or the number of stack stages is increased, the number of required flip-flops becomes enormous.

Therefore, an object of the present invention is to provide a data stacking device that can immediately output the first input data and can simplify the circuit configuration.

[Means for solving the problem]

In the present invention, as a means for solving the above problems, as shown in FIG. 1, a stacking device for data selects a holding state for holding data of a plurality of bits and a passing state for passing data. Latch device 11 _{-1 to} 11 _-n
Stack section that stacks multiple data by providing multiple stages
10 and a stack control unit 12 that puts the latch device in the preceding stage into a passing state from the latch device that latches the data so that the latch device 11 _{-1 in the} final stage sequentially holds the data toward the preceding stage. .

[Action]

According to the present invention, since the stack unit is composed of the latch devices provided in a plurality of stages, the structure of the device can be simplified, and as shown in FIG. The latch device that latches data so that the data is latched sequentially from the latch device to the latch device in the preceding stage is brought into the passing state, so that the input data can be output quickly. For example, in the case of inputting four data, the first data, the data No. 1 is from the latch device 11 _{-n in the} passing state to the latch device 11
_It passes through _-2 and is held in the latch 11 _-1 (1). The data No. 2 input thereafter is held in the latch device 11 _-2 , and similarly the data No. 3 is held in the latch device 11 _-3 (2).
When the latch device 11 _-1 outputs the data No. 1, the latch device 11 _-2 holds the data No. 2 in the latch device 11 _-1 , and similarly when the latch device 11 _-2 outputs the data No. 2. ,
The data No. ₃ from the latch device 11 _-3 is held in the latch device 11 _-2 (3) and the same processing continues (4).

〔Example〕

An embodiment of a data stacking device according to the present invention will be described below with reference to the drawings.

3 to 5 show an embodiment of the data stacking apparatus according to the present invention. In this embodiment, the input data is 8 bits and is composed of D0 to D7. The stack unit for holding this data is a four-stage latch device (latch device A to latch device D) 21, 22, 23, 24.

Then, these latch devices have input request signals (IN-RE
Q) and an output completion signal (OUT-END) to control the stack control unit 29 which generates four clock signals (clock A to clock D) for controlling the operation of the above four stack devices. . These clock signals are sent to the system clock (SCL) at the respective OR gates 25, 26, 27 and 28.
K) and the logical sum is input.

In this embodiment, the stack controller 29 has a structure as shown in FIG. In the figure, 31,32,33,34
Is a JK flip-flop that generates clock A to clock D, and 35, 36 and 37 are the outputs of the terminals of the upper JK flip-flops 31, 32 and 33 and the Q of the own JK flip-flops 32, 33 and 34.
The logical product of the outputs of the terminals is used to calculate the JK flip-flops 32, 33,
An AND gate is input to the K terminal of 34, and 38 is an input request signal (IN-REQ) and the logical sum of the output of the Q terminal of the JK flip-flop 31 of the first stage to the J of the JK flip-flop 31 of the first stage.
OR gates output to the terminals, 39, 40, 41 are AND gates for generating a logical product of the input request signal and the outputs of the Q terminals of the upper JK flip-flops 31, 32, 33, 42, 43 are the AND gates 39, Output of 40 and Q of JK flip-flops 33 and 34 in the next stage
The logical sum of the output of the terminal is the JK flip-flop 32, 33
It is an OR gate that outputs to the J terminal. A system clock signal is input to each JK flip-flop 31,3233,34.

Next, the operation of the embodiment of the data stacking apparatus according to the present embodiment will be described. FIG. 5 is a time chart showing the operation of the embodiment of the data stacking apparatus according to the present invention. In this example, there is shown a case in which a 4-byte data write request is issued to the stack device and 2-byte data is output during the write request.

First, there is the first input request signal (), and the clock A rises to the latch device A (). At this time, the clock signal does not rise to the other latch devices, and the latch devices B, C and D are in the passing state, and the first data passes through these latch devices and is latched. Held in device A. Then, when there is the second input request signal in this state (), the clock B rises to the latch device B this time (). As a result, similarly, the second data passes through the latch devices C and D and is held in the latch device B. Similarly, when there is a third write request (), the clock C rises () and the third data is held in the latch device C.

When the output of the first data is completed, the read completion signal (OUT-END) is input to the stack control unit (), and the clock A is reset. As a result, the latch device A is brought into the passing state, and at this time, the second data is held and the clock B is in the rising state, so the clock A rises and the JK flip-flop is set again, and the latch device A becomes Holds the second data. Then, the clock B is reset and the latch device B
However, since the latch device C holds the third data and the clock C has risen, the clock B rises again () and the third data is held. At this time, the latch device C is in the passing state again, and when the second data is then output from the latch circuit A, the output completion signal is input to the stack control unit (), and the clock A is similarly reset, and the third data is output. Data is shifted from the latch device B and held in the latch device A, and the third data output operation is started. During this period, when the input request signal is input again (), only the latch device A is in the holding state at that time, so the fourth data is held in the latch device B. Similarly, data is held and output, and the data stacking device operates.

Therefore, according to the present embodiment, since the first input data is held in the final stage latch device A at the first timing, it is possible to output this data quickly.
Even if the data bit width is increased or the number of data holding stages is increased, the number of flip-flops to be used does not increase so much and the configuration is not complicated.

〔The invention's effect〕

As described above, according to the present invention, the data stacking device is provided with a plurality of latch devices capable of selecting a holding state for holding data of a plurality of bits and a passing state for passing data, and stacks a plurality of data. Since the stack unit and the stack control unit that puts the latch device in the preceding stage of the latch device that latches the data so that the data is sequentially held from the latch device in the final stage toward the preceding stage, The data input to is held in the latch device at the final stage at the first timing, the first input data can be output immediately, and the number of data holding stages is increased even if the bit width of the data is increased. Even if you do so, the number of flip-flops used does not increase so much, so the effect that the circuit configuration can be simplified To.

[Brief description of drawings]

FIG. 1 is a principle diagram of the present invention, FIG. 2 is a diagram showing an operating state of the present invention, FIG. 3 is a diagram showing an embodiment of a data stacking device according to the present invention, and FIG. 4 is FIG. FIG. 5 is a diagram showing a configuration of a stack control unit of the data stacking device shown in FIG. 5, FIG. 5 is a diagram showing an operation of the data stacking device shown in FIG.
FIG. 6 is a diagram showing a system using a stack device, and FIG.
The figure shows a conventional data stacking device. 10 …… Latch section 11 _{-1 to} 11 _-n … Latch device 12 …… Stack control section

Claims (1)

(57) [Claims] 1. A stack unit for stacking a plurality of data by providing a plurality of latch devices (11 _{-1 to} 11 _-n ) capable of selecting a holding state for holding data consisting of a plurality of bits and a passing state for passing the data. (10) and a stack control unit (1) that puts the latch device in the preceding stage into a passing state from the latch device that latches the data so that the data is sequentially held from the latch device (11 _-1 ) in the final stage toward the preceding stage.
2) Data stacking device characterized by consisting of