JPS61190389A - Character display unit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a display device such as a terminal of an information processing device or a personal computer, and particularly relates to a character display device that performs attribute control.

[Conventional technology]

Conventionally, this type of display device has been known to have a configuration as shown in FIG. This display device consists of a display control circuit 1 that controls the entire display device, a screen memory 2 that stores character codes, a character generator memory 3 that stores character patterns, a screen memory 4 that stores attribute codes, and a character generator memory 3. It has a timing conversion circuit 7 that converts the read character pattern in accordance with the timing of the display.

Display addresses are generated from control circuit 1 and input to screen memories 2 and 4 via address bus 6. The character code read from the screen memory 2 according to the display address is latched by the register 5 and becomes the address of the character generator memory 3. The character pattern read from the character generator memory is converted into a signal passed to the display by the timing conversion circuit 7. is converted to In this case, since the display is a CRT (cathode ray tube) 11, the timing conversion circuit 7 converts multiple bits of parallel data into one serial
Convert to bit data. The converted data is input to the attribute synthesis circuit 16 which is composed of a combination of gate circuits (AND circuit, OR circuit, 808 circuit).

On the other hand, the attribute code read out from the screen memory 4 according to the display address is input to the attribute synthesis circuit 16 via the attribute code signal line 14 after adjusting the timing with the character pattern in the register 8.9.

In this display device, each character is assigned an 8-bit code, and the attribute functions are green, blue, red, overline, underline, reverse, blinking, and secret, depending on the bit. The control signal line 13 from the display control circuit 1 is a control signal line necessary for attribute control. For example, 13a is a signal line that generates the timing to output an overline, and the overline bit in the attribute code is an AND circuit. 1 after being gated by 15. OR circuit 1
7 is ored to the character pattern. Below, control signal line 13
To explain only the functions, 13b is an underline timing signal line, 13C is a cursor display signal line, and 13d is
is a signal line indicating the blinking interval of the blinking display.

The green, red, and blue signals to which attribute control has been added, which are output from the attribute synthesis circuit 16, are sent to the drive circuit 10, and are also sent from the display control circuit 1 to the synchronization signal line 12.
The signal is supplied to the CRTII along with the synchronization signal sent via the synchronous signal, and drives the CRTII.

[Problem that the invention seeks to solve]

As explained above, in conventional character display devices, attribute synthesis circuits can be realized by combining simple gate circuits, but on the other hand, the attributes of the characters that are finally displayed depend on how the gate circuits are combined. It will change a lot. For example, even if the same gate circuits are used, simply changing the order of the gate circuits will result in completely different attributes being displayed.

In the conventional character display device described above, the attribute synthesis circuit is a wiring circuit consisting of a combination of gate circuits, so the specifications of the attributes are fixed at the time of circuit design.
Subsequent changes are not easy.

Furthermore, the character display device is an important part of the user interface, and even a slight difference in attributes can have a large impact on the user and the software. Therefore, it is very difficult to change the attributes of a character display device once it has been shipped, and there are several types of character display devices that have been shipped.
This has been a major obstacle in standardizing character display devices.

[Means for solving problems]

An object of the present invention is to provide a character display device that solves the above-mentioned drawbacks.

The character display device of the present invention includes a display control circuit, a character code screen memory into which addresses are input from the display control circuit, and a character generator memory whose addresses are character codes read from the character code screen memory.
an attribute code screen memory into which an address is input from the display control circuit; a memory whose address is the attribute code read from the attribute code screen memory and a control signal from the display control circuit; and a memory read from the character generator memory. an arithmetic circuit that controls the character pattern in bit units based on the data read from the memory; a timing conversion circuit that converts the output of the arithmetic circuit in accordance with the timing of the display; and an attribute of the memory. The display device is characterized by comprising a logic circuit that gates the controlled data using the output of the timing conversion circuit and inputs the gated data to the display drive circuit.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention. In FIG. 1, a display control circuit 1, a screen memory 2 for storing character codes, a character generator memory 3, a screen memory 4 for storing attribute codes, and registers 5, 8, and 9 are shown.
, the drive circuit 10, the CRT II, the synchronization signal line 12, the control signal line 13, and the attribute code signal line 14 are the same as those shown in FIG. The character display device includes a register 18 that latches the character pattern read from the character generator memory 3, a memory 9 that outputs data using an attribute code signal line 14 and a display control signal line 13 necessary for attributes as addresses. Arithmetic circuits 21a, 21b, . . . , 21h that control character patterns in 1-bit units according to the state of the data line 20 of this memory, and a timing conversion circuit 22 that converts the outputs of these arithmetic circuits in accordance with the timing of the CRTII. , memo I71
a logic circuit 24 consisting of a register 23 that latches the data on the data lines 20 of the green, red, and blue signals of 9; and an AND circuit that gates the output of this register with the output of the timing conversion circuit 22 and supplies it to the drive circuit 10; and central processing unit 2
It further includes a memory change circuit 26 for changing the contents of the memory 19 in response to instructions from the memory 19.

A specific configuration of the arithmetic circuits 21a, 21b, . . . , 21h is shown in FIG. FIG. 2 shows an example in which each arithmetic circuit is composed of a four-person multiplexer 27.

Depending on the values of the input signal lines 28 and 29 from the memory 19, the output line 30 is configured to output the same value, the inverted value, always O, or always 1 of the input pattern from the character generator memory 3. .

In the character display device described above, by writing predetermined data into the memory 19 in advance, logic equivalent to the connection circuit of the attribute synthesis circuit 16 in the conventional character display device shown in FIG. 4 can be realized. . In the case of this embodiment, assuming that the attribute code is 8 bits and the number of control signal lines is 4, the number of addresses in the memory 19 is 12.

In addition, since the character pattern is read in 8-bit parallel, the data line 20 of the memory is connected to 16 bits in order to convert the character pattern.
The book and three inputs to the logic circuit 24 make a total of 19, and the capacity of the memo I719 is 76 Kbit.

Next, a detailed example of the memory change circuit 26 will be explained with reference to FIG. This memory changing circuit is a control signal generating circuit 3.
1 and tri-state gates 32° and 33. The control signal generation circuit 31 is a circuit that receives a memory change command from the central processing unit 25 and generates control signals for the write slope and dry state gates 32 and 33 for the memory chip 19. tristate gate 32.33
The address line and data line of the central processing unit 25 are connected to the input of the central processing unit 25, and the tri-state gates 32 and 33 are open during the memory change command of the central processing unit 25, and the address line of the central processing unit is input to the memory 19. , data is supplied. At this time, control signal line 13. The attribute code signal line 14 needs to be in a high impedance state, but in this embodiment, the register 91 display control circuit 1
creates a high impedance state by controlling the signal line 34 from the control signal generating circuit 31. In this way, the contents of the memory 19 can be freely changed by commands from the central processing unit 25.

In the character display device described above, when a display address is generated from the display control circuit 1, this display address is input to the screen memories 2 and 4. The character code read from the screen memory 2 according to the display address is loaded in the register 5 and becomes the address of the character generator memory 3. Each bit of the character pattern read from the character generator memory is sent via the register 18 to arithmetic circuits 21a, 21b, -, and 21h, respectively.

On the other hand, the attribute code sequentially outputted from the screen memory 4 according to the display address is input to the memory 19 via the attribute code signal line 14 after adjusting the timing with the character pattern in the register 8.9. Further, from the control circuit 1, signals necessary for attribute control are input to the memory 19 via the display control signal line 13. The memory reads the stored data using the attribute code signal line 14 and the display control signal line 13 as addresses, and outputs it to the data line 20. Among these data, the data necessary for converting the character pattern is the arithmetic circuit 21a,
21b, -, and 21h, each arithmetic circuit converts the character pattern from the character generator memory 3 into one character pattern.
Control bit by bit. The output of each arithmetic circuit is input to a timing conversion circuit 22, where it is converted into a signal suitable for a display device. In this case, since the display is a CRT, the timing conversion circuit 22 converts multiple bits of parallel data into serial 1-bit data. The converted data is input to the logic circuit 24, which gates the attribute-controlled green, red, and blue signals input from the read-only memory 19 via the C dimeta 23 and input them to the drive circuit 10. Let it be, CR
Drives Tll.

In the above embodiments, the case where the display device is a CRT has been described, but the present invention is not limited to the CRT, and it goes without saying that the present invention can be implemented with a liquid crystal display, a plasma display, and the like.

〔Effect of the invention〕

As explained above, the present invention makes it easier to change attribute functions by changing the attribute synthesis circuit, which was conventionally realized by a wiring circuit, to a programmable system using a memory that can be changed from a central processing unit. Even if the type of character display device is different and the function of the attribute is different, various attributes can be realized by changing only the memory, which has the effect of improving the efficiency of device design.

Furthermore, since the central processing unit can change the attributes at any time, it is possible to simulate between models with different attributes.

[Brief explanation of the drawing]

1 is a configuration diagram of an example of the present invention; FIG. 2 is a configuration diagram of an example of the arithmetic circuit of FIG. 1; FIG. 3 is a configuration diagram of an example of the memory change circuit of FIG. 1; The figure is a configuration diagram of a conventional device. 1...Display control circuit 2...Character code screen memory 3...Character generator memory 4...
・Attribute code screen memory 5.8, 9.18.
23...Register 6...Address bus line 7.22...Timing conversion circuit 10...Drive circuit 11...CRT 12...Synchronization signal line 13...Control signal line 14... Attribute code signal line 15...
AND circuit 16...Attribute synthesis circuit 17...OR circuit 19...Memory 20...Memory data line 21...Arithmetic circuit 24...Logic circuit 25... Central processing unit 26...Memory change circuit 27...Multiplexer 31...Control signal generation circuit

Claims (1)

[Claims] (1) A display control circuit, a character code screen memory into which an address is input from the display control circuit, a character generator memory whose address is the character code read from the character code screen memory, and an address from the display control circuit. an attribute code screen memory into which is input, a memory whose address is the attribute code read from the attribute code screen memory and a control signal from the display control circuit, and a character pattern read from the character generator memory; an arithmetic circuit that controls bit by bit based on the data read from the memory; a timing conversion circuit that converts the output of the arithmetic circuit in accordance with the timing of the display device; 1. A character display device comprising: a logic circuit that gates the output of a timing conversion circuit and inputs it to a display drive circuit; and a memory change circuit that changes the contents of the memory based on a command from a central processing unit.