KR950005229B1 - Address generator - Google Patents

Abstract

The generator reduces the CPU burden and improves the VGA chip performance by hardware realization of VGA chip through video BIOS. The generator includes a page register (1) which writes the accessed page, an address generator (2) which outputs the starting address signal, the 1st and 2nd X position registers (3,4), the 1st and 2nd Y position registers (5,6), the 1st adder(7) which outputs 20 bit output signal, a multiplier (8) which outputs 20 bit output signal, a mode type column division register (9), the 1st and 2nd latches(10,11), the 2nd multiplier (12), the 3rd latch(13), and the display memory access address generator(14).

Description

Actual address generator for text generation in graphical mode

1 is a block diagram according to the present invention.

2 is an address generation circuit diagram.

3 is an internal configuration diagram of a page size register.

4 is a detailed block diagram of a start address unit.

5 is a configuration diagram of a display memory access address generator.

* Explanation of symbols for main parts of the drawings

1: page register 2: address generator

3,4: X position register 5,6: Y position register

7, 12: adder 8: multiplier

9: Mode Decomposition Register 10,11,13: Latch

14: display memory access address generator 15: clock generator

The present invention relates to a real address generator applied to a high performance graphics controller.

The graphics mode operation using the existing AGA chip creates a real pixel address through the video basic input / output system (hereinafter referred to as BIOS), sets the corresponding VGA register for the operating environment, and then converts the pixel color to the graphic display controller of the VGA. The display memory is accessed via GDC). This is the video BIOS function pixel light (hereinafter referred to as OCH), the video BIOS function pixel read (hereinafter referred to as ODH).

In the case of an active cursor, the actual cursor position is calculated by the BIOS and the CRTC Indexed E and F registers are updated to control the cursor. There are many routines for creating a real pixel position and a routine for creating a real characteristic position (per display memory access). As a result, the CPU load is a large part, and there is a problem that the VGA chip performance is degraded.

In order to solve the above problems, the present invention provides a physical address generator that hardware implements a software putin such as an actual characteristic position routine, an actual pixel position routine, a routine for accessing a CRTC register after creating an active cursor position, and the like. There is a purpose.

In order to achieve the above object, the present invention provides a page register means for writing a page to access a display memory in the BIOS with an 8-bit register, a page register means for connecting the page register means and a graphic display control register signal externally. Address generation means for outputting a page start address signal for each mode by receiving a signal, and first and second X position register means for writing in a BIOS as a 16-bit register for an X position of a cursor or pixel upon receiving a graphic enable signal, and graphic in First and second Y position register means, 16 bit registers for Y position of cursor or pixel, 20 bit signal from the address generating means and 16 bit signal from the first and second X position register means First outputting a 20-bit output after receiving and adding Multiplication means for receiving a 16-bit signal from the adding means, the first and second Y-position register means, and outputting a 20-bit output signal, and a mode-specific thermal decomposition register that writes a thermal decomposition value for each mode in the video BIOS and applies it to the multiplier. Means, the first and second latches latched by an applied clock after receiving the output signal from the first adding means and the ascending means, and a second applying and adding the output signals from the first and second latches. Addition means, a third latch used for cursor control when having actual X and Y position addresses for graphic acceleration, and display memory access address generating means for generating according to the display memory usage type.

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

1 is a block diagram according to the present invention, in which 1 is a page register, 2 is an address generator, 3 and 4 are X position registers, 5 and 6 are Y position registers, 7, 12 is an adder, 8 is a multiplier, 9 represents mode-specific thermal decomposition registers, 10, 11, and 13 latches, 14 represents a display memory access address generator, and 15 represents a clock generator.

As shown in the figure, the page register 1 is an 8-bit register that writes the page value, i.e., the page in the BIOS, to access the display memory.

The address generator 2 is connected to the page register 1 and receives a graphic display control register signal from the outside to output a page start address signal for each mode.

The X position registers 3 and 4 receive a graphics enable signal and write to the BIOS as a 16 bit register for the X position of a cursor or pixel. The pixel position is 16-bit enabled and the character position or cursor position is implemented with logic to make the 8-bit enable bit.

The Y position registers 5 and 6 are 16-bit registers for the Y position of a cursor or pixel by receiving the graphic enable signal.

The adder 7 receives and adds a 20-bit signal from the address generator 2 and a 16-bit signal from the X position registers 3 and 4, and outputs a 20-bit output.

Multiplier 8 receives a 16-bit signal from the Y-position registers 5 and 6 to produce a 20-bit output signal.

The mode specific thermal decomposition register 9 writes the mode specific thermal decomposition value in the video BIOS and applies it to the multiplier 8.

The latches 10 and 11 are latched by a clock that is applied with an output signal from the adder 7 and the multiplier 8.

The adder 12 applies the output signals from the latches 10 and 11 and adds them.

The latch 13 is used for cursor control if it has an actual X and Y position address for graphic acceleration.

The display memory access address generator 14 is generated according to the display memory usage form.

The clock generator 15 generates a usable CPU address latch enable signal by using a CPU cell and a clock generated in a time sequence of the VGA chip, and applies it to the latches 10, 11, 13 to be used as a clock signal.

2 is a detailed block diagram of an address generator, in which 2-1 is a page size register, 2-2 is a multiplier, 2-3 is an adder, and 2-4 shows a page start address unit for each mode.

As shown in the figure, the page size register 2-1 is used in the text mode and varies depending on the size of the page for each mode, and the page value and page size register 2-1 applied from the page register 1 are used. The multiplier 2-2 and the mode-based page start address section 2-4 receiving the output from the display memory area use the display memory area by the VGA graphic enable signal [3: 2] as shown in Tables 1 and 2 below. .

TABLE 1

[Table 2]

The adder 2-3 receives the outputs from the multiplier 2-2 and the mode-based page start address unit 2-4, adds them, and transmits them to the adder 7.

That is, the page size register 2-1 has an updated value when the video mode is set in the video BIOS. When the value of the page register 1 is enabled, the multiplier 2-2 is turned on. The start address section 2-4 has the enable data by the set of GR6.

3 is an internal configuration diagram of a page size register, in which 31 represents an exclusive OR gate.

As shown in the figure, an 8-bit data from the system data bus [7: 0] is used as an input, and an exclusive OR gate 31 that outputs an 8-bit output signal by applying a low signal to the type power stage is implemented.

This is because the page size for each mode is different and the upper 6 bits should be low in the 45x25 text mode and the upper 5 bits should be low in the 80x25 text mode. In other words, when setting the mode in the BIOS as necessary, these two registers also write the corresponding values in consideration of the mode.

4 is a detailed block diagram of the start address unit shown in Tables 1 and 2, in which 41 and 42 are end gates.

As shown in the figure, the 20-bit signal applied to the adder 2-3 applies a low [14: 0] of the start address section 2-4, the high signal as one input, and two inputs. Is inputted with GR6 [3], AND3 is inputted with GR6 [2], AND gate 41 for applying the 16th bit [15], and high signal is applied as one input. And gate 42 for applying the 17th bit [16] by applying the signal, and applying the 18th bit [17] as the other high signal, applying the 19th bit [18] which is low, Bit 20 of the bit [19].

5 is a configuration diagram of a display memory access address generator, in which 51 to 53 are multiplexers, 54 and 55 are NOR gates, and 56 are inverters, respectively.

The present invention can be applied to a VGA chip and a high performance graphics controller to implement graphics acceleration such as cursor controller bit block conversion and window controller.

Therefore, in the present invention, when performing a graphics mode or a text mode using a VGA chip, the display memory address generation for each pixel position and the cursor position offset calculation for the cursor position take up a lot of CPU time (load). This is done by software through the video BIOS, and by implementing the hardware inside the existing VGA chip, it reduces the CPU burden and increases the performance of the VGA chip.

Claims (2)

8-bit register is connected to the page register means (1), the page register means (1), which writes the corresponding page value, i.e., the characteristic, in the BIOS to the display memory, and receives a graphic display control register signal from an external mode. Address generating means (2) for outputting a separate page start address signal; first and second X position register means (3, 4), which are written in the BIOS as a 16-bit register for receiving the graphic enable signal and for the X position of a cursor or a pixel; First and second Y position register means 5 and 6, which are 16 bit registers for Y position of a cursor or a pixel, by receiving a graphic enable signal; The first adding means (7), the first and second Y for receiving a 16-bit signal from the first and second X position register means (3, 4) and outputting a 20-bit output; Multiplication means (8) for receiving a 16-bit signal from the position register means (5,6) to produce a 20-bit output signal, and mode-specific thermal decomposition for writing the thermal decomposition value for each mode in the video BIOS and applying it to the multiplier (8). First and second latches 10 and 11 latched by a clock to which an output signal from the register means 9, the first addition means 7 and the multiplication means 8 is applied and applied; And a second adding means 12 for applying and adding output signals from the second latches 10 and 11, a third latch 13 to be used for cursor control when having actual X and Y position addresses for graphic acceleration, and And a display memory access address generating means (14) for generating in accordance with the display memory usage form. 2. The apparatus according to claim 1, wherein said address generating means (2) comprises; The page size register means 2-1, which is used in the text mode and changes according to the page size for each mode, applies the page value applied from the page register means 1 and the output from the page size register means 2-1. Receiving multiplication means 2-2, mode-specific page start address means 2-4 using the display memory area by the VGA graphic enable signal, and multiplication means 2-2 and the page start address for each mode. And an adder (2-3) for receiving and adding the output from the means (2-4) and transmitting it to the adding means (7).