JPH02207297A - Display memory address device - Google Patents

Abstract

PURPOSE:To perform increment operation by a minimum circuit without using any barrel shifter by generating an enable and a disable signal by a decoding circuit and controlling the operation of a specific bit of an address counter, and performing increment operation. CONSTITUTION:The address counter 12 which generates a display memory address has an enable terminal, to which a signal which puts the address counter 12 in the enable or disable state is inputted from the decoding circuit 13. Therefore, the decoding circuit 13 controls the operation of the specific bit of the address counter 12 to perform the desired increment operation. Consequently, the increment operation is performed by the minimum circuit without using any barrel shifter.

Description

[Detailed description of the invention] Industrial field of application Prior art (Figure 3.4) Problems to be solved by the invention Examples of means and actions for solving the problems Explanation of the principle of the present invention (Figure 1) Book Embodiment of the Invention (Figure 2) Effects of the Invention [Summary] Regarding a display memory addressing device, it is an object of the present invention to provide a display memory addressing device that can perform the same increment operation as the conventional one with a minimum circuit without using a barrel shifter. A display memory addressing device comprising an address counter that generates a display memory address to be input to a display memory, wherein the address counter has an enable terminal, and the enable terminal of the address counter is used to enable or disable the address counter. A decoding circuit is provided that outputs enable and disable signals for disabling the address counter, and by inputting a control signal to the decoding circuit, the enable and disable signals are generated to control the operation of predetermined bits of the address counter. and is configured to perform an increment operation.

[Industrial application field]

The present invention relates to a display memory addressing device, and more particularly to a display memory addressing device that generates a display address to be input to a display memory.

In order to display an image on a CRT display (hereinafter referred to as CRT), it is necessary to provide a horizontal/vertical synchronizing signal and a video signal according to the CRT standard, and a CRT controller controls this synchronizing signal. The video signal is not directly output by the CRT controller, but is output after parallel-to-serial conversion of data read from a memory such as an image memory (frame frame memory) or a character generator.

Therefore, the CRT controller operates as a type of address generator, and uses an oscillation circuit to provide timing for generation of this address and a synchronization signal for the CRT.

In other words, this given timing is the basic unit of display timing on a CRT display, and is the cycle for accessing the image memory (generating a display address).

[Conventional technology]

An example of a conventional display memory addressing device of this type is shown in FIG. 3.4.

FIG. 3 is a diagram showing a schematic configuration of the display system.

In Fig. 3, ■ is a CRT controller, 2 is an image memory (display memory) consisting of frame, sofa, memory, etc., 3 is a parallel-to-serial converter that converts read data from parallel to serial, and 4 is display data. (
This is a CRT display that displays images based on a video signal) and a synchronization signal from a CRT controller 1.

The CRT controller 1 is composed of counters for display addresses and synchronization signals, registers for setting the counters, and the like, and has, for example, a function of generating display memory addresses and a function of generating horizontal and vertical synchronization signals for the CRT display 4.

The horizontal/vertical synchronization timing settings are defined based on a memory cycle called one character period, and
For the video signal, data corresponding to the display screen is allocated in units of dots, and this 1 bit is treated as 1 pixel of the dot on the CRT.
It consists of memory pins corresponding to the screen resolution of the display. Therefore, the video signal is read out from the memory, which is written in advance as image data or font data, based on the display address generated by the CRT controller 4.
Parallel-to-serial conversion is performed in dot units of time.

The CRT display 4 receives horizontal/vertical synchronization signals generated from the CRT controller 1 based on a reference clock CLK, which is the minimum unit of the operation cycle, and also receives video signals ( video signal) is input. This CLK is a cycle for accessing the image memory. For example, when reading 8-bit data and displaying 640 dots in one raster [1 bit/pixel], 640/pixel data is read out. 8 = The image memory will be accessed 80 times. In display access, the address to be accessed is incremented in order, and returns to the first address when the frame access is completed. The settings for CRT controller 1 are memory access cycles (1
Using time as the most basic unit (also referred to as a character period), a value that is an integer multiple of the time is set in advance from the CRT to a register in the CRT controller 1, and thereafter this display operation is repeated cyclically. The video signal is output in synchronization with the dot clock, which is the time obtained by dividing memory access data (for images or from a character generator) by the access time by the amount of data shift.

By the way, as shown in FIG. 4, the output of the address counter 5 in the CRT controller 1 is a barrel shifter (barrel 5hifter) capable of shifting multiple bits.
6 or a shift register to output the address to the outside as a display memory address. The barrel shifter 6 changes the address value from 1 to 1 depending on the mote specification (for example, 1 increment, 2 increment I...
4 increment operation), high image display, cycle steal, etc., are performed quickly and easily.

Problem to be solved by the invention C] However, in such a conventional display memory address device, the barrel shifter 6 is used to increment the address count value by 1, 2, 4 increments, and 1 according to the mode specification. Since the configuration was such that it includes a barrel shifter 6 that can shift multiple bits to shift 1, the circuit configuration has to be large. In case, 20bi
Since all the components must be moved at once, the hardware becomes quite large. Generally, it is necessary to design a circuit with the inside of an IC minimized, and as the amount of circuits (gates) increases, the chip area increases, resulting in higher cost I/I. The size of the barrel shifter 6 varies depending on the shift amount, but is usually several hundred gates.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a display memory addressing device that can perform an increment operation similar to the conventional one with a minimum circuit without using a barrel shifter.

[Means to solve the problem]

To achieve the above object, a display memory addressing device according to the present invention includes an address counter that generates a display memory address to be input to a display memory, wherein the address counter has an enable terminal and the address A decoding circuit for outputting an enable/disable signal to enable or disable the address counter is provided at the enable terminal of the counter, and the enable/disable signal is generated by inputting a control signal to the decoding circuit. It is configured to control the operation of a predetermined pin I of the address counter and perform an increment operation.

[Effect]

In the present invention, an address counter that generates a display memory address has an enable terminal, and a signal that enables or disables the address counter is inputted to the enable terminal from a decoding circuit.

Therefore, the operation of a predetermined pin I of the address counter is controlled by the decoding circuit, and a desired increment operation is performed. As a result, operations such as one increment and two increments can be performed with a minimum circuit without using a barrel shifter.

〔Example〕

FIG. 1 is a diagram for explaining the present invention in detail. 1st
In FIG. 1A, reference numeral 11 denotes a CRT controller (display memory address device), and the CRT controller 11 includes an address counter 12 and a decoding circuit 13.

As can be seen by comparing FIG. 4, which shows the conventional example, with FIG. 1, the device shown in FIG. Assuming that the value of the increment mode designation A input to the decode circuit 13 is set to an appropriate value in a register, command, or hardware, the decode circuit 13 controls the address counter 12 according to the value of the increment mode. Create enable/disable signals for This signal causes address counter 1 to
The display memory address is incremented by controlling the presence/absence of the operation from 1 to 1 in units of 1 to 2 bits. For example, if only the least significant bit of the address counter 12 is invalidated, the display memory address will be 2 as shown in Table 1.
It is incremented and output.

Table 1 In other words, if the address counter 12 has 8 bits as shown in FIG. 1(b), the lowest bit is invalidated (fixed to the initial state) and a clock is given to the address counter 12 in this state. and the enable input terminal EI that controls the 1-count operation (here, the count operation is performed with "H" level input), and the 3rd place bi
It has an enable output signal E○ (here, it is assumed that the upper bit counter performs the counting operation when the "■1" level is output) that controls the counting operation of the t counter.

One output of a decoding circuit 27, which will be described later, is input to the enable input terminal EI of the bit counter 21.
The enable output terminal EO of the bit counter 21 is connected to the enable input terminal EI of the focus counter 22 via the AND circuit 26, and its enable output terminal E○ is connected to the enable input terminal El of the bit counter 23, and its enable output ( The i number Eo is the bit counter 24
is connected to the enable input terminal ET of. Therefore, it operates when the enable input signal ET is at the "H" level, and does not operate when it is at the "L" level.Also, the output of the enable output terminal EO is the same as the Garry output of the counter, but the El terminal is ' When the input is at the "L" level, the output is always at the "T-I" level.
You will be left behind. Similarly, if the lower 2 bits are fixed to the initial state, a 4-increment operation will be performed.

Embodiments will be described based on the basic principles described below. FIG. 2 is a diagram showing an embodiment of the display memory address device according to the present invention, and shows an example applied to a circuit that performs an increment operation of a 4-bit counter. Also, if the increment operation is performed, 1 increment I, 2 increment I
. , 4 increments I. only.

In this figure, 21 to 24 are bit counters,
Bit counter 21 is the lowest hit, hit counter 2
4 is the most significant bit and goes to Pi1 counters 21-24
constitutes a 4-bit address counter 25 as a whole. The pinot I counters 21 to 24 are connected to a clock input terminal CI (to which a clock CLK for performing a counter operation is input), and an output terminal Do to output each bit of counter output data (display memory address). Output signal E○ data output from the counter (1 bit)
For example, when it is 0”, the enable becomes “H”,
When it outputs ``1'', it outputs ``,'' and enters the disable state. Therefore, if the counter is the 0th bit of the counter 21, it is determined whether the counter has carried up to the counter state.

On the other hand, 27 is a decoding circuit in which mode designation signals (control signals) AI and A2 are manually input, and the decoding circuit 27 is E
It is composed of a NOR circuit 28, an inverter 29, and an OR circuit 30. AI is input to the ENOR circuit 28 and also to the OR circuit 30, and A2
It is input to the circuit 28 and also to the OR circuit 30 via the inverter 29. Further, the output of ENOR is outputted to the enable input terminal ET of the bit counter 21 as the output of the decoding circuit 27, and the output of the OR circuit is inputted to one input terminal of the AND circuit 26. Therefore, the enable input terminal E of the bit counter 21
The output data from the bit counter 21 is determined by the signal input to the bit counter 21, and the output of the OR circuit 30 is
The bit counter 22 is inputted to the D circuit 26.
The output data of is determined. From this, 1 increment, 2 increment and 4 increment operations are determined.

Next, the effect will be explained.

The increment operation shown in Table 2 is specified by the input levels of A1 and A2. With this designation, a counter operation not shown in Table 2 is performed.

Table 2 “H” to enable input terminal ET of bit counter 21
” is input, and the focus counter 21 is enabled. On the other hand, “L” is always input to one input terminal El of the AND circuit 26, and the 1st and 2nd bits of the address counter 25 are set to the 1-th bit. Performs a 4-increment operation that always stops working (always outputs the initial value).

As described above, the conventional example uses a barrel shifter 6 or a shift register and has a circuit with several tens to several gates, but according to this embodiment, only a few gates are used as the decoding circuit 27, which is the same as the conventional example. Increment operation can be performed. Furthermore, if the bit length of the counter increases, all bits are shifted in the conventional example, which increases the size of the circuit, whereas the circuit of this embodiment changes the pitch I/length of the counter as long as the designated mode is the same. is irrelevant.

For example, in the case of a 1 increment and 2 increment 1~ circuit, even if the number of bits in the memory address increases, the data 1-number in the decoder section will not increase, but the number of bits in the address counter will simply increase by some bits. On the other hand, in the conventional example using a barrel shifter, "'H" is input when the number of bits of the barrel shifter increases in addition to the number of bits of the address counter increasing. Therefore, one increment operation (normal operation) is performed, and all the counters 21 to 24 operate.

A1. When A2 is set to "HI-", "L" is input to the enable input terminal EI of the bit counter 21, and "H" is input to one input terminal of the AND circuit 26.
is input. Therefore, the bit counter 21 enters the enabled state and the bits 1 to 1 of the address counter 25
Only the first bit does not operate (that is, the initial value remains output), and from the next bit onwards, the 2-increment operation is performed normally.

When “LH” is applied to AlA2, “L” is input to the pinto enable input terminal EI, and
L" is input to one input terminal of the AND circuit 26. Therefore, the bit counter 21 enters the disabled state, and the bit counter 21 stops operating.
The enable output signal of the bit counter 21 inputted to one terminal of the AND circuit 26 and “'L” inputted to the other terminal of the AND circuit 26 cause the bit counter 22 to be
is enabled. In any case, since the same operation as the conventional one can be performed with a minimum circuit without using the barrel shifter 6, the chip area can be significantly reduced and costs can be reduced.

〔Effect of the invention〕

According to the present invention, it is possible to realize a display memory addressing device that can obtain the same increment operation as the conventional one with a minimum circuit without using a barrel shifter.

[Brief explanation of the drawing]

Fig. 1 is a diagram explaining the principle of the present invention, Fig. 2 is a diagram showing a circuit for incrementing a 4-bit counter of a display memory address device according to the present invention, and Fig. 3.4 is a diagram showing a conventional display memory address device. FIG. 3 is a schematic configuration diagram of a display system, and FIG. 4 is a diagram showing a display memory address device. 11...CRT controller (display memory address device), 12.25...Address counter, 13.27
...Decode circuit, 21 to 24 ... Focus counter, 26 ... AND circuit, 28 ... ENOR circuit, 29 ... Inverter, 30...OR circuit, ET...Enable input terminal (enable terminal), EO...Enable output terminal (enable terminal). Agent Patent attorney Igatasada

Claims (1)

[Scope of Claims] A display memory address device including an address counter that generates a display memory address to be input to a display memory, wherein the address counter has an enable terminal, and the address counter has an enable terminal connected to the address counter. A decoding circuit is provided that outputs an enable/disable signal to enable or disable the address counter, and by inputting a control signal to the decoding circuit, the enable/disable signal is generated to set a predetermined bit of the address counter. A display memory addressing device configured to control operations and perform incrementing operations.