JPH07281634A - Liquid crystal display - Google Patents

Abstract

PURPOSE:To reduce the power consumption of an information processor using a liquid crystal display and to realize high-speed plotting access. CONSTITUTION:A display memory 134 equivalent to one screen is incorporated in a liquid crystal driver 101, display data equivalent to one horizontal line is read at a rate of once per horizontal period, converted into an applied voltage to liquid crystal and displayed on a liquid crystal driver 102, an address bus 105 and a data bus 106 are provided on the liquid crystal driver 101 and data in an optional position is caused to be easily updated. Further, a selection circuit 112 for selecting the latch lock of an address is provided and thereby continuous plotting is made possible in horizontal and vertical directions.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal driver having a built-in display memory, and a liquid crystal display and an information processing device using the liquid crystal driver.

[0002]

2. Description of the Related Art A conventional liquid crystal display is shown in FIGS.
Will be explained.

FIG. 2 is a block diagram of a liquid crystal display using a conventional liquid crystal driver.

In FIG. 2, 201 is a liquid crystal driver, and 102 is a liquid crystal panel. In this embodiment, the horizontal resolution is 160 dots and the vertical resolution is 240 lines. X
1 to X160, Y drive electrodes Y1 to Y240
Becomes Reference numeral 202 is a scanning circuit, and 104 is a power supply circuit.

In the liquid crystal driver 201, 203 is a data bus for transferring display data, 204 is a latch clock (hereinafter also referred to as CL2) synchronized with the display data, and 121 is a synchronizing signal having a frequency of a horizontal cycle. (Hereinafter, also referred to as CL1.

[0006] 123 is a liquid crystal alternating signal for instructing alternating current of the liquid crystal, and in the present embodiment, any of the above signals is inputted from an external system (not shown in the drawing). . Reference numeral 205 denotes a latch clock generation circuit, 206 denotes a clock bus for transferring the latch clock generated by the latch clock generation circuit 205, and 2
Reference numeral 07 denotes a shift register, which sequentially stores display data transferred via the data bus 203 in accordance with a latch clock that is valid on the clock bus 206, and transfers the stored data via the data bus 208. Reference numeral 209 denotes a line latch circuit, which simultaneously stores display data for one horizontal line transferred via the data bus 208 in synchronization with the synchronization signal 121, and the stored data is transferred by the data bus 210. Reference numeral 140 denotes a level shift circuit, which is a circuit for converting a voltage of a logic level of about 5V into a voltage level of about 15V or higher required to drive the liquid crystal panel 102. Reference numeral 141 is a data bus for transferring the display data of the level-shifted voltage level, and 142 is the data bus 1.
A voltage selection circuit that selects a display-on voltage and a display-off voltage according to the display data transferred at 41, generates a liquid crystal applied voltage, and outputs the voltage to the liquid crystal panel 102. The liquid crystal application selected by the voltage selection circuit 142 is applied. The voltage is transferred to the liquid crystal panel 102 via the output terminal of 143. The output terminal 14
3 is connected to the X drive electrode of the liquid crystal panel 102.

Since the scanning circuit 202 controls the application of the selection voltage to the scanning line and the non-selection voltage to the non-scanning line, the output terminal 148 is the liquid crystal panel 1.
No. 02 Y drive electrode.

Reference numeral 122 is a signal for instructing the data of the first line to be displayed on the liquid crystal panel 102, that is, the first line, and is a synchronizing signal having a frequency of a frame cycle (hereinafter, FLM).
Also called. ). The synchronization signal 122 is input from an external system (not shown in the drawing).

FIG. 3 is a timing chart for explaining the operation of the conventional liquid crystal driver 201 shown in FIG.

FIG. 4 is a block diagram of an information processing apparatus composed of a liquid crystal display using the conventional liquid crystal driver shown in FIG.

In FIG. 4, 401 is a liquid crystal display using the conventional liquid crystal driver 201 shown in FIG.
Reference numeral 402 is a CPU, 403 is a memory, and 404
Is an I / O controller, 405 is a display controller, and 406 is a display memory. 444 is an address bus, 445 is a data bus, and 446 is a control signal.

In the display controller 405, 407
Is an address conversion circuit, and 408 is an address bus for transferring the converted address. A selection circuit 409 serves as a circuit for selecting an upper address and a lower address transferred by the address bus 408. Therefore, the output address is a multiplexed address, and the address bus 410
To transfer. Reference numeral 411 is a display counter, which generates a display address and a synchronization signal, and outputs 412 address buses,
It is transferred by the synchronization signal bus 413. Sync signal bus 413
, Includes the synchronization signals 122 and 123 described in FIG. Reference numeral 414 is a selection circuit, which is an address bus 41.
Since it is a circuit for selecting the upper address and the lower address transferred in 2, the output address becomes a multiplexed address and is transferred by the address bus 415. 416
Is a selection circuit, which selects an address transferred by the address bus 410 and the address bus 415 and transfers it to the display memory 406 via the address bus 417. Reference numeral 418 is a bidirectional buffer circuit, and 419 is a data bus that controls data transfer between the display controller 405 and the display memory 406. 420 is a display memory 40 for display.
6 is a data bus for transferring the display data read from the reference numeral 6, 421 is a parallel / serial conversion circuit, and the serial-converted display data is transferred to the liquid crystal display 401 via the data bus 203. A timing signal generation circuit 422 generates various timing signals for operating the display controller. Reference numeral 423 is a clock for operating the display counter 411, 424 is a selection signal of the selection circuits 409 and 415, and 425 is a CPU for accessing the display memory 406.
Address bus 41 when the accelerator is from 402
Select the address to be transferred via 0 and display memory 4
Access to the display data to display liquid crystal display 40
Address bus 41 when the access is to 1
5 is a selection signal for performing arbitration control for selecting an address transferred via the address 5. Access to the display memory 406 is C
When the accelerator is from the PU 402, the memory read enable signal 426 or the write enable signal 427 is input, and the timing signal generation circuit performs arbitration control. Reference numeral 428 denotes a latch clock (hereinafter, referred to as RAS) that takes in a row address which is an upper address among the addresses multiplexed and transferred by the address bus 417.
429 is a latch clock (hereinafter referred to as CAS) that takes in a column address, which is a lower address among the addresses multiplexed and transferred by the address bus 417, and 430 is a control for reading and writing display data. Is a write enable signal (hereinafter, referred to as WE). Both signals are transferred to the display memory 406.

In the display memory 406, 431 is a latch circuit for storing the row address transferred by the address bus 417, and 432 is an address bus for transferring the stored row address. 433 is an address bus 417
Is a latch circuit for storing the column address transferred by (4), and 433 is an address bus for transferring the stored column address. 435 is a row address decoder,
The output of the 436 row address decoder 435 is a word line selection signal. 437 is a column address decoder, and 438 is an output of the column address decoder 437, which is a data line selection signal. Reference numeral 439 is a data selection circuit, and 440 is a data bus for transferring display data.
A memory cell array 441 stores display data for one screen. Therefore, in this embodiment, one pixel is 1
Since it is described as having bit data information,
It is assumed that display data information of 160 bits in the horizontal direction and 240 bits in the vertical direction is stored. Reference numeral 442 is a data bus for transferring write / read data to / from the memory cell array 441, and 443 is a bidirectional buffer circuit for controlling the data transfer direction.

FIG. 5 is a diagram for explaining the memory map of the liquid crystal display 401.

FIG. 6 is a timing chart showing how the display memory 406 shown in FIG. 4 is accessed.

FIG. 7 is a timing chart of dynamic access when the CPU 402 performs display data write / read control to the display memory 406 (hereinafter referred to as drawing).

FIG. 8 is a timing chart of paging access when the CPU 402 draws display data on the display memory 406.

FIG. 9 shows an example of bitmap data of the character "A".

Again, the operation of the conventional liquid crystal driver and the operation of the liquid crystal display using the conventional liquid crystal driver will be described with reference to FIG.

In the conventional liquid crystal driver 201 shown in FIG. 2, the latch clock generation circuit 205 synchronizes with the latch clock 204 to generate a latch clock for sequentially storing display data transferred via the data bus 203 in the shift register 207. To generate. Since the latch clock 204 and the display data are synchronized as shown in FIG. 3, the shift register 207 has one horizontal line (in this embodiment, 1
Display data of 60 dots) will be fetched. When the display data for one horizontal line is stored in the shift register 207, the synchronization signal 121 becomes effective, and the latch circuit 1
40 simultaneously captures the display data for one horizontal line transferred via the data bus 208. The data taken into the latch circuit 140 is the level shifter circuit 1
At a voltage of 40, a voltage of a logic level of about 5 V is applied to the liquid crystal panel
To a voltage level of about 15 V or higher required to drive the. The level-converted display data is supplied to the voltage selection circuit 14
2 the liquid crystal drive voltage 150 according to the liquid crystal alternating signal 123
The display-on voltage and the display-off voltage are selected from among them. As a result, the liquid crystal applied voltage corresponding to the display data can be simultaneously generated for the output terminal 143 for one line. When the output liquid crystal applied voltage is the voltage corresponding to the first line of the liquid crystal panel 102, the scanning circuit 202 causes the synchronization signal 12
When 2 is enabled, the output terminal 148 operates in synchronization with the synchronization signal 121 to apply a selection voltage to the Y drive electrode y1 of the first line of the liquid crystal panel 102. In the liquid crystal panel 102, the effective voltage is the difference voltage between the selection voltage generated by the scanning circuit 202 and the liquid crystal applied voltage generated by the liquid crystal driver 201. Since the effective voltage can control the transmittance of the liquid crystal, it is possible to perform display. Become. Therefore, the first line of the liquid crystal panel 102 can be displayed by the above operation. Further, in the liquid crystal driver 201, the latch circuit 209, the level shifter circuit 140, the voltage selection circuit 142.
While generating the liquid crystal applied voltage of the uppermost line, the latch clock generation circuit 205 and the shift register 207
Starts the operation of fetching the display data of the second line. Then, when the acquisition of the display data for one horizontal line is completed again, the synchronization signal 121 becomes valid, and the liquid crystal applied voltage is generated via the latch circuit 209, the level shifter circuit 140, and the voltage selection circuit 142. Then, in synchronization with this, the scanning circuit operates so as to apply a selection voltage to the Y drive electrode y2 of the second line of the liquid crystal panel 102 among the output terminals 148. By repeating this operation, it is possible to display one screen.

As described above, in the liquid crystal display using the conventional liquid crystal driver 201, even if the display screen is a still image, it is necessary to always fetch the display data in synchronization with the synchronization signal 204. Therefore, an information processing device using this liquid crystal display is as shown in FIG.

In FIG. 4, the display data displayed on the liquid crystal display 401 can be generated by sequentially reading the display data stored in the display memory 406. Display reading from the display memory will be described.

When reading display data from the display memory, the display counter 411 sequentially counts up in synchronization with the clock 423. The output value becomes the display address, and the selection circuits 414 and 416 select the display memory 40.
6 address bus 417 format is converted into a multiplexed address. Then, since the selection circuit 416 selects the address bus 415 by the selection signal 425, the multiplexed display address is output to the address bus 417. The display memory 406 latches the row address of the display addresses in the latch circuit 431 in synchronization with the RAS 428. Further, the column address of the display address is latched in the latch circuit 433 in synchronization with the CAS 429. The latched addresses are output to the decoding circuits 435 and 4337. The decode circuit 435 selects a word line in the memory cell array 441 designated by the row address and transfers display data for one horizontal line corresponding to the row address to the data selection circuit 439 via the data bus 440. In the data selection circuit 439, according to the decode signal generated by the decode circuit 437, the data bus 442 of the data for one horizontal line is generated.
It is selected and output according to the bus width of 419. When the bus width of the data buses 442 and 419 is 8 bits, 8-bit data is selected.

The selected display data is the display memory 406.
Bidirectional buffer circuit 443 and display controller 40
5 is transferred to the parallel / serial conversion circuit 421 through the bidirectional buffer circuit 418 in the liquid crystal display 4.
Will be transferred to 01. For example, as shown in FIG. 5, when the display is performed on the first line, that is, on the Y drive electrode y0, the row address is hex. 0, and the display data supplied to the X drive electrodes x1 to x7 driven by the liquid crystal driver 201 has the column address hex. 0, the column address is sequentially counted up, and the display data supplied from the X drive electrodes x152 to x160 has the column address h.
ex. It will be read as 49. When displaying on the second line, that is, on the Y drive electrode y1, the row address is hex. All the display data of the second line can be read by setting the value to 1 and counting up the column address in the same manner as in the first line. By repeating this, it is possible to read the display data for one screen, but in this conventional example, 20 (=
Display memory access of 160 dots / 8 bits) is required.

Therefore, in the conventional information processing apparatus, even if the display screen is a still image, it is necessary to always access the display memory 406, which is an obstacle to reducing the power consumption.

When updating the display data stored in the display memory 406, the CPU 402 draws. The CPU 402 enables the memory read enable signal 426 or the memory write enable signal 427, which is a drawing command, and also activates the system address bus 4
The address for drawing is transferred to 44, and the display data for drawing is transferred by the system data bus 445. The address conversion circuit 407 determines whether the address is an address in the display memory 406 space, and the selection circuits 414 and 416 convert the address into a multiplexed address in accordance with the format of the address bus 417 of the display memory 406 to obtain a desired address. It becomes possible to control the reading and writing of the display data to the position. In order to increase the drawing speed, in the conventional information processing apparatus, the display data is displayed on the liquid crystal display 4 as shown in FIG.
01 for display access and transfer to display memory 40
It was necessary to control the drawing access for updating the display data stored in No. 6 in a time division manner. However, as shown in FIG. 6, since the drawing access can be executed only once in four access cycles of the display memory 406, there is a problem that the display data cannot be updated at high speed.

Further, the display data is displayed on the liquid crystal display 40.
During the period in which the data is not transferred to 1, the drawing access can be continuously performed as shown in FIG. 7, but a function of the display memory 406 called a paging mode can be used for further speeding up. . The paging mode is a function that allows continuous access to data on the same row address, and as shown in FIG. 8, by fixing the row address latched when RAS 428 is asserted and changing the column address, high-speed drawing is possible. Can be realized.
However, when drawing the character data as shown in FIG. 9, since the drawing process is continuously performed in the line direction, the current paging mode cannot be used and the dynamic mode is used. , The drawing speed could not be improved further.

[0028]

Conventional liquid crystal driver 2
Even if the display screen of the liquid crystal display using 01 is a still image, it is necessary to always fetch the display data in synchronization with the synchronization signal 204. Therefore, in the example using the conventional liquid crystal driver, there is a problem in that it is necessary to access the display memory 20 (= 160 dots / 8 bits) times within one horizontal period, which hinders reduction of power consumption.

Further, since the display access and the drawing access to the display memory 406 are performed in a time-sharing manner, the drawing access can be executed only about once every four access cycles, so that the display data can be updated at high speed. There was no problem.

Further, when the character data as shown in FIG. 9 is drawn, since the drawing process is continuously performed in the vertical direction, it is possible to use the paging mode in which the current horizontal direction can be continuously accessed. I could not do it, and I had to use the dynamic mode, so I could not improve the drawing speed further.

An object of the present invention is to reduce the power consumption of an information processing device using a liquid crystal display and to realize high-speed drawing access.

[0032]

In order to achieve the above object, a liquid crystal driver for generating a liquid crystal applied voltage corresponding to display data has a built-in display memory for one screen, and a sync signal having a horizontal cycle frequency is generated. There are provided means for simultaneously reading out the display data for one horizontal line in synchronism, means for temporarily storing the display data for one horizontal line, and means for converting the display data for one horizontal line into a liquid crystal applied voltage and outputting it. . Further, a means for inputting an address bus, a data bus and a control signal to the liquid crystal driver, a circuit for storing an address, a means for selecting an address of a line for displaying and an address for external access are provided.

Further, there is provided means for selecting a timing signal to be taken into the means for storing the multiplexed address.

Further, in order to perform drawing access, means for storing the number of times the address is incremented and means for incrementing the address are provided.

[0035]

Function: A liquid crystal driver for generating a liquid crystal applied voltage corresponding to display data has a built-in display memory for one screen, and simultaneously reads out display data for one horizontal line in synchronization with a synchronization signal having a frequency of a horizontal cycle. And means for temporarily storing display data for one horizontal line and means for converting display data for one horizontal line into a liquid crystal applied voltage and outputting the same.
The display data for one horizontal line is converted into a voltage applied to the liquid crystal only by accessing the display memory once every one horizontal period.

Further, the means for inputting the address bus, the data bus and the control signal to the liquid crystal driver, the circuit for storing the address, and the means for selecting the address of the line for displaying and the address for external access are: The display data stored in the display memory is arbitrarily selected and updated.

Further, the means for selecting the timing signal to be fetched into the means for storing the multiplexed address does not only continuously access the horizontal address on the display memory but also continuously accesses the vertical address. There is an action that can be done.

Further, the means for storing the number of times the address is incremented and the means for incrementing the address have the function of generating consecutive addresses in a certain area in the liquid crystal driver.

[0039]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention is shown in FIGS.
2 is used for the explanation.

FIG. 1 is a block diagram of a liquid crystal display using the liquid crystal driver of the present invention.

In FIG. 1, 101 is a liquid crystal driver having a built-in memory, and 102 is a liquid crystal panel. In this embodiment, horizontal resolution is 160 dots and vertical resolution is 240 dots.
Since the description will be given using lines, the X drive electrodes of the liquid crystal panel 102 are changed from X1 to X160 and the Y drive electrodes thereof are changed from Y1 to Y240. 103 is a scanning circuit,
Reference numeral 04 is a power supply circuit. In the liquid crystal driver 101, 105 is an address bus for transferring a display address, which multiplexes and transfers a row address (hereinafter referred to as a row address) and a column address (hereinafter referred to as a column address). 106 is a data bus for transferring display data, 107 is a latch clock (hereinafter, referred to as RAS) that captures a row address, 108 is a latch clock (hereinafter, referred to as CAS) that captures a column address, Reference numeral 109 is a write enable signal (hereinafter, referred to as WE) for reading and writing display data, and 110 is a control signal for instructing an access mode to the memory. In this embodiment, any of the above signals will be input from an external system (not shown in the drawing). Reference numerals 111 and 112 are selection circuits for switching between the RAS 107 and the CAS 108, and reference numerals 113 and 114 are selected latch clocks. Reference numeral 115 is a latch circuit for storing a row address, 116 is a latch circuit for storing a column address, 117 is an address bus for transferring the row address stored by the latch circuit 115, and 118 is a storage circuit for the latch circuit 116. An address bus that transfers column addresses. Reference numeral 119 is a bidirectional buffer circuit that controls the data transfer direction, and 120 is a data bus that transfers display data. Reference numeral 121 is a sync signal synchronized with the horizontal frequency (hereinafter, also referred to as CL1), and 122 is a signal indicating the first line data to be displayed on the liquid crystal panel 102, and a sync signal synchronized with the vertical frequency (hereinafter FL).
Also called M. ), And 123 is a liquid crystal alternating current signal for instructing alternating current of the liquid crystal, and in the present embodiment, any of the above signals is input from the scanning circuit 103. 1
A scanning counter 24 generates a row address for display by using the synchronizing signals 121 and 122, and transfers the row address through an address bus 125. A selection circuit 126 selects a row address transferred via the address bus 117 and a row address transferred via the address bus 125, and transfers the selected row address via the 127 address bus. 128 is a row address decoder, which is 1
Reference numeral 29 is an output of the row address decoder 1028, which is a word line selection signal. Reference numeral 130 is a column address decoder, and 131 is an output of the column address decoder 130, which is a data line selection signal. Reference numeral 132 is a data selection circuit, and 133 is a data bus for transferring display data.
A memory cell array 134 stores display data for one screen. Therefore, in this embodiment, one pixel is 1
Since it is described as having bit data information,
It is assumed that display data information of 160 bits in the horizontal direction and 240 bits in the vertical direction is stored. 135 is a liquid crystal panel 1
Reference numeral 02 denotes a data bus used to transfer display data from the memory cell array to perform display, and 136 denotes a line latch circuit for temporarily storing display data.
37 is a data bus for transferring the display data stored in the line latch circuit 136, 138 is a line latch circuit for temporarily storing the display data, and 139 is a data bus for transferring the display data stored in the line latch circuit 138. is there. Reference numeral 140 denotes a level shift circuit, which is a circuit for converting a voltage of a logic level of about 5V into a voltage level of about 15V or higher required to drive the liquid crystal panel 102.
Reference numeral 141 is a data bus for transferring the display data of the level-shifted voltage level, and 142 is the data bus 141.
The display-on voltage and the display-off voltage are selected according to the display data transferred by, and the liquid crystal applied voltage is generated to generate the liquid crystal panel 1.
02 is a voltage selection circuit for outputting to
The liquid crystal applied voltage selected in 2 is transferred to the liquid crystal panel 102 via the output terminal 143. The output terminal 201 is connected to the X drive electrode of the liquid crystal panel 102. 144 is a timing signal generation circuit for controlling the overall operation of the liquid crystal driver 101, 145 is a selection signal of the selection circuit 126, and via the address bus 117 when the access to the memory cell array 134 is an accelerator from the system. Arbitration control for selecting a row address to be transferred via the address bus 125 when the row address to be transferred is selected and the access to the memory cell array 134 is an access to display on the liquid crystal panel 102. Become. 146 is a memory access enable signal, and this signal is input to the row address decoder 128, the column address decoder 130, and the memory cell array 134. 1
Reference numeral 47 is a display data latch signal, which is valid when the access to the memory cell array 134 is an access for displaying on the liquid crystal panel 102, and the timing is variable by the arbitration control with the access from the system. , A signal that becomes valid every horizontal period, and is input to the line latch circuit 136.

Since the scanning circuit 103 controls the application of the selection voltage to the scanning line and the non-selection voltage to the non-scanning line, the output terminal 148 is the liquid crystal panel 1.
No. 02 Y drive electrode.

The power supply circuit 104 uses liquid crystal drive voltages 149, 1
50, and the liquid crystal drive voltage 149 is applied to the scanning circuit 103.
Further, the liquid crystal drive voltage 150 is input to the liquid crystal driver 101.

FIG. 7 is a timing chart of dynamic access when writing and reading display data to and from the display memory in the liquid crystal driver 101 (hereinafter referred to as drawing).

FIG. 8 is a timing chart for paging access when writing and reading display data to and from the display memory in the liquid crystal driver 101 (hereinafter referred to as drawing).

FIG. 9 shows an example of bitmap data of the character'A '.

FIG. 10 shows the liquid crystal driver 101 shown in FIG.
FIG. 9 is a timing chart of a display access for supplying a liquid crystal applied voltage corresponding to display data to the liquid crystal panel 102.

FIG. 11 shows a liquid crystal driver 101 shown in FIG.
FIG. 6 is a timing chart of the high speed page access of FIG.

FIG. 12 is a block diagram of an information equipment device constituted by using the liquid crystal display shown in FIG.

In FIG. 12, reference numeral 402 is a CPU, 403 is a memory, 404 is an I / O controller, 444 is an address bus, 445 is a data bus, and 446 is a control signal. 12
Reference numeral 01 is a liquid crystal display, 1202 is a timing signal generation circuit, 1203 is a selection signal for multiplexing an address into a row address and a column address, 12
Reference numeral 04 is an address selection circuit.

The first embodiment of the present invention will be described below with reference to FIG.
The operation will be described in detail below.

First, referring to FIG. 1, the liquid crystal panel 10 is shown.
The display access for outputting the liquid crystal applied voltage corresponding to the display data and displaying is described in 2. For display access, display data for one horizontal line stored in the memory cell array 134 is transferred to the latch circuit 136, the latch circuit 138,
The voltage is converted into a liquid crystal applied voltage via the level shifter circuit 140 and the voltage selection circuit 142, output to the output terminal 143, and supplied to the liquid crystal panel 102. More specifically, the address generated by the scan counter 124 is selected by the selection circuit 126 and output to the address bus 127. The selection circuit 126 is the timing signal generation circuit 1
It is controlled by the selection signal 145 generated by 12 and operates as described above when the display access is valid. Then, the row address decoding circuit 128 validates the display data for one horizontal line of the corresponding memory cell array 134 of the word line selection signal 129 according to the input address,
Output to the data bus 135. In the latch circuit 136,
The latch clock 14 generated by the timing signal generation circuit 112 is controlled by the arbitration control with the drawing access described later.
In synchronism with 6, the display data for one horizontal line transferred onto the data bus 136 is simultaneously fetched. The latch circuit 138 latches the display data stored in the latch circuit 136 which is transferred onto the data bus 137 at the timing of the synchronizing signal 121 synchronized with the horizontal cycle. Then, the display data, which is the voltage of the logic level of about 5V, latched by the latch circuit 138, is level-converted by the level shift circuit 140 to a voltage level of about 15V or higher required to drive the liquid crystal panel 102. The display data that has undergone the voltage level image conversion is input to the voltage selection circuit 142, and the liquid crystal driving voltage 15
One of the display on voltage and the display off voltage of 0 is selected to generate a liquid crystal applied voltage, and 1 is applied to the output terminal 143.
Output for horizontal lines at the same time.

Since the scanning counter 124 receives the synchronizing signal 121 synchronized with the horizontal period and the synchronizing signal 122 synchronized with the vertical period, an address which is a counter value output when the synchronizing signal 122 is inputted. Is he
x. It becomes 0. Therefore, the first memory cell array 134
Enable the word line selection signal 129 corresponding to the line,
The display data of the first line is fetched by the latch circuit 136 and fetched by the latch circuit 138 in synchronization with the synchronizing signal 121. Therefore, the liquid crystal applied voltage output from the liquid crystal driver 101 can be obtained at the timing shown in FIG. In synchronization with this, when the synchronizing signal 122 becomes valid, the scanning circuit 103 operates so as to apply a selection voltage to the Y drive electrode y1 corresponding to the first line of the liquid crystal panel 102 among the output terminals 148. The liquid crystal panel 102 includes the scanning circuit 10
The difference voltage between the selection voltage generated in 3 and the liquid crystal application voltage generated in the liquid crystal driver 101 becomes the effective voltage, and the transmittance of the liquid crystal in the pixel portion can be controlled, so that the first line display can be performed.

Then, when the synchronizing signal 121 becomes valid next time, the scanning counter 124 in the liquid crystal driver 101 sets the address to hex. Count up to 1. Therefore, the row address decoding circuit 128 validates the word line selection signal 129 corresponding to the second line, similarly to the case where the display data of the first line is selected. Then, in the same operation as the first line, the liquid crystal applied voltage corresponding to the display data of the second line is output to the output terminal 143. Also, the scanning circuit 1
In 03, since the operation is performed so as to apply the selection voltage to the Y drive electrode y2, the display of the second line can be performed. By repeating this in sequence, one screen can be displayed. Furthermore,
When the display for one screen is completed, the synchronization signal 122 becomes valid and the same operation is repeated again.

Therefore, the display memory is set to the liquid crystal driver 101.
Since the display memory can be displayed on the liquid crystal panel 102 only by accessing the display memory once in the horizontal cycle by incorporating the same in the display memory, the display memory can be compared to the conventional liquid crystal display and information processing device using the liquid crystal driver. The frequency of access to the device is reduced, and the power consumption can be reduced.

Next, the control for updating the display data stored in the display memory built in the liquid crystal driver 101 will be described. When the display data stored in the display memory stored in the liquid crystal driver 101 is updated, it can be easily accessed from the outside by using the same interface as the conventional display memory.

That is, as shown in FIG. 1 and FIG.
When S107 is asserted, the row address of the display addresses to be updated is stored in the latch circuit 115, and CAS1
When asserting 08, the column address of the display address to be updated is stored in the latch circuit 116. The row address stored in the latch circuit 115 is selected by the selection circuit 126, the word line decoded by the row address decoder circuit 125 is selected, and the display data of the corresponding one horizontal line stored in the memory cell array is transferred to the data bus 1.
Appears at 33. Then, the column address decoding circuit 130 determines which data is selected from the column address stored in the latch circuit 116. When the write enable signal is valid, the write data via the bidirectional buffer 119 will be written to the memoryrel array 134. Further, when the write enable signal is not valid, the read data is transferred to the outside through the bidirectional buffer. As a result, the display data stored in the display memory can be updated.

Since the display access for transferring the display data to the liquid crystal panel 102 occurs only once per horizontal frequency, the drawing access can occupy most of the horizontal period. Further, since the row address is stored in the latch circuit 115 as shown in FIG.
By sequentially asserting the column addresses, the display data on the same row address can be drawn at high speed.

Further, in the liquid crystal display of this embodiment, since the synchronizing signal 121, the synchronizing signal 122 and the liquid crystal alternating signal 123 are generated by the scanning circuit 148, it is not necessary for the external circuit to be aware of display access. At the same time, it is not necessary to generate the control signals. Therefore, even if the display access and the drawing access occur at the same timing, there is a latch circuit 136 that pre-reads in advance, so that the timing signal generation circuit 144 causes the latch clock 147.
By adjusting the timing of, drawing access can be prioritized and high-speed drawing becomes possible.

Therefore, as shown in FIG. 11, the information equipment device using the present liquid crystal display has an address selection circuit 1103 for multiplexing addresses and a timing signal generation circuit 11 for generating RAS, CAS, and WE timing signals.
It is enough to provide 02.

As means for realizing high-speed drawing of the characters and the like shown in FIG. 9, RAS 107 and CAS as shown in FIG.
It is decided to provide selection circuits 111 and 112 for switching 108. When the control signal 110 is at the “High” level, high-speed drawing is possible only by changing the column address as in the paging access described in FIG.
RA when the control signal 110 is at “Low” level
The column address is taken into the latch circuit 116 at the timing when S107 is asserted, and the row address is taken into the latch circuit 115 at the timing when CAS is asserted. Thereby, RAS107, CAS108
The timing is the same as before, but by inputting the address at the timing shown in FIG. 12, it is only necessary to change the row address with the same column address. It becomes accessible. Further, the switching between the row address and the column address can be easily realized only by changing the switching timing of the selection circuit 1103 shown in FIG.

Next, the second embodiment will be described with reference to FIGS. 13 to 15.

FIG. 13 is a block diagram of a liquid crystal display using the liquid crystal driver of the second embodiment.

In FIG. 13, reference numeral 1301 is a liquid crystal driver having a built-in display memory, and 1302 is a negative logic AN.
Reference numeral 1303 denotes a D circuit, and 1303 is a memory access valid signal (hereinafter, also referred to as MA) output to the AND circuit 1302.

FIG. 14 shows the liquid crystal driver 13 shown in FIG.
FIG. 16 is a first example of a timing chart of the paging access of No. 02.

FIG. 15 shows the liquid crystal driver 13 shown in FIG.
23 is a second example of a timing chart of the paging access of 02. FIG.

Again, the operation will be described in detail with reference to FIG.

In FIG. 13, the display access operation of the liquid crystal driver 1301 is the same as that of the liquid crystal driver 101 of the first embodiment shown in FIG. 1, and therefore its explanation is omitted here. Therefore, the drawing access will be described. In this embodiment, the row address and the RAS 107, the column address and the CAS 108 transferred by the address bus 105 are transferred.
Is based on the assumption that it is always valid at the synchronized timing. That is, the timing signal generation circuit 144
14 enables the memory access enable signal MAE1303 as shown in the timing charts of FIGS. 14 and 15 only when both RAS 107 and CAS 108 are asserted by the AND circuit 1302, so that the row address is constant as shown in FIG. Therefore, it is not necessary to be aware of whether it is a paging access for inputting a column address or a paging access for sequentially inputting a row address with a constant column address as shown in the timing chart of FIG. Therefore, paging access according to the purpose can be easily performed, and high-speed drawing can be performed.

Next, the third embodiment will be described with reference to FIGS.

FIG. 16 is a block diagram of a liquid crystal display using the liquid crystal driver of the third embodiment.

In FIG. 16, 1601 is a liquid crystal driver having a built-in display memory, 1602 is a row address counter, and 1603 is a row address counter 16.
2 is an address bus for transferring the row address output to 02, 1604 is a data register, 1605 is a data bus for transferring the data output from the data register, 1606 clocks, and 1607 is a load-type down counter. Yes, 1608 is an enable signal output from the counter 1607, 1609 is an address decoder circuit, 1610 is a register data latch signal (hereinafter also referred to as RAE) output from the address decoder circuit, and 1611 is a load type. It is an up-counter that stores the column address and increments it.

FIG. 17 is a timing chart for explaining the operation when setting data in the data register 1604 in this embodiment.

FIG. 18 shows a liquid crystal driver 16 shown in FIG.
It is a timing chart figure which shows the paging access of 01.

Again, the operation will be described in detail with reference to FIG.

In FIG. 16, the display access operation of the liquid crystal driver 1601 is the same as that of the liquid crystal driver 101 of the first embodiment shown in FIG. 1, and therefore its explanation is omitted here. Therefore, the drawing access will be described. The paging access of the present embodiment is such that the address can be internally generated and high-speed drawing can be performed without inputting the address. When the register address is transferred through the address bus 105 as shown in the timing chart of FIG. 17, the address decoder circuit 1609 enables the register data latch signal 1610. At this time, an address that does not exist in the display memory space is used. Then, the register data latch signal 161
0 captures register data transferred by the data bus 106 in the data register 1604,
Output to 5. In this embodiment, the data is hex. Proceed as 7 Next, when a drawing access occurs as shown in FIG. 18, the row address is fetched into the latch circuit 115 and the counter 1602 in synchronization with the timing of asserting the RAS 107. Then, the column address is loaded into the counter 1611 in synchronization with the timing of asserting the CAS 108. Then, in the counter 1607, the data register 1
The data stored in 604 is fetched. Then, as shown in FIG. 18, a row address h input from the outside is initially input.
ex. n and the column address hex. At m, the drawing access is executed as in the first embodiment. And then, CAS
108 is asserted, the counter 1602 is incremented and the row address hex. n + 1 will be generated. In synchronization with this, the counter 107 counts down and hex. 6 will be stored. CA again
When S108 is asserted, the counter 1602 is incremented and the row address hex. will generate n + 2. In synchronization with this, the counter 107 counts down and hex. 5 will be stored. When this is repeated sequentially and the CAS 108 is asserted, the counter 1602 is incremented to the row address he.
x. When n + 7 is generated, the counter 1 is synchronized with it.
07 counts down and hex. You will remember 0. Then, when CAS is asserted again, the enable signal 1608 generated by the counter 1607 becomes valid, and the counter 1602 determines that the row address hex. Load n and output. Further, in synchronization with this, the counter 1611 is incremented and, as shown in FIG.
x. generate m + 1. In addition, in the counter 1607,
The data he stored in the data register 1604 again
x. Load 7. With such an operation, when the characters shown in FIG. 9 are drawn, the row address can be internally generated without sequentially inputting the row address from the address bus, so that high-speed drawing becomes possible. In addition, after the row address is incremented to a constant value, it is reset to the original row address and the column address is incremented. Therefore, even when characters as shown in FIG. There is an effect that high-speed drawing can be realized without sequentially inputting. Further, since the external address bus does not change, it is effective in reducing the power consumption of the information processing apparatus using the liquid crystal display of this embodiment.

Although the present embodiment has been described with reference to the D-RAM interface in which the row address and the column address are multiplexed, the row address and the column address are simultaneously input without being multiplexed. RAM
An interface compliant with the interface can be realized with the same configuration as this embodiment.

[0077]

The liquid crystal display using the liquid crystal driver of the present invention has a built-in display memory for one screen.
Since the display memory is only accessed once in the horizontal cycle, there is an effect that the power consumption of the liquid crystal display and the information processing device using the liquid crystal driver of the present invention can be promoted.

Further, since the display access to the display memory occurs only once in one horizontal cycle, the drawing access can always be performed, and thus the display data can be updated at high speed.

Further, since the drawing access in the horizontal direction and the vertical direction can be continuously performed by keeping the row address or the column address constant, there is an effect that a drawing image with a character can be drawn at high speed.

Further, since the circuit for generating the drawing address is built in, the address bus is not sequentially input when performing continuous access. Therefore, the liquid crystal display and the information processing apparatus using the liquid crystal driver of the present invention are provided. It has the effect of promoting low power consumption.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a liquid crystal display using a liquid crystal driver of the present invention.

FIG. 2 is a configuration diagram of a liquid crystal display using a conventional liquid crystal driver.

FIG. 3 is a timing chart illustrating the operation of the conventional liquid crystal driver 201 shown in FIG.

FIG. 4 is a block diagram of an information processing device including a liquid crystal display using the conventional liquid crystal driver shown in FIG.

FIG. 5 is a diagram illustrating a memory map of a liquid crystal display.

6 is a timing chart showing a state of access to the display memory shown in FIG.

FIG. 7 is a timing chart diagram of dynamic access for display data writing / reading control to / from a display memory.

FIG. 8 is a timing chart diagram of paging access for display data writing and reading control with respect to a display memory.

FIG. 9 is an example of bitmap data of the character'A '.

10 is a timing chart diagram of a display access for the liquid crystal driver 101 shown in FIG. 1 to supply a liquid crystal applied voltage corresponding to display data to the liquid crystal panel 102. FIG.

11 is a timing chart of a high speed page access of the liquid crystal driver 101 shown in FIG.

12 is a block diagram of an information equipment device configured by using the liquid crystal display shown in FIG.

FIG. 13 is a configuration diagram of a liquid crystal display using a liquid crystal driver that is a second embodiment of the present invention.

14 is a timing chart of a first example of paging access of the liquid crystal driver 1302 shown in FIG.

15 is a timing chart of a second example of paging access by the liquid crystal driver 1302 shown in FIG.

FIG. 16 is a configuration diagram of a liquid crystal display using a liquid crystal driver that is a third embodiment of the present invention.

FIG. 17 is a timing chart illustrating an operation of setting data in a data register 1604 in the liquid crystal driver shown in FIG.

FIG. 18 is a timing chart showing paging access in the liquid crystal driver shown in FIG. 16.

[Explanation of symbols]

 101 ... Liquid crystal driver, 102 ... Liquid crystal panel, 103 ... Scan circuit, 104 ... Power supply circuit, 105 ... Address bus, 106 ... Data bus, 107 ... Latch clock (RAS), 108 ... Latch clock (CAS), 109 ... Write enable Signal (WE), 110 ... Control signal, 111 ... Selection circuit, 112 ... Selection circuit, 113 ... Latch clock, 114 ... Latch clock, 115 ... Latch circuit, 116 ... Latch circuit, 117 ... Address bus, 118 ... Address bus, 119 ... Bidirectional buffer circuit, 120 ... Data bus, 121 ... Synchronous signal (CL1), 122 ... Synchronous signal (FLM), 123 ... Liquid crystal alternating current, 124 ... Scan counter, 125 ... Address bus, 126 ... Selection circuit, 127 … Address bus, 128… Row address Coder, 129 ... Word line selection signal, 130 ... Column address decoder, 131 ... Selection signal, 132 ... Data selection circuit, 133 ... Data bus, 134 ... Memory cell array, 135 ... Data bus, 136 ... Latch circuit, 137 ... Data bus , 138 ... Latch circuit, 139 ... Data bus, 140 ... Level shift circuit, 141 ... Data bus, 142 ... Voltage selection circuit, 143 ... Output terminal, 144 ... Timing signal generation circuit, 145 ... Selection signal, 146 ... Memory access valid Signals, 147 ... Display data latch signals, 148 ... Output terminals, 149 ... Liquid crystal drive voltage, 150 ... Liquid crystal drive voltage, 1201 ... Liquid crystal display, 1202 ... Timing signal generation circuit, 1203 ... Selection signal, 1204 ... Selection circuit.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Hiroyuki Nitta 1099, Ozenji, Aso-ku, Kawasaki, Kanagawa Stock Company, Hitachi, Ltd. System Development Laboratory (72) Makiko Ikeda 1099, Ozenji, Aso-ku, Kawasaki, Kanagawa Hitachi, Ltd. System Development Laboratory (72) Inventor Satoru Tsunekawa 5-20-1 Kamimizuhoncho, Kodaira-shi, Tokyo Hitachi Ltd. Semiconductor Division (72) Inventor Tatsuhiro Inuzuka 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Hitachi Image Information Systems Co., Ltd. (72) Inventor Junichi Miyata, 3681 Hayano, Mobara-shi, Chiba Hitachi Device Engineering Co., Ltd.

Claims (10)

[Claims] 1. A liquid crystal panel having pixel portions arranged in a matrix at intersections of a plurality of data lines and a plurality of scanning lines, a scanning circuit for sequentially applying a selection voltage to the plurality of scanning lines, and a host device. In a liquid crystal display comprising a liquid crystal driver for applying a voltage corresponding to face display data to the plurality of data lines by contracting display data from, the scanning circuit, a slam display synchronization signal representing a frame period of display, and The liquid crystal driver includes a circuit for generating a line display synchronization signal indicating a display line cycle, and the liquid crystal driver is accessed through a general-purpose memory interface to store display data corresponding to the pixel units arranged on the matrix. Display data and display data on one horizontal line are sequentially read out from the display memory by being attributed to the line display synchronization signal. Stage, storage means for simultaneously holding the read display data of the output data line of the liquid crystal driver, and converting the display data held in the storage means into a liquid crystal applied voltage of the liquid crystal panel for output. Circuit, a storage unit for temporarily holding an address corresponding to the scanning line of the liquid crystal panel when the upper device controls display data reading and writing to the display memory, and an address corresponding to the data line. A liquid crystal display, comprising: a storage unit that temporarily stores the data, and a unit that switches a timing signal for fetching an address into the two storage units. 2. The liquid crystal driver multiplexes and inputs an address corresponding to a scanning line and an address corresponding to a data line of the liquid crystal panel, and stores an address corresponding to a scanning line and an address corresponding to a scanning line. And a function of fetching an address corresponding to the data line with a signal for storing an address corresponding to the data line, and a function of fetching an address corresponding to the scanning line with a signal for storing an address corresponding to the data line. , By switching the function of fetching the address corresponding to the data line with the signal that stores the address corresponding to the scanning line, the address corresponding to the scanning line is made constant and the addresses corresponding to the data lines are sequentially input. , The address corresponding to the data line is made constant at the same timing as the function that updates the horizontal display data at high speed. By inputting an address corresponding to the scanning line sequentially, the liquid crystal display of claim 1, wherein the function of updating the vertical direction of the display data at a high speed can be realized. 3. A liquid crystal panel having pixel units arranged in a matrix at intersections of a plurality of data lines and a plurality of scanning lines, a scanning circuit for sequentially applying a selection voltage to the plurality of scanning lines, and a host device. In a liquid crystal display comprising a liquid crystal driver for applying a voltage corresponding to face display data to the plurality of data lines by contracting display data from, the scanning circuit, a slam display synchronization signal representing a frame period of display, and The liquid crystal driver includes a circuit for generating a line display synchronization signal indicating a display line cycle, and the liquid crystal driver is accessed through a general-purpose memory interface to store display data corresponding to the pixel units arranged on the matrix. Display data and display data on one horizontal line are sequentially read out from the display memory by being attributed to the line display synchronization signal. Stage, storage means for simultaneously holding the read display data of the output data line of the liquid crystal driver, and converting the display data held in the storage means into a liquid crystal applied voltage of the liquid crystal panel for output. Circuit, a storage unit that temporarily holds an address corresponding to the scanning line of the liquid crystal panel when the upper device controls display data reading and writing to the display memory, and an address corresponding to the data line. A liquid crystal display having storage means for temporarily storing the number of consecutive accesses, storage means for temporarily storing the number of consecutive accesses, means for counting the number of consecutive accesses, and means for incrementing the temporarily held address. . 4. The liquid crystal driver inputs an address designating a storage means for temporarily holding the number of consecutive accesses from an address bus and a value of the number of consecutive accesses from a data bus. The liquid crystal display according to claim 3. 5. The liquid crystal driver inputs an address corresponding to a scanning line and an address corresponding to a data line once from an address bus, and for successive addresses thereafter, an address is input every time a control signal is input. The liquid crystal display according to claim 3, wherein the liquid crystal display is internally generated. 6. The liquid crystal driver increments the address corresponding to the scanning line by the number of times stored in the storage means by the incrementing unit each time a control signal is input, and the address corresponding to the scanning line is incremented. The liquid crystal display according to claim 3, wherein 7. The liquid crystal driver uses the increment means for incrementing the address corresponding to the data line by the number of times stored in the storage means each time a control signal is input, and the address corresponding to the data line is incremented. The liquid crystal display according to claim 3, wherein 8. The liquid crystal driver, when incrementing the address corresponding to the scanning line by the number of times held in the storage means by the increment means each time a control signal is input, the address corresponding to the data line is obtained. 4. The liquid crystal display according to claim 3, wherein the address corresponding to the scanning line is returned to the initial value again to generate the address. 9. The liquid crystal driver, when incrementing the address corresponding to the data line by the number of times held in the storage means by the increment means each time a control signal is input, the address corresponding to the scanning line is obtained. 4. The liquid crystal display according to claim 3, wherein the address is generated by incrementing by one and returning the address corresponding to the data line to the initial value again. 10. An information processing apparatus comprising a liquid crystal display driven by a liquid crystal driver having the display memory according to claim 1 or 3 as a display device.