JP3264520B2 - Display control device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display control device,
More specifically, the present invention relates to a display control device for a display device including a display element that can maintain a display state updated by applying an electric field, for example, using a ferroelectric liquid crystal as an operating medium for updating a display.

[0002]

2. Description of the Related Art In an information processing system or the like, a display device is used as information display means for performing a visual expression function of information. As such a display device, a CRT display device (hereinafter simply referred to as CRT) is generally used. It is a target.

There are various types of information processing systems available as so-called personal computers and the like depending on the hardware, software, signal transmission system, and the like used therein. In this case, a CRT display control device (CRTC) that is unique to each system is used. As such a CRTC, for example, a VGA (Vi) dedicated to the information processing system PC-AT is used.
VG as a deo Graphics Array)
A81 (by IBM) or 86C as an SVGA (Super VGA) to which an accelerator function or the like for displaying a predetermined image such as a circle or a rectangle is added.
911 (by S3) is known.

FIG. 1 is a block diagram showing an example of a configuration using SVGA for CRTC.

When the host CPU of the information processing system rewrites a part of the display memory window area in the host side memory space, the rewritten display data is transferred to the VRAM 3 via the system bus 40 and the SVGA 1. The SVGA 1 generates a VRAM address based on the address of the display memory window area,
In 3, the display data specified by the VRAM address is rewritten.

On the other hand, the SVGA 1 accesses the VRAM 3 at the same cycle as the scanning cycle on the CRT, and
Display data sequentially read out to the RAMDAC2
Transfer to The RAMDAC 2 sequentially converts the display data into R, G, B analog signals and transfers them to the CRT 4. As described above, the SVGA used as a display control device for a CRT functions to unilaterally transfer display data to the CRT side at a predetermined cycle.

In the case of the CRT display control described above, a VRAM
Reference numeral 3 denotes a dual-port RAM, so that writing of display data to the VRAM for changing display information and the like and reading of display data from the VRAM and display can be performed independently of each other. For this reason,
The host CPU does not need to consider display timing and the like at all, and has an advantage that desired display data can be written at an arbitrary timing.

However, the CRT, in particular, requires a certain length in the thickness direction of the display screen, so that the volume of the CRT as a whole increases, and it is difficult to reduce the size of the entire display device.
Further, this allows a degree of freedom in using an information processing system using such a CRT as a display,
That is, the degree of freedom such as installation location and portability is impaired.

A liquid crystal display (hereinafter, referred to as LCD) can be used as a display device to compensate for this. That is, according to the LCD, it is possible to reduce the size (particularly, the thickness) of the entire display device. Some of such LCDs include
Ferroelectric liquid crystal (hereinafter, FLC: Ferroelectric)
There is a display (hereinafter, referred to as FLCD: FLC display) using an ic Liquid Crystal) liquid crystal cell. One of its features is that the liquid crystal cell has a display state preserving property with respect to application of an electric field. It is in. That is, in the FLCD, the liquid crystal cell is sufficiently thin, and the molecules of the elongated FLC therein are oriented in the first stable state or the second stable state depending on the direction of application of the electric field, and the electric field is removed. However, the respective alignment states are maintained. Due to such bistability of FLC molecules, FLCD
Has memory. Details of such FLC and FLCD are described in, for example, Japanese Patent Application No. 62-76357.

Although the FLCD has the above-mentioned memory characteristics, the speed required for the display update operation of the FLC is relatively slow, so that, for example, cursor movement, character input, scrolling, etc.
In some cases, it is not possible to follow a change in display information that requires immediate rewriting of the display.

An FLCD having such contradictory characteristics
Derives from these characteristics or supplements these characteristics, so that various driving modes for the display are possible. That is, as with the CRT and other liquid crystal displays, the refresh cycle in which the scanning lines on the display screen are sequentially and continuously driven has a relatively long margin in the drive cycle. In addition to the refresh driving, partial rewriting driving for updating the display state of only a portion (line) corresponding to a change on the display screen, and interlacing driving for thinning out scanning lines on the display screen can be performed. Then, by the partial rewriting drive and the interlace drive, it is possible to improve the followability to the change of the display information.

If the display control of the FLCD having the above advantages can be performed by using the existing CRT display control circuit, an information processing system using the FLCD as a display device can be configured at a relatively low cost. It is advantageous.

[0013]

SUMMARY OF THE INVENTION It is an object of the present invention to provide a display control device of an FLCD using a display control circuit for a CRT, which can perform good interlaced display.

[0014]

According to the present invention, there is provided:
A display control device for a display device, comprising a display element capable of holding an updated display state and capable of updating the display state only for a display line related to the display update, a display data storage unit storing display data Holding means for holding an interlace value, and a horizontal synchronizing signal .
In the semi, run each horizontal count-up enable time according to the interlace value held in said holding means
A generating means for generating within a scanning period, and a predetermined clock during a count-up enable time generated by the generating means.
A counter means for counting the click, the value counted by the said counter hand <br/> stage, a predetermined Timing after counting up
An address latch hand <br/> stage for holding the line address in ring, based on the line address held by said address latch means, from the display data storage means data to be displayed on the display line corresponding to the line address Supply means for reading and supplying the read data to the display device.

[0015]

According to the above arrangement, the predetermined clock is counted during the count-up enable time in the horizontal scanning period according to the interlace value held in the holding means, and the counted value is used as the interlace line. Since it is held as an address, an address corresponding to the held interlace value is generated, and an interlaced display based on the display data of this address is performed.

[0016]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 2 is a block diagram of an information processing system using an FLC display device having a display control device according to an embodiment of the present invention as a display device for various characters, image information, and the like.

In FIG. 1, reference numeral 21 denotes a CPU for controlling the entire information processing system; 22, a ROM for storing a program to be executed by the CPU 21; and 28, a main memory used as a work area for executing the program. is there. Reference numeral 14 denotes a DMA controller (Direct Me) for transferring data between the main memory 28 and various devices constituting the system without the intervention of the CPU 21.
memory access controller (hereinafter referred to as DMAC). 32 is Ethernet (XER
OX Corporation) and a LAN interface between the present system and a local area network (LAN) 37. Reference numerals 26 and 27 denote a hard disk device as an external storage device and its interface, and a floppy disk device and its interface, respectively. Reference numeral 36 denotes a printer which can be constituted by an ink jet printer, a laser beam printer, or the like capable of recording at a relatively high resolution, 31 denotes a parallel interface for signal connection between the printer and the present system, and 29 denotes a parallel interface. A keyboard and its controller for inputting character information such as various characters, control information, and the like. Reference numeral 33 denotes a communication modem for performing signal modulation between a communication line and the system of the present embodiment, reference numeral 34 denotes a mouse as a pointing device, and reference numeral 35 denotes an image scanner for reading an image or the like. Exchanging signals with the example system. The interrupt controller 24 controls interrupt processing in program execution, and
Controls the timing function in the present example system. Reference numeral 20 denotes an F whose display is controlled by the FLCD interface 10 as a display control device according to an embodiment of the present invention.
An LC display device (also referred to as an FLCD) having a display screen using the above-described ferroelectric liquid crystal as a display operation medium.
The FLCD interface 10 also has a display memory window area accessible by the CPU 21. Reference numeral 40 denotes a system bus including a data bus, a control bus, and an address bus for signal connection between the above devices.

In the information processing system including the various devices described above connected, generally, the user of the system
The operation is performed while corresponding to various information displayed on the display screen of the FLCD 20. That is, external devices connected to the LAN 37, the hard disk 26, floppy disk 27, scanner 35, keyboard 29, characters supplied from the mouse 34, image information, etc.
The operation information related to the user's system operation stored in 8 is displayed on the display screen of the FLCD 20, and the user performs information editing and instructs the system while viewing this display. Here, the above-mentioned various devices and the like are respectively F
The LCD 20 constitutes a display information supply unit.

FIG. 3 is a block diagram showing details of the FLCD interface 10 according to the first embodiment of the present invention.

As shown in FIG. 1, the FLCD interface 10 of the present embodiment, that is, a display control device, is an SVG using an existing SVGA which is a display control circuit for a CRT.
A1 is used. The configuration of the SVGA 1 of this example will be described with reference to FIG.

In FIG. 4, the rewrite display data accessed by the host CPU 21 (see FIG. 2) for writing in the display memory window area of the interface 10 (see FIG. 2) is transferred via the system bus 40.
It is temporarily stored in the FIFO 101. Further, bank address data for projecting the display memory window area to an arbitrary area of the VRAM 3 is also transferred via the system bus 40. The display data has a form of 24-bit data expressing 256 gradations of each of R, G, and B colors. C
Control information such as a command from the PU 21 and the above-described bank address data is transferred in the form of register set data, and register get data is transferred to the CPU 21 so that the CPU 21 knows the state of the SVGA. The resist set data and the display data stored in the FIFO 101 are sequentially output, and according to the data, the bus interface unit 103 and the VGA 11
It is set in each register in 1. The VGA 111 can know the bank address, its display data, and the control command according to the set state of these registers.

The VGA 111 generates a corresponding VRAM address in the VRAM 3 based on the address of the display memory window area and the bank address,
At the same time, the strobe signals RAS and CAS as memory control signals, the chip select signal CS, and the write enable signal WE are transferred to the VRAM 3 via the memory interface unit 109, thereby writing display data to the VRAM address. be able to. At this time, the display data to be rewritten is similarly transmitted to the VRA via the memory interface unit 109.
Transferred to M3.

On the other hand, the VGA 111 has a VRAM specified by a request line address transferred from the line address generation circuit 7 (see FIG. 3), as will be described in detail later.
3 is read out from the VRAM 3 in response to the line data transfer enable signal similarly transferred, and
Store it in O113. From the FIFO 113, the display data is sent to the FLCD in the order in which it is stored.

The SVGA 1 is provided with the data manipulator 105 and the graphics engine 107 which perform an accelerator function as described above. For example, when the CPU 21 sets data on a circle and its center and radius in a register of the bus interface 103 and instructs drawing of the circle, the graphics engine 10
7 generates the circle display data, and the data manipulator 105 writes the data into the VRAM 3.

The rewrite detection / flag generation circuit 117 has a VG
A111 monitors the VRAM address generated, and
The VRAM address when the display data of M3 is rewritten (written), that is, the VR when the write enable signal and the chip select signal CS become "1".
Take in the AM address. Then, a line address is calculated based on the VRAM address, the VRAM address offset obtained from the CPU 9, the total line number, and the total line bit number. Figure 5 shows the concept of this calculation.
Shown in

A part of the rewrite detection / flag generation circuit 117 is also provided with a circuit for generating an interlace line address according to an interlace value from the CPU 9 as described later.

As shown in FIG. 5, the pixel indicated by the address X on the VRAM 3 corresponds to the line N on the FLCD screen, one line is composed of a plurality of pixels, and one pixel is composed of a plurality of pixels. (N) bytes. At this time, the line address (line number N)
Is calculated as follows:

[0029]

(Equation 1)

The rewrite detection / flag generation circuit 117 sets the flag of the partial rewrite line flag register 119 according to the calculated line address. This is shown in FIG.

As is apparent from FIG. 6, when the display of the corresponding address on the VRAM 3 is rewritten to display, for example, the character "L", the rewritten line address is detected by the above calculation, and this address is detected. Are flagged (set to "1").

Referring again to FIG. 3, the CPU 9 reads the contents of the rewrite line flag register of the rewrite detection / flag generation circuit 117 via the line address generation circuit 7 and changes the line address in which the flag is set to SVG.
Send to A1. At this time, the line address generation circuit sends out a line data transfer enable signal corresponding to the line address data, and
113), the display data of the above address is transferred to the binary halftone processing circuit 11.

The binarized halftone processing circuit 11 comprises R, G, B
The multi-level display data of 256 gradations or 256 colors represented by 8 bits for each color is converted into binary pixel data corresponding to each pixel on the display screen of the FLCD 20. In this example, as shown in FIG. 7, one pixel of the display screen has display cells having different areas for each color. In response to this, the data of one pixel also has 2 bits (R1, R2, G1, G2, B1, B) for each color, as shown in FIG.
2). Therefore, the binary halftone processing circuit 11
The bit display data is converted into binary data of two bits for each color (that is, quaternary data for each color).

FIG. 9 shows the flow of data up to conversion into pixel data for FLCD display as described above.

As apparent from FIG. 9, in this example, the VRA
The display data of M3 is stored as 8-bit multi-value data of each of R, G, and B colors, and is binarized when these are read out and displayed. This allows the host CPU 21 (see FIG. 2) to access the FLCD 20 in the same manner as when using a CRT, thereby ensuring compatibility with the CRT.

A known technique can be used for the binarization halftone processing. Examples of such techniques include an error diffusion method, an average density method, and a dither method. I have.

In FIG. 3, the border generation circuit 13
Pixel data of a border portion on the FLCD display screen is generated. That is, as shown in FIG.
A display screen of 0 indicates that one line consisting of 1280 pixels is 10 lines.
There are twenty-four, and a border portion of the display screen not used for display is formed so as to border the display screen.

By the presence of this border portion, F
The format of the pixel data transferred to the LCD 20 is
FIG. 8 (A) or FIG. 8 (B). FIG.
FIG. 8A shows the data format of the display line A shown in FIG. 7, that is, the display line in which all the display lines are included in the border portion. FIG. 8B shows the display line B shown in FIG. This is the data format of the line used. The data format of display line A is
A line address is added at the head, followed by border pixel data. On the other hand, since both ends of the display line B are included in the border portion, the data format thereof follows the line address, border pixel data, pixel data, and border pixel data in this order.

The border pixel data generated by the border generation circuit 13 is synthesized in series with the pixel data from the binary halftone processing circuit 11 in the synthesis circuit 15. Furthermore, the combined data is sent to the FLCD 20 after the combining line 17 combines the display line address from the line address generating circuit 7.

The CPU 9 controls the entire configuration described above. That is, the CPU 9 is the host CPU 2
1 (see FIG. 2), the total number of lines on the display screen, the total number of line bits, and cursor information are received. Also, CP
U9 supplies the rewrite detection / flag generation circuit 117 with V
Each data of the RAM address offset, the total number of lines and the total number of line bits is transmitted, the line flag register is initialized, and the line address generation circuit 7
Display start line address, number of continuous display lines,
Each data of the total number of lines, the total number of line bits, and the border area is transmitted, and the partial rewrite line flag information is obtained from the circuit 7. Further, the CPU 9 controls the binarized halftone processing circuit 1
The data of the bandwidth, the total number of line bits, and the processing mode are transmitted for 1 and the border pattern data is transmitted to the border generation circuit 13.

The CPU 9 receives status information such as temperature information, trimmer information, and a Busy signal from the FLCD 20, and sends a command signal and a reset signal to the FLCD 20. Further, referring to the refresh mode table 9A, it controls the interlace refresh display described later.

The interlace refresh display control by the FLCD interface 10 described above with reference to FIGS. 3 and 4 will be described below.

FIG. 10 is a schematic diagram showing the refresh mode table shown in FIG.

The refresh display is generally started when the partial rewriting is not performed within a predetermined period, and the ratio between the partial rewriting and the refresh shown in FIG. 10 is determined according to the interlace value. In the table, the interlace value, that is, the number of lines to be thinned out, is obtained by referring to the temperature information and the trimmer information from the FLCD 20.

In general, when the temperature of the FLCD 20 is high and its operation speed is high, the refresh ratio is increased with a small interlace value, and when the temperature is low and the operation speed is low, the partial rewrite ratio is increased with a relatively large interlace value. Set the table to be higher.

FIG. 11 shows a rewrite detection / flag generation circuit 11.
FIG. 7 is a block diagram showing an interlace line address generation circuit provided in 7.

In FIG. 11, the CPU 9 operates in a table 9A.
Are held in the interlace latch 121. Timing generator 123
Generates a count-up enable time of the Hsync counter 125 in accordance with the interlace value held in the interlace latch 121.

FIG. 12 is a block diagram showing details of the timing generator 123. Referring to FIG.
Numeral 31 outputs a decoder having the relationship shown in FIG. 13 according to the interlace value. The output of this decoder 1231 is
Each corresponding AND gate 133 is input. A signal of each bit of the shift register 1233 that shifts in synchronization with a clock is input to the other of the AND gates 133. As a result, the timing generator 123 outputs a count-up enable signal (time) having a length corresponding to each interlace value as shown in FIG.

The Hsync counter 125 counts up in synchronization with the clock during the count-up enable time, and this count value is held by the address latch 127 at a predetermined timing.

The initial register 131 stores Hsync
The initial value (start address) of the counter 125 is held, and the comparator 129 compares the value of the interlace latch 121 with the value of the initial register 131, and when the values are equal, clears the value of the initial register 131.

FIG. 15 is a flowchart showing the flow of the processing of the circuit shown in FIG.

At step S11, the counter 125 is initialized, and at step S12, the value of the interlace latch is decoded by the decoder 1231. Next, each time Hsync becomes "1" in steps S13 and S14, the count is incremented for a count enable time determined according to the decoded interlace value, and the address latch 128 counts, for example, at the falling edge of the enable time. Latch the value. The latched count value is transferred to the line address generation circuit 7 as display line address data for interlaced display. That is, display lines are thinned out according to the count value.

In step S15, the above steps S13 and S1 are repeated until the count value of the counter 125 becomes equal to 1024 or 0, which is the number of display lines of the FLCD 20.
4 are repeated, and when they become equal, the initial address of the initial register 131 is incremented by 1 in step S16. If it is determined in step S17 that the initial address has become equal to the interlace value, the initial address of the initial register 131 is initialized in step S19, and this is set as the initial value of the Hsync counter 125. If the initial address is less than the interlace value, the value is incremented by the counter 125 in step S18.
The initial value of.

FIG. 16 is a block diagram showing another example of the interlace line address generation circuit, and FIG. 17 is a timing chart thereof.

The Hsync counter 203

[0056]

[Outside 1]

The latch 204 latches this count value by a signal of one of timings 1 to 4 transferred from the timing generator 202 via the selector 201, and uses this signal as a display line address. For example, taking timing 1 as an example, as shown in FIG. 17, when the first timing 1 is "1", the counter value is 0, the display line address is 0, and the next timing 1 is "1".
, The display line address is 2, since the counter value is 2. In this case, one interlace display is performed.

The signals 1 to 4 from the timing generator 202 enter the mask timing generation circuit 205 via the selector 201, and the output mask timing is input to the data mask circuit 206. With this, VRAM
The display data from

[0059]

[Outside 2]

[0060]

As is apparent from the above description, according to the present invention, the count of the predetermined clock is counted during the count-up enable time in the horizontal scanning period according to the interlace value held in the holding means. Then, since the counted value is latched as an interlace line address, an address corresponding to the held interlace value is generated, and an interlace display based on the display data of this address is performed.

As a result, good interlace display can be performed with a simple configuration.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a conventional display control device.

FIG. 2 is a block diagram showing an information processing system according to one embodiment of the present invention.

FIG. 3 is a block diagram illustrating a display control device according to the first embodiment of the present invention.

FIG. 4 is a block diagram showing details of an SVGA shown in FIG. 3;

FIG. 5 is a schematic diagram for explaining conversion from a VRAM address to a line address in the embodiment of the present invention.

FIG. 6 is a schematic diagram showing a relationship between a rewrite display pixel and a rewrite line flag register in the embodiment of the present invention.

FIG. 7 is a schematic diagram showing an FLCD display screen according to the embodiment of the present invention.

FIGS. 8A and 8B are schematic diagrams showing a data format of display data according to the embodiment of the present invention.

FIG. 9 is a block diagram illustrating a flow of processing of display data according to the embodiment of the present invention.

FIG. 10 is a schematic diagram of a refresh mode table shown in FIG. 3;

FIG. 11 is a block diagram showing an interlace line address generation circuit according to one embodiment of the present invention.

FIG. 12 is a block diagram showing details of a timing generator shown in FIG. 11;

FIG. 13 is an explanatory diagram for describing a decoding relationship of the decoder illustrated in FIG. 12;

FIG. 14 is a waveform diagram showing a count-up enable time generated by the timing generator.

FIG. 15 is a flowchart showing a flow of processing in the interlace line address generation circuit shown in FIG. 11;

FIG. 16 is a block diagram showing another example of the interlace line address generation circuit.

FIG. 17 is a timing chart of a process in the circuit shown in FIG. 16;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 SVGA 3 VRAM 7 Line address generation circuit 9 CPU 9A Refresh mode table 10 FLCD interface 11 Binary halftone processing circuit 13 Border generation circuit 15, 17 Synthesis circuit 20 FLCD 20A Trimmer 21 CPU / FPU 101, 103 FIFO 103 Bus interface Unit 105 Data manipulator 107 Graphics engine 109 Memory interface unit 111 VGA 117 Rewrite detection / flag generation circuit 119 Partial rewrite line flag register 121 Interlace latch 123 Timing generator 125 Hsync counter 127 Address latch 129 Comparison circuit 131 Initial register 133 AND gate 201 Selector 202 timing generator 203 sync counter 204 latches 205 mask timing generation circuit 206 data mask circuit 1231 decoder 1233 shift register

──────────────────────────────────────────────────続 き Continuing from the front page (72) Inventor Junichi Tanahashi 3-30-2 Shimomaruko, Ota-ku, Tokyo Inside Canon Inc. (72) Inventor Toshiyuki Shingoya 3-30-2, Shimomaruko, Ota-ku, Tokyo Inside Canon Inc. (72) Inventor Morimoto Hajime 3-30-2 Shimomaruko, Ota-ku, Tokyo Canon Inc. (72) Inventor Tatsuya Sakashita 3-30-2 Shimomaruko, Ota-ku, Tokyo Canon Inc. (56) References JP-A-4-3119 (JP, A) JP-A-2-120720 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G09G 3/00-3 / 38 G02F 1/133 505-580

Claims (1)

(57) [Claims] 1. A display control device for a display device, comprising: a display element capable of holding an updated display state, wherein the display state can be updated only for a display line related to the display update, wherein display data is stored. a display data storing means for a holding means for holding the interlace value, based on the horizontal synchronizing signal, generates a count-up enable time according to the interlace value held in said holding means in each horizontal scanning period Generating means; counter means for counting a predetermined clock during the count-up enable time generated by the generating means ; and counting up the value counted by the counter means.
Address latch means for holding as a line address at a later predetermined timing; and reading out display data to be displayed on a display line corresponding to the line address from the display data storage means based on the line address held by the address latch means. And a supply unit for supplying the display device with the display device.