JPH0683292A - Display control device - Google Patents

Abstract

PURPOSE:To enable finely rewriting a comparatively high speed part such as moving of a cursor and the like in display control of an FLCD using a display control circuit for a CRT. CONSTITUTION:Cursor line flag information relating to partial rewriting of cursor display is transferred to a rewriting address generating circuit via a buffer 705 and an all bit OR circuit 703. On the other hand, ordinary partial writing line flag information is inputted to an AND gate 706 via a buffer 704 and an all bit OR circuit 702. While, an inverted signal of an output of the all bit OR circuit 703 relating to cursor display is inputted to the AND gate 706. Thereby, cursor line flag information is preferentially inputted to a writing address generating circuit 701.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display control device,
More specifically, the present invention relates to a display control device for a display device that includes a display element that can maintain a display state updated by applying an electric field or the like using a ferroelectric liquid crystal as an operation medium for display update.

[0002]

2. Description of the Related Art In information processing systems and the like, a display device is used as an information display means having a function of visually expressing information. As such a display device, a CRT display device (hereinafter, simply referred to as CRT) is generally used. Target.

There are various types of information processing systems available as so-called personal computers depending on the hardware, software, signal transmission system, etc. used therein. In this case, the display control device (CRTC) of the CRT is also unique to each system. As such a CRTC, for example, a VGA (Video Graphics Arr) dedicated to an information processing system PC-AT (by IBM) is used.
ay) as a VGA 81 (by IBM) or an SVGA (Super V) to which an accelerator function for displaying a predetermined image such as a circle or a rectangle is added.
86C911 (according to S3 company) as a GA) is known.

FIG. 1 is a block diagram showing an example of a configuration using SVGA for CRTC.

When the host CPU of the information processing system rewrites a part of the display memory window area in the host side memory space, the rewritten display data is transferred to the VRAM 3 via the system bus 40 and the SVGA 1. The SVGA 1 generates a VRAM address based on the address of the display memory window area,
In 3, the display data specified by this VRAM address is rewritten.

On the other hand, the SVGA1 accesses the VRAM3 in the same cycle as the scanning cycle in the CRT, and the VRAM3
The display data that is expanded to are sequentially read, and RAMDAC2
Transfer to. The RAMDAC 2 sequentially converts the display data into R, G, B analog signals and transfers them to the CRT 4. Thus, the SVGA used as the display control device for the CRT functions to unilaterally transfer the display data to the CRT side at a predetermined cycle.

In the case of the above-mentioned CRT display control, VRAM
Since 3 is a dual port RAM, writing of display data to the VRAM for changing display information and the like, and operation of reading the display data from the VRAM and displaying the data can be performed independently of each other. For this reason,
The host CPU has an advantage that desired display data can be written at any timing without any consideration of display timing and the like.

However, since the CRT requires a certain length in the thickness direction of the display screen, the volume of the CRT becomes large as a whole, and it is difficult to reduce the size of the entire display device.
In addition, the degree of freedom in using an information processing system that uses such a CRT as a display is also improved.
That is, the degree of freedom in installation location, portability, etc. is impaired.

A liquid crystal display (hereinafter referred to as LCD) can be used as a display device that compensates for this point. That is, according to the LCD, it is possible to reduce the size (in particular, reduce the thickness) of the entire display device. In such LCD,
Ferroelectric liquid crystal (hereinafter, FLC: Ferroelectric
There is a display (hereinafter, referred to as FLCD: FLC display) using a liquid crystal cell of ic Liquid Crystal), and one of the features is that the liquid crystal cell has a storage state of a display state against the application of an electric field. It is in. That is, in the FLCD, the liquid crystal cell is sufficiently thin, and the elongated FLC molecules therein are oriented in the first stable state or the second stable state depending on the direction of application of the electric field, and excluding the electric field. However, each alignment state is maintained. Due to the bistability of the FLC molecule, the FLCD
Has memory. Details of such FLC and FLCD are described in, for example, Japanese Patent Application No. 62-76357.

Although the FLCD has the above-mentioned memory property, the display update operation of the FLC is relatively slow, and therefore, for example, cursor movement, character input, scrolling, etc.
In some cases, it is not possible to follow the change in the display information that requires the display to be immediately rewritten.

An FLCD having such contradictory characteristics
Are derived from these characteristics or supplement these characteristics, so that various driving modes for display thereof are possible. That is, in the refresh driving in which the scanning lines on the display screen are sequentially and continuously driven like the CRT and other liquid crystal display devices, a relatively long margin can be provided in the driving cycle. In addition to this refresh driving, partial rewriting driving for updating the display state of only a portion (line) corresponding to a change on the display screen and interlaced driving for driving by thinning out scanning lines on the display screen are possible. Then, the partial rewriting drive and the interlace drive can improve the followability to the change of the display information.

If the display control of the FLCD having the above advantages can be performed using the existing CRT display control circuit, an information processing system using the FLCD as a display device can be constructed at a relatively low cost. It is advantageous.

[0013]

An object of the present invention is to provide a display control device capable of favorably performing partial rewriting at a relatively large speed such as cursor movement in display control of an FLCD using a display control circuit for a CRT. And

[0014]

Therefore, according to the present invention,
In a display control device of a display device capable of updating a display state of a display element related to a display change, a display data storage unit storing display data and display data stored in the storage unit And a display control circuit capable of sequentially rewriting the display data stored in the storage means and partially rewriting the display data, and the display control circuit for rewriting the display data. Rewriting detection means for detecting an address to be accessed in the display data storage means, specific pattern rewriting detection means for detecting an address in the display data storage means of display data relating to rewriting of a specific pattern, and the rewriting detection means The address detected by the specific pattern rewriting detection means is given priority over the detected address and transferred to the display control circuit. And rewrite address generating means for transferring display data of the address relating to the transfer by reading from said display data memory means to said display device, characterized in that comprises a.

Further, in a display control device of a display device capable of updating a display state only for a display element associated with a display change, a display data storage unit storing display data and a display data storage unit stored in the storage unit. A display control circuit capable of sequentially reading display data at a predetermined cycle and transferring the display data to the display device, and capable of partially rewriting the display data stored in the storage means, and rewriting of a specific pattern. Specific pattern rewriting detection means for detecting an address in the display data storage means of the display data located at a predetermined position among the plurality of display data according to the above, and the plurality of other than the display data of the address detected by the specific pattern rewriting detection means. Generate address of display data,
Rewriting address generating means for transferring the detected address and the generated address to the display control circuit, reading display data of an address related to the transfer from the display data storage means, and transferring the display data to the display device. It is characterized by that.

Further, in the display control device of the display device capable of updating the display state only for the display element relating to the display change, the display data storage means storing the display data and the display data storage means stored in the storage means. Display data
A display control circuit capable of being sequentially read out at a predetermined cycle and transferred to the display device, and capable of partially rewriting the display data stored in the storage means; and a display control circuit for rewriting the data. In order to detect an address to be accessed in the display data storage means, a specific pattern rewrite detection means for detecting an address in the display data storage means of display data for rewriting a specific pattern, and the specific pattern Of the display data of the address detected by the rewrite detection means, the display data transparently displayed on the display device is provided with a read prohibition means for prohibiting reading by the display control circuit.

[0017]

With the above arrangement, partial rewriting of a specific pattern such as cursor movement is preferentially performed.

Further, the rewriting information of the specific pattern is reduced, and the rewriting process becomes faster.

[0019]

Embodiments of the present invention will now be described in detail with reference to the drawings.

FIG. 2 is a block diagram of an information processing system in which an FLC display device having a display control device according to an embodiment of the present invention is used as a display device for displaying various characters and image information.

In the figure, 21 is a CPU for controlling the entire information processing system, 22 is a ROM for storing a program executed by the CPU 21, and 28 is a main memory used as a work area or the like when the program is executed. is there. Reference numeral 23 denotes a DMA controller (Direct Me) that transfers data between the main memory 28 and various devices constituting the present system without going through the CPU 21.
(more access controller, hereinafter referred to as DMAC). 32 is Ethernet (XER
It is a LAN interface between a LAN (Local Area Network) 37 such as OX Company and this system. Reference numerals 26 and 27 are a hard disk device and its interface and a floppy disk device and its interface as external storage devices, respectively. 36 is a printer which can be constituted by an ink jet printer, laser beam printer or the like capable of relatively high resolution recording, 31 is a parallel interface for making a signal connection between the printer and this system, and 29 is A keyboard and a controller for inputting character information such as various characters and control information. Reference numeral 33 is a communication modem for performing signal modulation between the communication line and the system of this example, 34 is a mouse as a pointing device, and 35 is an image scanner for reading images and the like, which are connected via the serial interface 30. Exchange signals with the system of this example. The interrupt controller 24 controls interrupt processing during program execution, and the real-time clock 25 controls the time counting function in the system of this example. 20 is
FLC as a display control device according to an embodiment of the present invention
An FLC display device (referred to as FLCD) whose display is controlled by the D interface 10 has a display screen using the above-mentioned ferroelectric liquid crystal as its display operation medium. The FLCD interface 10 has a CPU 2
The display memory window area accessible by 1 is also expanded. Reference numeral 40 is a system bus composed of a data bus, a control bus, and an address bus for connecting signals between the above-mentioned devices.

In the information processing system in which the various devices described above are connected, generally, the system user is
The operation is performed while responding to various information displayed on the display screen of the FLCD 20. That is, the external device connected to the LAN 37, the hard disk 26, the floppy disk 27, the scanner 35, the characters supplied from the keyboard 29, the mouse 34, image information, and the main memory 2
The operation information related to the user's system operation stored in 8 is displayed on the display screen of the FLCD 20, and the user edits the information and gives an instruction operation to the system while watching this display. Here, the above various devices are
A display information supply unit is configured for the LCD 20.

First Embodiment FIG. 3 is a block diagram showing details of the FLCD interface 10 according to the first embodiment of the present invention.

As shown in the figure, the FLCD interface 10 of this embodiment, that is, the display control device, uses an existing SVGA which is a display control circuit for a CRT.
A1 is used. The configuration of the SVGA 1 of this example will be described with reference to FIG.

In FIG. 4, the rewrite display data that the host CPU 21 (see FIG. 2) accesses for writing in the display memory window area of the FLCD interface 10 (see FIG. 2) is transferred via the system bus 40, It is temporarily stored in the FIFO 101. Also,
Bank address data for projecting the display memory window area onto an arbitrary area of the VRAM 3 is also stored on the system bus 4.
Transferred via 0. The display data has a form of 24-bit data representing 256 gradations of R, G, and B colors. The control information such as the command from the CPU 21 and the bank address data described above is transferred in the form of register set data, and the register get data is transferred to the CPU 21 side for the CPU 21 to know the state of the SVGA side. The resist set data and display data stored in the FIFO 101 are sequentially output, and the bus interface unit 103 and VG are output according to these data.
It is set in each register in A111. VGA111
The bank address and its display data and control command can be known from the set status of these registers.

The VGA 111 generates a VRAM address in the VRAM 3 corresponding to the address of the display memory window area and the bank address,
At the same time, the strobe signals RAS and CAS as the memory control signals, the chip select signal CS, and the write enable signal WE are transferred to the VRAM 3 via the memory interface unit 109, whereby the display data is written to the VRAM address. be able to. At this time, the display data to be rewritten is similarly VRA via the memory interface unit 109.
Transferred to M3.

On the other hand, the VGA 111 is a VRAM specified by the requested line address transferred from the line address generation circuit 7 (see FIG. 3), as will be described later.
The display data of No. 3 is read from the VRAM 3 in accordance with the line data transfer enable signal similarly transferred, and the FIF
Store in O113. From the FIFO 113, the display data is sent to the FLCD side in the order in which the display data was stored. At this time, the display data is sent out through a circuit for performing partial rewriting for cursor display. This circuit includes a hard cursor control circuit 115, which will be described in detail later, and an AND circuit 1 that performs an AND operation on a signal from this circuit and display data.
19, and an XOR circuit 117 that performs an exclusive OR operation on the output of the AND circuit 119 and the signal from the hard cursor control circuit 15. The hard cursor control 115 performs control such as writing a cursor pattern in the VRAM 3 and superimposing cursor pattern data on display data. The AND pattern memory and the XOR pattern memory used at this time are expanded in the VRAM 3. Further, the display line applied to the non-transparent portion of the cursor display pattern is detected, and the flag of the non-transparent flag register 18 (see FIG. 3) is set based on the detection result.

The SVGA 1 includes, in addition to the cursor display circuit, a data manipulator 105 and a graphics engine 1 having an accelerator function as described above.
07 is provided. For example, when the CPU 21 sets a circle and data regarding the center and radius in the register of the bus interface unit 103 and instructs drawing of the circle, the graphics engine 107 generates the circle display data, and the data manipulator 105 stores this data. Write to VRAM3.

The SVGA 1 described above with reference to FIG.
Is obtained by making a slight modification to the VGA portion of the existing SVGA for CRT.

Referring again to FIG. 3, the rewrite detection / flag generation circuit 5 monitors the VRAM address generated by the SVGA 1, and the VRAM address when the display data of the VRAM 3 is rewritten (written), that is, a write. The VRAM address when the enable signal and the chip select signal CS become "1" is fetched. Then, this VRAM address and the VRA obtained from the CPU 9
A line address is calculated based on each data of M address offset, total line number, and total line bit number. The concept of this calculation is shown in FIG.

As shown in FIG. 5, the pixel indicated by the address X on the VRAM 3 corresponds to the line N of the FLCD screen, one line is made up of a plurality of pixels, and one pixel is made up of a plurality of pixels. It shall consist of (n) bytes. At this time, the line address (line number N)
Is calculated as follows:

[0032]

[Equation 1]

The rewrite detection / flag generation circuit 5 sets the partial rewrite line flag register provided therein according to the calculated line address. This state is shown in FIG.
Shown in.

As is apparent from FIG. 6, in order to display the character "L", for example, when the display of the corresponding address on the VRAM 3 is rewritten, the rewritten line address is detected by the above calculation, and this address is detected. A flag is set in the register corresponding to (1 is set).

As will be described later, the rewrite detection / flag generation circuit is provided with a circuit for performing partial rewrite related to cursor display, in addition to the above-described structure for normal partial rewrite.

The CPU 9 reads the content of the rewrite line flag register of the rewrite detection / flag generation circuit 5 via the line address generation circuit 7 and sends the line address in which the flag is set to the SVGA 1. At this time, the line address generation circuit 7 sends a line data transfer enable signal corresponding to the line address data, and S
The display data of the above address is transferred from the VGA 1 (FIFO 113 thereof) to the binarization halftone processing circuit 11.

Further, the line address generation circuit 7 has a structure in which partial rewriting of the cursor is preferentially performed, as will be described later.

The binarization halftone processing circuit 11 includes R, G, B
The multi-value display data of 256 gradations represented by 8 bits for each color is converted into binary pixel data corresponding to each pixel on the display screen of the FLCD 20. In this example, one pixel of the display screen has display cells having different areas for each color as shown in FIG. Accordingly, the data for one pixel also has 2 bits (R1, R2, G1, G2, B1, B2) for each color, as shown in FIG. Therefore, the binarization halftone processing circuit 11 converts 8-bit display data into 2-bit binary data of each color (that is, 4-value data of each color).

FIG. 9 shows the flow of data until the pixel data for FLCD display is converted as described above.

As is apparent from FIG. 9, in this example, VRA
The display data of M3 is stored as multi-valued data of 8 bits for each color of R, G and B, and is binarized when these are read out and displayed. As a result, the host CPU 21 (see FIG. 2) can access the FLCD 20 side as in the case of using a CRT, and can ensure compatibility with the CRT.

A known method can be used for the binarization halftone processing. As such a method, for example, an error diffusion method, an average density method, a dither method, etc. are known. There is.

In FIG. 3, the border generation circuit 13 is
The pixel data of the border portion on the FLCD display screen is generated. That is, as shown in FIG.
The display screen of 0 has 10 lines per line consisting of 1280 pixels.
There are 24 lines, and a border portion of this display screen that is not used for display is formed so as to frame the display screen.

Due to the existence of this border portion, F
The format of the pixel data transferred to the LCD 20 is
It becomes what is shown in FIG. 8 (A) or FIG. 8 (B). Figure 8
7A shows the data format of the display line A shown in FIG. 7, that is, the display line in which all the display lines are included in the border portion, and FIG. 8B shows the display line B shown in FIG. This is the data format of the line used. The data format of display line A is
A line address is added to the beginning, and this is followed by border pixel data. On the other hand, since both ends of the display line B are included in the border portion, the data format thereof follows the line address, followed by border pixel data, pixel data, and border pixel data in this order.

The border pixel data generated by the border generation circuit 13 is serially synthesized by the synthesis circuit 15 with the pixel data from the binarized halftone processing circuit 11. Further, the combined line 17 is combined with the display line address from the line address generation circuit 7 in the combined circuit 17 and then sent to the FLCD 20.

The CPU 9 controls the entire configuration described above. That is, the CPU 9 is the host CPU 2
1 (see FIG. 2), the total number of lines on the display screen, the total number of line bits, and cursor information are received. Also, CP
U9 sends VRA to the rewrite detection / flag generation circuit 5.
The M address offset, the total number of lines, and the total number of line bits are transmitted, the line flag register is initialized, and the line address generation circuit 7 receives a display start line address, a continuous display line number, The total number of lines, the total number of line bits, and the data of the border area are transmitted, and the partial rewriting line flag information is obtained from the circuit 7. Further, the CPU 9 sends each data of the bandwidth, the total number of line bits and the processing mode to the binarization halftone processing circuit 11 and sends the border pattern data to the border generation circuit 13.

Further, the CPU 9 receives the temperature information and the status signal such as the Busy signal from the FLCD 20, and sends a command signal and a reset signal to the FLCD 20.

In the display control apparatus described above with reference to FIGS. 2 to 9, a configuration for preferential partial rewriting corresponding to a relatively fast movement such as cursor movement will be described below.

FIG. 10 is a block diagram showing details of the rewrite detection / flag generation circuit 5 shown in FIG.

This circuit 5 detects the display data rewriting in the VRAM 3 by the SVGA 1 (see FIG. 3) and sets the flag of this rewriting line, and also transfers the set flag information and the portion related to cursor movement. It has a circuit that detects rewriting (hereinafter, also referred to as cursor rewriting), sets a flag of the rewriting line, and similarly transfers set fluff information.

That is, the flag set circuit 501 is S
The VGA 1 detects the VRAM address to be accessed in the VRAM 3 for rewriting the display, converts this to the line address as described above, and sets the flag corresponding to this line address in the line flag register 504 via the flag interface 503. . Further, the flag read and clear circuit 502 reads the flag information set in the flag register 504 via the flag interface 503 to read the line address generation circuit 7.
(See FIG. 3) and clears the contents of the register for this reading.

On the other hand, the flag of the cursor rewriting line address provided from the CPU 9 (see FIG. 3) to the circuit 5 is similarly set in the cursor flag register 508 via the flag interface 507 by the flag setting circuit 505. In addition, this register 50
The flag set to 8 is the flag interface 5
It is read to the flag read and clear circuit 506 via 07 and transferred to the line address generation circuit 7.

Here, the setting by the flag setting circuit 505 for the cursor will be described in more detail.

When partial rewriting for moving the cursor occurs, only the address (source top line address) of the uppermost line of the cursor pattern before the movement is first transferred to the flag setting circuit 505. The flag setting circuit 505 responds to all other lines (for example, 6
The flag corresponding to the address of (3 lines) is set. The flag read and clear circuit 506 reads out the set flag information in a predetermined order and transfers it to the line address generation circuit 7, and clears the flag of the register for reading. Next, the flag setting circuit 5
Similarly, only the address (destination top line address) of the uppermost line of the moved cursor pattern is transferred to 05 and set in the flag register together with other lines. This set flag information is
It is transferred to the line address generation circuit 7 by the flag read and clear circuit 506, and the flag of the corresponding register is cleared.

If there are overlapping lines in the patterns before and after the cursor movement, there is no problem even with the above-described flag setting and reading procedure, but the flag setting is possible by the processing shown in the flowchart of FIG. 11 below. Is.

That is, when the movement of the cursor is detected in step S11, the larger source top line address and destination line address (lower line on the display screen) is set in the register Y size in steps S12 and S13. Then, set the smaller one to Y small. Next, in step S14, the counter N corresponding to the number of lines of the cursor pattern is reset, and step S
In steps S15, S16, and S17, the flag corresponding to the address of 64 lines from the small Y address is set to "1".

Next, in step S18, it is determined whether or not the lines of the source cursor pattern and the destination cursor pattern overlap each other. If they do not overlap, the counter N is reset in step S19. , In step S20, the difference between 64 and the value obtained by subtracting Y small from Y large is set in the counter N. Then, in steps S21, S22, and S23, a flag is set for each address of Y large + N until N is counted up to 64.

With respect to the flags set as described above, the flag read and clear circuit 506 reads from the flag associated with the address of the source cursor pattern and transfers it to the line address generation circuit 7.

FIG. 12 is a block diagram showing the details of the line address generation circuit 7.

The partial rewriting line flag information and the partial rewriting cursor line flag information transferred from the above-mentioned rewriting detection / flag generation circuit 5 are stored in buffers 704 and 705, respectively. The flag information stored in these buffers 704 and 705 is sent to the rewrite address generation circuit 701 via OR circuits 702 and 703 for all the bits of these buffers, respectively.
An AND circuit 706 is provided in the signal path from the R circuit 702 to the rewrite address generation circuit 701.

The AND circuit 706 receives the data from the all-bit OR circuit 702 and the inversion of the data from the all-bit OR circuit 703. Therefore, the data from the all-bit OR circuit 703, that is, the partial rewriting cursor line flag information is preferentially rewritten to the rewriting address generation circuit 701.
To enter. With such a configuration, partial rewriting related to cursor movement is preferentially performed.

As described above, of the cursor line flag information transferred to the line address generation circuit 7, the flag information related to the line of the source cursor pattern is transferred before the flag related to the destination cursor. As a result, the rewrite address generation circuit 70
1 requests the SVGA1 for the display data of the line address related to the flag information transferred thereafter, and the SCGA1
Reads the display data of this line address and transfers it to the FLCD side as erase data. As a result, the source cursor pattern is erased.

Details of the cursor pattern are shown in FIG. That is, in a pattern in which 64 lines of 64 pixels are formed, “white” surrounds the “black” arrow and other parts are “transparent”. In the modified example described below, partial rewriting is performed only for the "non-transparent" portion of the pattern.

FIG. 14 is a block diagram showing a structure for superimposing the cursor pattern data shown in FIG. 13 on display data. This structure has the circuits and hardware described in FIGS. 3 and 4. Cursor control circuit 11
5, AND circuit 119, XOR circuit 117, AND pattern memory 301, XOR pattern memory 302, and non-transparent line flag 18.

AND pattern memory 301 and XOR
In each address of the pattern memory 302, “0” or “1” corresponding to each pattern as shown in FIG. 15 is written in advance. For example, in the AND pattern memory, "0" is written in the portion corresponding to the arrow of the cursor. First, the hard cursor control circuit 115
The AND circuit 119 sets the contents of the ND pattern memory 301.
And the AND operation with the display data is performed. The AND output is input to the XOR circuit 117, and the XOR operation is performed between the AND output and each content of the XOR pattern memory 302. As a result, each superimpose output as shown in FIG. 15 is obtained. Here, when the output of "transparent" is obtained, the image of the display data is displayed in that portion.

The non-transparent line flag 18 is set with a flag corresponding to a non-transparent output line other than the line in which all the pixels are "transparent" in the cursor pattern. In this flag set, the host CPU 21 writes each data in the AND pattern memory 301 and the XOR pattern memory 302 via the hard cursor control circuit 115. At this time, it is detected which line is all "transparent", the non-transparent line is known based on this, and the flag of that line is set. The flag setting process will be described below with reference to FIG.

In FIG. 16, in step S31, initial values are set to the transparent / non-transparent discrimination parameter F and the pixel addresses X and Y in the cursor pattern (64 × 64). Next, in steps S32, S33, and S34, AN
When the D pattern memory 301 is written, if it is not "1", the parameter F is set to "1", and when the XOR pattern memory 302 is written next in steps S35, S36 and S37, it is When it is not "0", the parameter F is set to "1". Next, by the processing of steps S38 and S39, the F setting processing is repeated for one line, and in step S40, the F value after the processing for the one line is set as the content of the non-transparent line flag. That is, in the processing for one line, if F becomes "1" even once, "1" is set in the flag. This means that at least part of the line has non-transparent parts.

By steps S41 and S42, the above processing is repeated for the number of lines (64 lines), and the non-transparent flag setting processing ends. 17A and 17B show the results of the non-transparent flag set, respectively.

The SVGA1 refers to the non-transparent line flag obtained as described above to generate the above-mentioned cursor rewriting line address, and the flag of the cursor flag register 508 is set based on this.

As another example, it is possible to combine the above two processes for partial rewriting. That is, only the flag related to the address of the uppermost line of the cursor pattern is set, and the line address generation circuit 7 generates the rewrite request address while referring to the non-transparent line flag based on this set flag.

Embodiment 2 Another embodiment for preferentially performing partial rewriting related to cursor movement will be described below.

FIG. 18 is a block diagram showing details of the rewrite detection / flag generation circuit 5 (see FIG. 3) according to this example.

The address accessed by the SVGA 1 (see FIG. 3) in the VRAM 3 for rewriting the display is memory to.
It is stored in the buffer flag register 512 via the line address conversion unit 514. In addition, the cursor address from the CPU 9 is the cursor-to-line address conversion unit 51.
It is stored in the buffer flag register 511 after passing 5.
The flag information of the buffer flag registers 511 and 512 is transferred to the rewrite flag register group 510 in the form of a serial signal as described later.

FIG. 19 shows a rewrite flag register group 510.
3 is a block diagram showing the details of FIG.

The rewrite flag register group 510 includes a rewrite flag register 52 for partial rewriting of the cursor display.
1, a rewrite flag register 522 for partial rewriting for accessing the VRAM, and a refresh address generation unit 523 are provided. Rewrite flag register 5
The flag information of the buffer flag register 511 is set in 21 and the flag information of the buffer flag register 512 is set in the rewrite flag register 522.
The selector 524 appropriately distributes the flag information transferred serially and stores it in each register.

FIG. 20 is a flow chart showing the flow of the display control process according to this example.

In step S201, when a cursor or normal partial write is detected in the VRAM 3, the buffer flag register 511 or 5 is detected in accordance with the write.
A flag is set to the 12 corresponding bits. Next, when the Busy signal from the FLCD 20 is released in step S203, the rewriting flag register 521 for cursor display is scanned in step S204 to determine whether or not there is a bit whose flag is "1".

If a flag is set in any bit of the register 521 in this determination, the line address is preferentially displayed in step S205.
Then, the rewrite flag register 521 corresponding to the line
And the flags of 522 are cleared, and the display data of the line address is transferred in step S206,
Display on the FLCD 20 is performed.

When there is no flag set in the rewrite flag register 521, it is determined whether or not there is a flag set in the rewrite flag register 522. When there is a set flag, the display operation is performed in steps S209 and S209, and when there is no set flag, steps S210 and S21 are performed.
A refresh display is performed with 1.

When one of the three display operations is completed, the buffer flag register 51 is operated at step S212.
The rewrite flag register 52 stores the flag information of 1,512.
Transfer to 1,522.

FIG. 21 shows VRAM addresses and cursor addresses transferred to the rewrite detection / flag generation circuit 5 of this example, and flag sets for the buffer flag registers 512 and 511 corresponding to the transfer of these addresses.
7 is a timing chart showing transfer of flag information of registers 512 and 511.

As shown in FIG. 21, as the VRAM address is transferred at the time points 1A, 2A, 3A, the corresponding flag is set in the buffer flag register 512 at the time points 1C, 2C, 3C. Similarly for the cursor address, the address transferred at time 1B is set in the buffer flag register 511 at time 1D.

Buffer flag registers 512 and 51
The flag information set to 2 is transferred to the rewrite flag registers 521 and 522, respectively, in the form of transfer data shown in FIG. That is, the data of the respective buffer flag registers are transferred at timings shifted from each other by the wavelength and are also transferred serially.

As a result, the rewrite flag registers 521 and 522 before transfer of the buffer flag information shown in FIG.
23 becomes the content shown in FIG. 23 by the above transfer.

[0084]

As is apparent from the above description, according to the present invention, partial rewriting of a specific pattern such as cursor movement is preferentially performed.

Further, the rewriting information of the specific pattern is reduced, and the rewriting process is speeded up.

As a result, it becomes possible to satisfactorily perform partial rewriting at a relatively high speed such as cursor movement.

[Brief description of drawings]

FIG. 1 is a block diagram showing a conventional display control device.

FIG. 2 is a block diagram showing an information processing system according to an embodiment of the present invention.

FIG. 3 is a block diagram showing a display control device according to the first embodiment of the present invention.

FIG. 4 is a block diagram showing details of the SVGA shown in FIG.

FIG. 5 is a schematic diagram for explaining conversion from a VRAM address to a line address in the embodiment of the present invention.

FIG. 6 is a schematic diagram showing a relationship between a rewriting display pixel and a rewriting line flag register in the embodiment of the present invention.

FIG. 7 is a schematic view showing an FLCD display screen in the embodiment of the present invention.

8A and 8B are schematic diagrams showing a data format of display data in the embodiment of the present invention.

FIG. 9 is a block diagram showing a flow of processing of display data in the embodiment of the present invention.

10 is a block diagram showing details of a rewrite detection / flag generation circuit shown in FIG.

11 is a flowchart showing flag setting processing in the rewrite detection / flag generation circuit shown in FIG.

12 is a block diagram showing details of the line address generation circuit shown in FIG.

FIG. 13 is a schematic diagram showing details of a cursor pattern.

FIG. 14 is a block diagram showing a configuration for outputting a superimpose according to the present example.

FIG. 15 is an explanatory diagram for explaining the relationship between the pattern memory used for the superimpose and the superimpose.

FIG. 16 is a flowchart showing a non-transparent line flag setting process according to a modified example of the first embodiment.

17A and 17B are schematic diagrams showing states of flags set by the processing shown in FIG.

FIG. 18 is a block diagram showing a rewrite detection / flag generation circuit according to a second embodiment of the present invention.

19 is a block diagram showing details of a rewrite flag register group shown in FIG.

FIG. 20 is a flowchart showing a flow of display control processing according to the second embodiment.

FIG. 21 is a timing chart of data set and transfer in the above processing.

FIG. 22 is a schematic diagram showing a rewrite flag register before data transfer in the above processing.

FIG. 23 is a schematic diagram showing a rewrite flag register after data transfer in the above processing.

[Explanation of symbols]

 1 SVGA 3 VRAM 5 Rewrite Detection / Flag Generation Circuit 7 Line Address Generation Circuit 9 CPU 10 FLCD Interface 11 Binary Halftone Processing Circuit 13 Border Generation Circuit 15, 17 Synthesis Circuit 18 Nontransparent Line Flag Register 20 FLCD 21 CPU / FPU 101, 103 FIFO 103 Bus interface unit 105 Data manipulator 107 Graphics engine 109 Memory interface unit 111 VGA 115 Hard cursor control circuit 117 XOR circuit 119 AND circuit 301 AND pattern memory 302 XOR pattern memory 501, 505 Flag setting circuit 502, 506 Flag Read and clear circuit 504 Line flag register 508 Cursor flag register 510 Rewrite flag register group 511, 512 Buffer flag register 514 Memory to line address conversion unit 515 Cursor to line address conversion unit 521, 522 Rewrite flag register 523 Refresh address generation unit 524 Selector 701 Rewrite address generation circuit 702, 703 All bit OR circuit

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Kenichiro Ono 3-30-2 Shimomaruko, Ota-ku, Tokyo Canon Inc. (72) Masami Shimakura 3-30-2 Shimomaruko, Ota-ku, Tokyo Canon Incorporated (72) Inventor Morimoto Hajime 3-30-2 Shimomaruko, Ota-ku, Tokyo Canon Inc. (72) Inventor Eiichi Matsuzaki 3-30-2 Shimomaruko, Ota-ku, Tokyo Canon Inc.

Claims (3)

[Claims] 1. A display control device of a display device capable of updating a display state of a display element associated with a display change, a display data storage unit storing display data, and a display stored in the storage unit. A display control circuit capable of sequentially reading out data at a predetermined cycle and transferring the data to the display device, and partially rewriting the display data stored in the storage means, and the display control circuit. Rewriting detection means for detecting an address to be accessed in the display data storage means for the rewriting, and a specific pattern rewriting detection means for detecting an address in the display data storage means of display data relating to rewriting of a specific pattern, The display control is performed by giving priority to the address detected by the specific pattern rewrite detection means over the address detected by the rewrite detection means. Transfer to the road, the display control device, characterized in that the display data of the address related to the transfer equipped with a rewrite address generating means for forwarding to the display device reads from the display data storage means. 2. A display control device of a display device capable of updating a display state only for a display element associated with a display change, and a display data storage unit storing display data, and a display data storage unit stored in the storage unit. A display control circuit capable of sequentially reading display data at a predetermined cycle and transferring the display data to the display device, and capable of partially rewriting the display data stored in the storage means, and rewriting of a specific pattern. Specific pattern rewriting detection means for detecting an address in the display data storage means of the display data located at a predetermined position among the plurality of display data according to the above, and the plurality of display data other than the display data of the address detected by the specific pattern rewriting detection means. An address of display data is generated, and the detected address and the generated address are transferred to the display control circuit. The display control device is characterized in that comprises a rewrite address generating means for transferring display data of the address relating to the transfer by reading from said display data memory means to said display device. 3. A display control device of a display device capable of updating a display state only for a display element associated with a display change, and a display data storage unit storing display data, and a display data storage unit stored in the storage unit. A display control circuit capable of sequentially reading display data at a predetermined cycle and transferring the display data to the display device, and partially rewriting the display data stored in the storage means, and the display control circuit. A rewrite detection means for detecting an address accessed by the display data storage means for the rewriting, and a specific pattern rewrite detection means for detecting an address in the display data storage means of the display data relating to the rewriting of a specific pattern. Of the display data of the addresses detected by the specific pattern rewriting detection means, a table transparently displayed on the display device. For data, the display control device is characterized in that comprises a, a read inhibiting means for inhibiting a read by the display control circuit.