JPS62255989A - Transfer system for data between frame buffers - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a data transfer system between frame buffers in a display control device that controls display on a display screen of a display device such as a CRT.

(Prior Art) A bitmap type CRT display control device generally uses CRT display control equipment.
A plurality of frame buffers are provided to store one screen worth of display data corresponding to the RT display screen. While reading display data from a display frame buffer and displaying it on the CRT display screen, when transferring data from another frame buffer to an arbitrary rectangular area (corresponding to the display screen) of this frame buffer, the CRT's This is done during the blanking period of horizontal scanning and vertical scanning so as not to interfere with the display. Therefore, data transfer cannot be performed during the CRT display period, which accounts for more than 70% of the total time, and data transfer is performed only during the remaining blanking period, which is less than 30% of the total time, resulting in a time-consuming data transfer.

Therefore, as a method for speeding up data transfer, there is a method that uses, for example, the page mode or nibble mode of the dynamic RAM that constitutes the frame buffer. In this method, the above mode is used to read data from the frame buffer for display multiple times in succession, and then sequentially display the data on the CRT display screen via a shift register. However, an empty time is created before the next read, and data transfer is performed within that empty time. As a result, the display frame buffer can be accessed even during display, and about half of the display period can be used for data transfer, thereby increasing speed.

(Problems to be Solved by the Invention) However, in the conventional method, during the display period, the interval between reading display data from the frame buffer using nibble mode and reading the next display data is set. Since data is transferred, there is a problem in that data cannot be transferred continuously. Furthermore, when data corresponding to an arbitrary rectangular area on a display screen is transferred between frame buffers, address control of the transfer destination and control of transfer timing are complicated. Furthermore, when performing multi-window display, when data of a rectangular area is transferred to the display frame buffer, the data that was in the display frame buffer is also needed again, so it must be saved.

Therefore, there is a problem in that data must be transferred twice in order to first save data and then write new data.

The present invention solves the above-mentioned problems, allows data transfer between frame buffers at high speed at continuous timing even during the display period, eliminates the need to specially generate data transfer destination addresses, and allows each frame buffer to The present invention provides a data transfer method between frame buffers that can simultaneously perform data saving and writing in one data transfer with simple control.

(Means for Solving the Problems) In order to solve the above problems, the present invention provides a first frame buffer for storing one screen worth of display data to be output to a display device; A second frame buffer is provided to store display data for one screen in order to rewrite data in an arbitrary area, and reading and writing of each frame buffer is performed in a single manner to display the display on the display screen of the display device. In the display control device to be controlled, a first latch means inputs output data of the first frame buffer to a second frame buffer, and a second latch means inputs output data of the second frame buffer to the first frame buffer.
The latch means determines whether or not the display address for reading data in synchronization with the scanning of the display belongs to an address within the area where data should be rewritten, and if the display address belongs to the address within the area where the data is to be rewritten, the first write signal is output. and a determining means for outputting the display address to at least one of the frame buffer and the second frame buffer, the display address is supplied to the first frame buffer, and an address obtained by adding the display address and a predetermined value is provided to the second frame buffer. By feeding the frame buffer, the first
At the same time as display data is read from the frame buffer of the frame buffer to the display device, data is transferred between the frame buffers via the respective latch means, and the transferred data is written to the address at the time of reading based on the output signal of the discrimination means. It's a lot of work.

(Function) According to the present invention, since the data transfer method between frame buffers is configured as described above, it functions as follows. First, a display address is supplied to the first frame buffer,
At the same time, an address obtained by adding a predetermined value (for example, the difference in the start address of the area where data is to be rewritten between frame buffers) to this display address is supplied to the second frame buffer. As a result, the display data read from the first frame buffer is output to the display and is also input to the second frame buffer via the first latch means. At the same time, data read from the second frame buffer is input to the first frame buffer via the second latch means. In this way, data is read from each frame buffer using display addresses synchronized with the scanning of the display, and data transfer between frame buffers (here, data from output to input) is performed sequentially. The determining means outputs a write signal when the display address belongs to an address within the area to be rewritten.
frame buffer and a second frame buffer. As a result, the data read from the first frame buffer is written to an address obtained by adding a predetermined value to the display address. At the same time, the data read from the second frame buffer is written to the display address. That is, the data in the area to be replaced is replaced between frame buffers so that the data is rewritten. Therefore, since data outside the area cannot be rewritten, only data within the area has been transferred and rewritten. In this way, data transfer can be performed using the entire display period of the display, so the problems of the prior art described above can be solved.

(Embodiment) FIG. 1 is a block diagram showing an embodiment of the present invention,
Bitmap type CR7 with two frame buffers that store display data for one screen as video memory
This shows the main parts of the display control device. In the same figure,
1 is a frame buffer for display, 2 is a main memory (via data bus 15 and multiplexer (MPX) 6).
3 is a WE signal (write enable signal) for controlling writing to frame buffers 1 and 2.
The WE control section 4.5 is a latch that latches data read from each buffer when exchanging data in an arbitrary area between frame buffer 1 and frame buffer 2. 6 is the output terminal (D, ut) of the data bus 15 and the frame buffer 1.
) to the input terminal of the frame buffer 2 (
This is a multiplexer (MPX) that inputs to the input signal (Din).

7 is data input from the output terminal (DO, jt) of the frame buffer 2 via the latch 5, and the data bus 1.
This is a multiplexer (MPX) that selects data from 3 and inputs any of the data to the input terminal (D, .) of the frame buffer 1. 8 selects a DMA address for DMA transfer input via the address bus 14a and a display address input via the address bus 14b for display on the display screen of a CRT (not shown); This is a multiplexer (MPX) that inputs the address of frame buffer 1 into frame buffer 1. 9 is data bus 1
A register 5 to which a predetermined value to be described later is set, an adder 10 that adds the display address and the set value of the register 9, and an adder 11 that selects the DMA address and the address obtained by the adder 10; A multiplexer (MPX) inputs the address of 1 to the frame buffer 2, 12 is a register for reading out the display data to the output terminal (Dout) of the frame buffer 1 and sequentially transferring the display data to the CRT as a video signal, 13 is a register for reading data from the frame buffer 2 a buffer 14a for outputting the data to the data bus 15;
, 14b are address buses for inputting DMA addresses and display addresses, respectively, and 15 is a data bus connected to the CPU, main memory (not shown), and the like.

Frame buffer 1 and frame buffer 2 have independent address buses (14, 14b) and data buses (15), and even when frame buffer 1 is displaying on a CRT, frame buffer 2 is DM with main memory (CPU side).
A transfer can be performed freely. At this time, multiplexer 8 selects the display address, and multiplexer 11 selects the DMA address on the CPU side. In addition, the multiplexer 6 selects the data bus 15 on the CPU side, the display address is stored in the frame buffer 1, and the display address is stored in the frame buffer 2.
DMA address and data are supplied and each operates simultaneously.

Next, data transfer of arbitrary rectangular areas between frame buffers will be explained. FIGS. 2(a) and 2(b) are explanatory diagrams of the operation of this embodiment, and FIG. 3 is a timing diagram of the dynamic RAM constituting the frame buffer 1.2 in read-modify-write mode.

Consider a case where data transfer is performed between frame buffer 1 and frame buffer 2 in the area (shaded area) shown in FIG. 2(a).

First, register 9 stores the above-mentioned predetermined value as the difference (
A'-A: number of words). In the case of FIG. 2(b), address A'- of frame buffer 2 is a smaller address than address A of frame buffer 1, and becomes a negative number, which is set as a two's complement number.

Frame buffer 1 is supplied with a display address selected by multiplexer 8, and frame buffer 2 is supplied with a value obtained by adding the contents of register 9 and the display address by adder 13, selected by multiplexer 11. The frame buffer 2 transfer address is always larger than the frame buffer 1 transfer address (CRT address) when the value of register 9 (the difference between the start addresses of the transfer areas of frame buffer 1 and frame buffer 2) is positive; is always smaller when .

Data read from the frame buffer 1 is set in a shift register 12 for display on a CRT display screen. At the same time, this data is latched by latch 4.

On the other hand, data read from frame buffer 2 is latched by latch 5. In this way, for the display address for displaying on the CRT display screen, the frame buffer 1
The output data of is selected by the multiplexer 6 and supplied to the input terminal (Dio) of the frame buffer 2. At the same time, the output of frame buffer 2 (D,, t
> is selected by multiplexer 7 and sent to frame buffer 1.
is supplied to the input (Din) of At this time, by using the read-modify-write mode in the dynamic RAM shown in FIG.
．． Immediately after latching at step 5, the WE controller 3 activates the WE double signal to rewrite the contents of each frame buffer to the same address as that read from each frame buffer. The data flow at this time is as shown in FIG. 2(b). In the figure, Dl is data read from frame buffer 1,
It is set in the shift register IO to CRT and latch 4, and is supplied to the input of frame buffer 2. D2 is the data read from frame buffer 2, and is set in latch 5 and supplied to the input terminal (Din) of frame buffer 1. be done. At this time, the W1 signal is
Therefore, when the display address reaches point A (frame buffer 1 is address A, frame buffer 2 is address A') in FIG. is connected to address B') and the W1 signal is output, and after passing point B, the W1 signal is not output. Thereafter, when the display address reaches the 6th point of the next raster (address C for frame buffer 1 and address C' for frame buffer 2), the WE multiplication signal becomes active again. In this way, any rectangular area can be transferred. In addition, by controlling the WE multiplied signal supply by the WE control unit 3 corresponding to frame buffer 1 and frame buffer 2, only transfer from frame buffer 1 to frame buffer 2, only transfer from frame buffer 2 to frame buffer 1, Three transfer modes can be realized by exchanging data between frame buffer 1 and frame buffer 2.

Next, details of the WEE control 3 will be explained. W
The internal configuration of the EE control 3 is shown in FIG. Registers 31, 32, and 33 are connected to the data bus 15, and set the start address of the transfer area of data to be rewritten, the number of horizontal words, and the number of vertical bits. Adder 34 generates the start address of the transfer area on each rask. Comparator 3
5 compares the top address of the transfer area on each rask with the display address to determine whether the address has arrived in the transfer area.

The counter 36 counts down the number of words in the horizontal direction and notifies the transfer of consecutive addresses in the horizontal direction with a carry. FF: 18 (flip flop) is comparator 35
It is set by the output of the counter 36 to make the WE flaw signal active and output, and is reset by the output of the counter 36 to stop the WE flaw signal. The counter 37 counts down the number of bits in the vertical direction and indicates completion of rectangular area transfer by a carry. F
F39 is set by the CPU start command and this W
Enable the entire E-control subcommittee. This FF
39 is reset by the carry of counter 37 and WE
Stop E-control 3. OR gate 40 provides a start signal or horizontal synchronization signal to counter 36.

The operation of the WEE control 3 will be explained using the flowchart shown in FIG. A detailed explanatory diagram of the transfer area used here is shown in FIG. First, the start address of the transfer area of the data to be rewritten (point A in FIG. 6), the number of words in the horizontal direction, and the number of bits in the vertical direction of the transfer area are stored in registers 31, 32, and 33 by a command from the CPU via the data bus 15. Set each (step ■). Thereafter, FF9 is set by a start command (start signal) from the CPU, the entire WE control section is enabled, and the operation begins (step 2). At this time, register 3
2.33. The contents of are loaded into counters 36 and 37, respectively (step ■). The start address set in the register 31 and the number of words for one line (fixed data) are added by the adder 34, and the result of this addition is compared with the display address8.
Compare with 35. Note that the value of the start address set in register 31 is actually always the display address, which is the sum of the value set in register 31 and the number of words for one line (fixed data) in adder 4. In order to compare the actual start address and the display address, the number of words for one line is subtracted from the actual start address. In this way, when the CRT scan reaches the start address (point A) of the transfer area, that is, when the display address reaches the start address (value at point A), the comparator 35 matches and the FF 38 is activated. Set (step ■). The output of the FF 38 makes the WE flaw signal active, and the transfer of data to be rewritten between the frame buffer 1 and the frame buffer 2 is started, and the counter 36 is enabled (step 2). At this time, the counter 36 counts down the number of horizontal words in synchronization with the update of the display address, that is, the read clock of the display address, and outputs a carry when the display address reaches point B in FIG. 6 (step ■). . F with this carry
F38 is reset to prohibit data transfer between frame buffers, and the register 31 is set to 1 of the adder 34.
Set the address to which the number of words for the line has been added (step ■). Further, the counter 37 counts down the number of vertical bits set by the start signal (step 2). This completes the transfer of the first line of the rectangular area, the display address is further updated, and the scanning of one line of the display area is completed. At this time, the number of horizontal words is loaded into the counter 36 again using the horizontal synchronization signal. Then the scanning of the next line begins,
When the display address reaches the 0 point in Figure 6, comparator 3 is turned on again.
5 match, FF3B is set, and data transfer between frame buffers in the second row of the rectangular area begins. The above operation is repeated for the number of bits in the vertical direction, and the display address is D in Figure 6.
When the point is reached, the counter 37 outputs a carry and the FF
39 and finish all rectangular area transfers (
Step ■).

(Effects of the Invention) As explained in detail above, according to the present invention, data in arbitrary rectangular areas between frame buffers can be rewritten to be exchanged simultaneously at the same address and timing as the display address for displaying on the CRT display screen. By doing so, you can easily achieve high-speed data transfer between frame buffers.

The transfer of the planned image is completed in the time required for one frame scan. For example, if the frame frequency is 50H2, 2
Full screen transfer is possible in 0ms.

Therefore, CRT
Can be used for multi-land control.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram of an embodiment of the present invention, FIG. 2(a),
(b) is an explanatory diagram of the operation of the embodiment shown in Fig. 1, Fig. 3 is a timing diagram in read/modify/write mode, Fig. 4 is an internal configuration diagram of the WE control section of Fig. 1', and Fig. 5 6 is a flowchart showing the operation of the WE control section, and FIG. 6 is an explanatory diagram of the transfer area. 1.2--Frame buffer, 3-W E control section, 4.5--Latch, 6.7
,8. '11-'? ) Lt + Plexa (MPX), 9.
-Register, 10-Adder, 12-Shift register, 13-Buffer, 14,
, 14b--Address bus, 15--Data bus, 31, 32.33--Register, 34--Adder, 35--Comparator, 36, 37--Counter, 38, 39--Flip-flop ( FF), 40...
Orgate.

Claims (1)

[Claims] A first frame buffer that stores one screen worth of display data to be output to a display device, and one screen worth of display data for rewriting data in an arbitrary area of the first frame buffer. a second frame buffer for storing data, and controls reading and writing of each frame buffer to control display on a display screen of a display device. a first latch means for inputting data to the second frame buffer; and a second latch means for inputting output data of the second frame buffer to the first frame buffer; and a second latch means for inputting output data of the second frame buffer to the first frame buffer; determining whether the display address for the data belongs to an address within the area where data should be rewritten, and if so, outputting a write signal to at least one of the first frame buffer and the second frame buffer. means, supplying the display address to the first frame buffer and supplying an address obtained by adding the display address and a predetermined value to the second frame buffer, thereby transmitting information from the first frame buffer to the display device. A frame characterized in that, at the same time as display data is read, data is transferred between frame buffers via each of the latch means, and the transferred data is written to the address at the time of reading based on the output signal of the discrimination means. Data transfer method between buffers.